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WO2008105437A1 - 半導体装置、リードフレームおよび半導体装置の製造方法 - Google Patents

半導体装置、リードフレームおよび半導体装置の製造方法 Download PDF

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Publication number
WO2008105437A1
WO2008105437A1 PCT/JP2008/053353 JP2008053353W WO2008105437A1 WO 2008105437 A1 WO2008105437 A1 WO 2008105437A1 JP 2008053353 W JP2008053353 W JP 2008053353W WO 2008105437 A1 WO2008105437 A1 WO 2008105437A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor chip
leadframe
lead
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/053353
Other languages
English (en)
French (fr)
Inventor
Yasumasa Kasuya
Motoharu Haga
Shoji Yasunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to US12/528,759 priority Critical patent/US8115299B2/en
Publication of WO2008105437A1 publication Critical patent/WO2008105437A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10W70/424
    • H10W74/014
    • H10W74/111
    • H10W72/0198
    • H10W72/5522
    • H10W74/00
    • H10W74/127
    • H10W90/756

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

 ばりに起因する実装不良の発生を防止することができる、半導体装置およびリードフレーム、ならびにそのリードフレームを用いた半導体装置の製造方法を提供する。半導体装置は、半導体チップと、半導体チップの周囲に配置されて、半導体チップの側面と交差する方向に延び、少なくとも半導体チップから遠い側の端部が実装基板に接合されるリードとを備えている。リードには、実装基板に対する接合面および半導体チップから遠い側の端面で開放される溝が、厚さ方向と直交かつ当該端面に沿う幅方向の全幅にわたって形成されている。そして、溝には、半田からなる埋設体が埋設されている。
PCT/JP2008/053353 2007-02-27 2008-02-27 半導体装置、リードフレームおよび半導体装置の製造方法 Ceased WO2008105437A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/528,759 US8115299B2 (en) 2007-02-27 2008-02-27 Semiconductor device, lead frame and method of manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-047394 2007-02-27
JP2007047394A JP5122835B2 (ja) 2007-02-27 2007-02-27 半導体装置、リードフレームおよび半導体装置の製造方法

Publications (1)

Publication Number Publication Date
WO2008105437A1 true WO2008105437A1 (ja) 2008-09-04

Family

ID=39721262

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053353 Ceased WO2008105437A1 (ja) 2007-02-27 2008-02-27 半導体装置、リードフレームおよび半導体装置の製造方法

Country Status (4)

Country Link
US (1) US8115299B2 (ja)
JP (1) JP5122835B2 (ja)
TW (1) TWI421998B (ja)
WO (1) WO2008105437A1 (ja)

Cited By (1)

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US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices

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WO2011122665A1 (ja) * 2010-03-30 2011-10-06 大日本印刷株式会社 Led用リードフレームまたは基板、半導体装置、およびled用リードフレームまたは基板の製造方法
JP2012023281A (ja) * 2010-07-16 2012-02-02 Nitto Denko Corp 発光装置の製法
JP2012028694A (ja) * 2010-07-27 2012-02-09 Panasonic Corp 半導体装置
US8513787B2 (en) * 2011-08-16 2013-08-20 Advanced Analogic Technologies, Incorporated Multi-die semiconductor package with one or more embedded die pads
US8841758B2 (en) 2012-06-29 2014-09-23 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
DE102013202551A1 (de) 2013-02-18 2014-08-21 Heraeus Materials Technologies GmbH & Co. KG Verfahren zur Herstellung eines Substrats mit einer Kavität
US20140377915A1 (en) * 2013-06-20 2014-12-25 Infineon Technologies Ag Pre-mold for a magnet semiconductor assembly group and method of producing the same
JP6244147B2 (ja) * 2013-09-18 2017-12-06 エスアイアイ・セミコンダクタ株式会社 半導体装置の製造方法
US9578744B2 (en) 2014-12-22 2017-02-21 Stmicroelectronics, Inc. Leadframe package with pre-applied filler material
JP6505540B2 (ja) * 2015-07-27 2019-04-24 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US20170271244A1 (en) * 2016-03-21 2017-09-21 Texas Instruments Incorporated Lead frame with solder sidewalls
JP6603169B2 (ja) * 2016-04-22 2019-11-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP6864440B2 (ja) * 2016-06-15 2021-04-28 ローム株式会社 半導体装置
US20190252256A1 (en) * 2018-02-14 2019-08-15 Nxp B.V. Non-leaded device singulation
US10810932B2 (en) * 2018-10-02 2020-10-20 Sct Ltd. Molded LED display module and method of making thererof
US11545418B2 (en) * 2018-10-24 2023-01-03 Texas Instruments Incorporated Thermal capacity control for relative temperature-based thermal shutdown
JP7243016B2 (ja) * 2019-01-30 2023-03-22 日清紡マイクロデバイス株式会社 半導体装置およびその製造方法
JP7183964B2 (ja) * 2019-06-11 2022-12-06 株式会社デンソー 半導体装置
CN113748510B (zh) * 2019-06-24 2024-03-08 株式会社村田制作所 电子模块
CN112768413B (zh) * 2019-10-21 2022-08-16 珠海格力电器股份有限公司 一种封装基板及半导体芯片封装结构
CN111180412B (zh) * 2020-01-03 2021-05-04 长电科技(宿迁)有限公司 一种侧边开槽的引线框架及其制造方法

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JP2000294719A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP2000294715A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd 半導体装置及び半導体装置の製造方法

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JP2000297415A (ja) * 1999-04-14 2000-10-24 Nippon Haatobiru Kogyo Kk 点字タイル、並びに点字タイル及びその原板の製造方法
MY133357A (en) * 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
JP2001257304A (ja) 2000-03-10 2001-09-21 Matsushita Electric Ind Co Ltd 半導体装置およびその実装方法
JP3628971B2 (ja) * 2001-02-15 2005-03-16 松下電器産業株式会社 リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法
US6841854B2 (en) * 2002-04-01 2005-01-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US7405468B2 (en) * 2003-04-11 2008-07-29 Dai Nippon Printing Co., Ltd. Plastic package and method of fabricating the same
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JP4860939B2 (ja) * 2005-04-08 2012-01-25 ローム株式会社 半導体装置
JP4890804B2 (ja) * 2005-07-19 2012-03-07 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8310060B1 (en) * 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2000294719A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP2000294715A (ja) * 1999-04-09 2000-10-20 Hitachi Ltd 半導体装置及び半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices
US10943885B2 (en) 2015-06-29 2021-03-09 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices

Also Published As

Publication number Publication date
TWI421998B (zh) 2014-01-01
US8115299B2 (en) 2012-02-14
JP5122835B2 (ja) 2013-01-16
JP2008211041A (ja) 2008-09-11
US20100013069A1 (en) 2010-01-21
TW200845351A (en) 2008-11-16

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