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WO2009031522A1 - 半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体 - Google Patents

半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体 Download PDF

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Publication number
WO2009031522A1
WO2009031522A1 PCT/JP2008/065739 JP2008065739W WO2009031522A1 WO 2009031522 A1 WO2009031522 A1 WO 2009031522A1 JP 2008065739 W JP2008065739 W JP 2008065739W WO 2009031522 A1 WO2009031522 A1 WO 2009031522A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor element
phosphorus
barrier metal
conductive
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/065739
Other languages
English (en)
French (fr)
Inventor
Kenichi Kato
Yoshio Shimoaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2009531227A priority Critical patent/JP5113177B2/ja
Priority to CN2008801056350A priority patent/CN101796622B/zh
Priority to US12/676,338 priority patent/US8330271B2/en
Publication of WO2009031522A1 publication Critical patent/WO2009031522A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10W72/012—
    • H10W72/07251—
    • H10W72/20—
    • H10W72/221—
    • H10W72/222—
    • H10W72/223—
    • H10W72/252—
    • H10W72/255—
    • H10W72/29—
    • H10W72/921—
    • H10W72/923—
    • H10W72/934—
    • H10W72/952—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

　機械的な信頼性および電気的な信頼性の両方に優れた半導体素子および該半導体素子の実装構造体を提供する。 　その半導体素子は、基板と、基板上に設けられた導電層と、導電層上に設けられた開口部を有する保護層と、開口部において導電層に接合されたバリアメタル層と、バリアメタル層上に形成された導電性バンプとを有している。このバリアメタル層は、リンを含有しており、かつ該リン含有率が他の部分より大きいリンリッチ部位を含んでいる。このリンリッチ部位は、導電性バンプ側の表面部に位置し、かつ導電性バンプの形成領域の周縁部における厚さが当該形成領域の中央部における厚さより大きい。
PCT/JP2008/065739 2007-09-04 2008-09-02 半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体 Ceased WO2009031522A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009531227A JP5113177B2 (ja) 2007-09-04 2008-09-02 半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体
CN2008801056350A CN101796622B (zh) 2007-09-04 2008-09-02 半导体元件、其制造方法及实装其的实装构造体
US12/676,338 US8330271B2 (en) 2007-09-04 2008-09-02 Semiconductor element, method for manufacturing the same, and mounting structure having the semiconductor element mounted thereon

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-228486 2007-09-04
JP2007228486 2007-09-04
JP2007-281252 2007-10-30
JP2007281252 2007-10-30

Publications (1)

Publication Number Publication Date
WO2009031522A1 true WO2009031522A1 (ja) 2009-03-12

Family

ID=40428838

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/065739 Ceased WO2009031522A1 (ja) 2007-09-04 2008-09-02 半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体

Country Status (5)

Country Link
US (1) US8330271B2 (ja)
JP (1) JP5113177B2 (ja)
CN (1) CN101796622B (ja)
TW (1) TWI452638B (ja)
WO (1) WO2009031522A1 (ja)

Cited By (3)

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JP2011029636A (ja) * 2009-07-02 2011-02-10 Taiwan Semiconductor Manufacturing Co Ltd 銅柱バンプ上の金属間化合物の接合のための方法と構造
US20110315429A1 (en) * 2010-06-24 2011-12-29 Sihai Chen Metal coating for indium bump bonding
JP2023058346A (ja) * 2021-10-13 2023-04-25 三菱電機株式会社 半導体装置および半導体装置の製造方法

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US7847399B2 (en) * 2007-12-07 2010-12-07 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
US9847308B2 (en) * 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8259464B2 (en) * 2010-06-24 2012-09-04 Maxim Integrated Products, Inc. Wafer level package (WLP) device having bump assemblies including a barrier metal
US20120261812A1 (en) * 2011-04-14 2012-10-18 Topacio Roden R Semiconductor chip with patterned underbump metallization
US10784221B2 (en) * 2011-12-06 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of processing solder bump by vacuum annealing
US9368437B2 (en) 2011-12-31 2016-06-14 Intel Corporation High density package interconnects
WO2013101241A1 (en) * 2011-12-31 2013-07-04 Intel Corporation Organic thin film passivation of metal interconnections
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
KR102007780B1 (ko) * 2012-07-31 2019-10-21 삼성전자주식회사 멀티 범프 구조의 전기적 연결부를 포함하는 반도체 소자의 제조방법
KR20140019173A (ko) * 2012-08-06 2014-02-14 삼성전기주식회사 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US9230934B2 (en) * 2013-03-15 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Surface treatment in electroless process for adhesion enhancement
US9576923B2 (en) 2014-04-01 2017-02-21 Ati Technologies Ulc Semiconductor chip with patterned underbump metallization and polymer film
JP2016076533A (ja) * 2014-10-03 2016-05-12 イビデン株式会社 バンプ付きプリント配線板およびその製造方法
TWI562255B (en) * 2015-05-04 2016-12-11 Chipmos Technologies Inc Chip package structure and manufacturing method thereof
US9786634B2 (en) * 2015-07-17 2017-10-10 National Taiwan University Interconnection structures and methods for making the same
JP6519407B2 (ja) * 2015-08-26 2019-05-29 日亜化学工業株式会社 発光装置及び発光装置の製造方法
JP6639188B2 (ja) * 2015-10-21 2020-02-05 ソニーセミコンダクタソリューションズ株式会社 半導体装置、および製造方法
US10586782B2 (en) * 2017-07-01 2020-03-10 International Business Machines Corporation Lead-free solder joining of electronic structures
WO2020085380A1 (ja) * 2018-10-25 2020-04-30 株式会社村田製作所 電子部品モジュール及び電子部品モジュールの製造方法
US11322465B2 (en) * 2019-08-26 2022-05-03 Cirrus Logic, Inc. Metal layer patterning for minimizing mechanical stress in integrated circuit packages
US10991668B1 (en) * 2019-12-19 2021-04-27 Synaptics Incorporated Connection pad configuration of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002203925A (ja) * 2000-12-28 2002-07-19 Fujitsu Ltd 外部接続端子及び半導体装置
JP2006147952A (ja) * 2004-11-22 2006-06-08 Kyocera Corp 半導体素子及び半導体素子実装基板

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JP4720963B2 (ja) * 2001-03-09 2011-07-13 ミネベア株式会社 軸流ファンモータ
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
JP2004273959A (ja) 2003-03-11 2004-09-30 Seiko Epson Corp 半導体チップの製造方法、半導体チップ、半導体装置、電子デバイスおよび電子機器
JP4726409B2 (ja) * 2003-09-26 2011-07-20 京セラ株式会社 半導体素子及びその製造方法
TWI347643B (en) * 2007-06-13 2011-08-21 Advanced Semiconductor Eng Under bump metallurgy structure and die structure using the same and method of manufacturing die structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002203925A (ja) * 2000-12-28 2002-07-19 Fujitsu Ltd 外部接続端子及び半導体装置
JP2006147952A (ja) * 2004-11-22 2006-06-08 Kyocera Corp 半導体素子及び半導体素子実装基板

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029636A (ja) * 2009-07-02 2011-02-10 Taiwan Semiconductor Manufacturing Co Ltd 銅柱バンプ上の金属間化合物の接合のための方法と構造
JP2013131782A (ja) * 2009-07-02 2013-07-04 Taiwan Semiconductor Manufacturing Co Ltd 銅柱バンプ上の金属間化合物の接合のための方法と構造
US20110315429A1 (en) * 2010-06-24 2011-12-29 Sihai Chen Metal coating for indium bump bonding
US9190377B2 (en) * 2010-06-24 2015-11-17 Indium Corporation Metal coating for indium bump bonding
JP2023058346A (ja) * 2021-10-13 2023-04-25 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP7622605B2 (ja) 2021-10-13 2025-01-28 三菱電機株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
US20100252926A1 (en) 2010-10-07
JP5113177B2 (ja) 2013-01-09
JPWO2009031522A1 (ja) 2010-12-16
CN101796622B (zh) 2011-12-28
TWI452638B (zh) 2014-09-11
CN101796622A (zh) 2010-08-04
TW200915457A (en) 2009-04-01
US8330271B2 (en) 2012-12-11

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