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WO2009060670A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2009060670A1
WO2009060670A1 PCT/JP2008/067009 JP2008067009W WO2009060670A1 WO 2009060670 A1 WO2009060670 A1 WO 2009060670A1 JP 2008067009 W JP2008067009 W JP 2008067009W WO 2009060670 A1 WO2009060670 A1 WO 2009060670A1
Authority
WO
WIPO (PCT)
Prior art keywords
section
semiconductor device
extending
insulating film
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/067009
Other languages
English (en)
French (fr)
Inventor
Katsuyuki Torii
Arata Shiomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007291892A external-priority patent/JP4293272B2/ja
Priority claimed from JP2007328672A external-priority patent/JP5098630B2/ja
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to EP08847499.4A priority Critical patent/EP2209142B1/en
Priority to US12/682,383 priority patent/US8207612B2/en
Priority to CN2008801110162A priority patent/CN101821853B/zh
Publication of WO2009060670A1 publication Critical patent/WO2009060670A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H10W72/019—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H10W70/481—
    • H10W72/07532—
    • H10W72/07533—
    • H10W72/07552—
    • H10W72/07553—
    • H10W72/07636—
    • H10W72/07652—
    • H10W72/527—
    • H10W72/5363—
    • H10W72/537—
    • H10W72/5475—
    • H10W72/5522—
    • H10W72/5524—
    • H10W72/5525—
    • H10W72/59—
    • H10W72/622—
    • H10W72/627—
    • H10W72/652—
    • H10W72/871—
    • H10W72/923—
    • H10W72/926—
    • H10W72/934—
    • H10W72/952—
    • H10W72/983—
    • H10W74/00—
    • H10W90/756—
    • H10W90/766—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

　ボンディング強度を確保しつつ、ボンディングに伴う層間絶縁膜（１２）の破壊や電極（１３）の破壊を防止することができ、電気的特性を向上することができる半導体装置及びその製造方法を提供する。半導体装置に搭載された半導体素子（１）は、ゲート電極（１１６）上を覆い第１の方向に延伸する延伸部（１２１）、第２の方向に隣接する延伸部（１２１）同士を第１の方向に一定間隔において連結する連結部（１２２）及び延伸部（１２１）と連結部（１２２）とにより開口形状が規定されベース領域（１１２）の主面とエミッタ領域（１１３）の主面とを露出する開口部（１２３）を有する層間絶縁膜（１２）を備える。また、層間絶縁膜（１２）の延伸部（１２１）下におけるエミッタ領域（１１３）の第２の方向の第１の幅寸法（１２１Ｗ）に比べて、連結部（１２２）下の第１の方向における第２の幅寸法（１２２Ｗ）が大きく設定されている。
PCT/JP2008/067009 2007-11-09 2008-09-19 半導体装置及びその製造方法 Ceased WO2009060670A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP08847499.4A EP2209142B1 (en) 2007-11-09 2008-09-19 Semiconductor device and manufacturing method thereof
US12/682,383 US8207612B2 (en) 2007-11-09 2008-09-19 Semiconductor device and manufacturing method thereof
CN2008801110162A CN101821853B (zh) 2007-11-09 2008-09-19 半导体器件及其制造方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007291892A JP4293272B2 (ja) 2007-11-09 2007-11-09 半導体装置
JP2007-291892 2007-11-09
JP2007-328672 2007-12-20
JP2007328672A JP5098630B2 (ja) 2007-12-20 2007-12-20 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
WO2009060670A1 true WO2009060670A1 (ja) 2009-05-14

Family

ID=40625572

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/067009 Ceased WO2009060670A1 (ja) 2007-11-09 2008-09-19 半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US8207612B2 (ja)
EP (1) EP2209142B1 (ja)
CN (1) CN101821853B (ja)
WO (1) WO2009060670A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020533793A (ja) * 2017-09-11 2020-11-19 ゼネラル・エレクトリック・カンパニイ 半導体素子上に金属層を形成するためのスパッタリングシステムおよび方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102414825B (zh) * 2009-04-28 2014-12-24 三菱电机株式会社 功率用半导体装置
JP6099302B2 (ja) * 2011-10-28 2017-03-22 富士電機株式会社 半導体装置の製造方法
WO2013067270A1 (en) * 2011-11-04 2013-05-10 Invensas Corporation Bonding wedge
CN103151251B (zh) * 2011-12-07 2016-06-01 无锡华润华晶微电子有限公司 沟槽型绝缘栅双极型晶体管及其制备方法
US9306046B2 (en) * 2012-02-22 2016-04-05 Mitsubishi Electric Corporation Semiconductor device having a semiconductor element and a terminal connected to the semiconductor element
CN104124271B (zh) * 2013-04-28 2017-09-12 三垦电气株式会社 半导体装置
JP5729497B1 (ja) 2014-02-04 2015-06-03 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
DE102014107387A1 (de) * 2014-05-26 2015-11-26 Infineon Technologies Ag Halbleiterchip mit verbesserter bondbarkeit und verfahren zur herstellung einer bondverbindung
US9722059B2 (en) * 2015-08-21 2017-08-01 Infineon Technologies Ag Latch-up free power transistor
DE102016116273B4 (de) * 2016-08-31 2024-07-18 Infineon Technologies Austria Ag Halbleiterbauelement und Verfahren zum Bilden eines Halbleiterbauelements
JP6904416B2 (ja) * 2017-06-09 2021-07-14 富士電機株式会社 半導体装置および半導体装置の製造方法
CN110383489B (zh) 2017-09-05 2023-07-04 富士电机株式会社 碳化硅半导体装置及碳化硅半导体装置的制造方法
JP7106981B2 (ja) * 2018-05-18 2022-07-27 富士電機株式会社 逆導通型半導体装置
JP7246287B2 (ja) * 2019-09-13 2023-03-27 株式会社東芝 半導体装置およびその製造方法
EP3907758A1 (en) * 2020-05-08 2021-11-10 Infineon Technologies AG Semiconductor die, semiconductor switching assembly and method of manufacturing
JP7663029B2 (ja) * 2021-06-11 2025-04-16 株式会社デンソー 半導体装置
JP7577623B2 (ja) * 2021-07-12 2024-11-05 ルネサスエレクトロニクス株式会社 半導体装置

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JPH1022322A (ja) * 1996-06-28 1998-01-23 Denso Corp 半導体装置
JP2005303218A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法
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JP2005303218A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法
JP2006140263A (ja) * 2004-11-11 2006-06-01 Sanken Electric Co Ltd 半導体素子及び半導体素子の製造方法
JP2007165635A (ja) * 2005-12-14 2007-06-28 Sanken Electric Co Ltd トレンチ構造半導体装置

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020533793A (ja) * 2017-09-11 2020-11-19 ゼネラル・エレクトリック・カンパニイ 半導体素子上に金属層を形成するためのスパッタリングシステムおよび方法
JP7262448B2 (ja) 2017-09-11 2023-04-21 ゼネラル・エレクトリック・カンパニイ 半導体素子上に金属層を形成するためのスパッタリングシステムおよび方法

Also Published As

Publication number Publication date
EP2209142B1 (en) 2020-05-27
CN101821853B (zh) 2012-06-27
EP2209142A1 (en) 2010-07-21
US20100264546A1 (en) 2010-10-21
EP2209142A4 (en) 2010-11-10
US8207612B2 (en) 2012-06-26
CN101821853A (zh) 2010-09-01

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