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WO1989003088A1 - Ensemble electronique avec circuit d'autocontrole - Google Patents

Ensemble electronique avec circuit d'autocontrole Download PDF

Info

Publication number
WO1989003088A1
WO1989003088A1 PCT/DE1988/000577 DE8800577W WO8903088A1 WO 1989003088 A1 WO1989003088 A1 WO 1989003088A1 DE 8800577 W DE8800577 W DE 8800577W WO 8903088 A1 WO8903088 A1 WO 8903088A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
pseudo
random
circuit
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE1988/000577
Other languages
German (de)
English (en)
Inventor
Joachim Mucha
Hans-Peter Klug
Sven-Axel Nilsson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of WO1989003088A1 publication Critical patent/WO1989003088A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]

Definitions

  • the invention relates to an electronic assembly according to the features of the preamble of claim 1.
  • the modules are caused to output test data (sequences of output data) by applying suitable test patterns (sequences of input data).
  • a comparison with the target test data determines whether the circuit under test is error-free or not. It is possible, for example, to feed the test samples from an automatic test machine via the test object's input pins and to query the test data via the output pins by the automatic test machine. In this case, both the generation of the test samples and the evaluation of the test data take place outside the test object.
  • test methods that provide for internal loading and evaluation of the test pattern.
  • a circuit as a self-test circuit, which consists of a series of flip-flop circuits which are arranged one behind the other for step-by-step operation. There are also direct inputs so that the output state of the circuit depends on current and previous input signals.
  • the output of a circuit is connected to a data input of a digital logic device to be tested, and the output of the digital logic device is connected to the input of a second circuit.
  • the output signals of the The first circuit is thus supplied to the logic module, and each output signal of the logic module is fed to an input of the second circuit, the state of which represents the response of the logic module to each input signal from the first circuit.
  • the known test circuit is arranged on the same integrated circuit module as the microprocessor or other components of the microprocessor.
  • the control signal for generating the test signals must, however, be supplied from outside the module, and the second circuit output must be read and processed outside the module in order to evaluate the test results.
  • the known self-test circuit does not offer any addresses or control information to the circuit to be tested, it is not suitable for checking the functions of an entire microprocessor system.
  • the checking of the functions of an entire microprocessor system requires commands, the generation of addresses and test data and the checking of signals which arise in the entire system.
  • EA-0 135 009 when a microprocessor system is tested with a main microprocessor and an associated main memory, a control is micro-controlled. processor provided with a memory in such a way that the detection of errors and the nature of these errors within the main microprocessor, the main memory and the test arrangement is possible via a display unit and that an interface circuit for establishing a connection between the control microprocessor and those to be tested Circuits are provided so that the control microprocessor can transmit test sequences to the remaining parts of the test arrangement, to the main microprocessor and to the main memory for their checking.
  • a disadvantage of this known arrangement is that a complete control microprocessor with the necessary circuitry is required which carries out a complete test program which is embedded in the main program of the microprocessor to be tested.
  • a complete control microprocessor with the necessary circuitry is required which carries out a complete test program which is embedded in the main program of the microprocessor to be tested.
  • an extraordinarily large number of functions (instructions, operands) and memory spaces are to be tested, which make reliable testing very time-consuming and costly.
  • the invention has for its object to provide an electronic module with a self-test circuit, in which a quick and safe test of modules with complex microprocessor systems is possible with little effort.
  • an electronic assembly of the type mentioned has the features of the characterizing part of claim 1.
  • the arrangement according to the invention can advantageously be used to enable reliable checking of the components of the assembly by using pseudo-random digital signals as the test pattern.
  • By separately applying the buses in the microprocessor system with specific test patterns an optimal adaptation to the functions to be tested is guaranteed.
  • No separate test microprocessor is required to generate the test patterns, which uses parts of the main program in the microprocessor of the module, which makes the self-test circuit very independent of the building blocks to be tested.
  • the test procedure described can also be carried out during other test phases (aging, heat test) by simply attaching the power supply.
  • the circuit design of the test pattern generators for example as a shift register circuit, is known per se from Tietze / Schenk "Semiconductor Circuit Technology", 5th edition, Springer-Verlag 1980, pages 509 to 512.
  • the electronic assembly works particularly advantageously with the self-test circuit if the test procedure according to claim 3 runs in four stages, which are processed one after the other.
  • the buses that are important for the components to be tested are loaded with specific pseudo-random test patterns.
  • control functions can also be tested in a simple manner via the control bus and a sensible check of the memory locations including their neighboring areas can be carried out in the memory modules (ROM, RAM).
  • FIG. 1 being a diagram for the test sequence
  • FIG. 2 shows a block diagram of the self-test circuit with the components to be tested
  • FIG. 3 shows a known embodiment of a test pattern generator
  • FIG. 4 shows an embodiment of a test data evaluation.
  • the sequence of test stages 1 to 4 is indicated by interactions between a self-test circuit STS and the components ⁇ P, ROM, RAM of an electronic assembly to be tested.
  • a self-test circuit STS the components ⁇ P, ROM, RAM of an electronic assembly to be tested.
  • Self-test of the self-test circuit STS in which the most important system functions of the self-test circuit STS, for example the correct output of a test pattern, are tested.
  • the processor module ⁇ P is subjected to a corresponding test pattern consisting of pseudo-random instruction sequences, pseudo-random operands and pseudo-random control signals.
  • the read modules ROM in the exemplary embodiment are supplied with pseudo-random addresses, the contents of which are used to form a signature.
  • the read / write modules RAM are tested with a test pattern that consists of pseudo-random addresses with which a memory area is addressed, pseudo-random data that are written into the memory area, and pseudo-random read / write cycles ⁇ stands.
  • a first test pattern generator TMG1 is connected to the processor module ⁇ P via a data bus DB;
  • a second test pattern generator TMG2 is connected to the processor module ⁇ P via a control bus SB.
  • the processor module ⁇ P is connected to a test data evaluation circuit TDA via the data bus DB, an address bus AB and the control bus SB.
  • Another test pattern generator TMG3, which in its simplest form can also be a digital counter module, is connected via address bus AB to the read module ROM, which also makes the data to be read available to the test data evaluation circuit TDA via a data bus DB poses.
  • a fourth test pattern generator TMG4 which in the simplest case can also be a digital counter or a linear feedback shift register, is connected via the address bus AB to the read / write module RAM, which also reads the read data via the data bus DB of the test data evaluation circuit - TDA provides.
  • the test pattern is thus applied with the aid of a multi-generator concept, in which the data bus DB, the address bus AB and the control bus SB are each subjected to corresponding and different test patterns.
  • the most extensive test pattern is required by the processor module ⁇ P, which therefore requires its own test pattern generator TMG1 for the data bus and another test pattern generator TMG2 for the control bus.
  • test pattern for the data bus can also be used for the data to be read in for the RAM read / write module.
  • a test pattern for the address bus AB is generated with the test pattern generator TMG3, which, as indicated by the dashed connecting line between the output of the test pattern generator TMG2 and the test pattern generator TMG4, also for the
  • FIG. 3 shows a known embodiment of a test pattern generator (compare, for example, Tietze / Schenk "semiconductor circuit technology", 5th edition, Springer-Verlag 1980, pages 509 to 512).
  • the state variables x, ... x are located at the outputs Q of the flip-flop modules FI ... F4. on.
  • the quantities x and x are fed back to the data input D of the first flip-flop module FI via an EXCLUSIVE / * ⁇ DER circuit EXO.
  • the outputs of the flip-flop circuits are each connected to the subsequent input D of the flip-flop modules F2, F3, F4.
  • test data evaluation circuit TDA In the right half of FIG. 4, a detailed representation of an embodiment of the test data evaluation circuit TDA is shown, in which the individual signatures are each evaluated in a linear feedback shift register LFSR, the outputs of which are fed to a further linear feedback shift register LFSR via a multiplexer MUX, which then forms a system signature.
  • the test result can thus be displayed in the form of this system signature.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Microcomputers (AREA)

Abstract

Circuit d'autocontrôle (STS) pour un ensemble électronique permettant non seulement d'assurer le fonctionnement normal de l'ensemble, mais aussi de produire des échantillons d'essai pour les composants à tester (muP, ROM, RAM) de cet ensemble et d'effectuer une évaluation interne au moyen d'un circuit d'évaluation de données d'essai (TDA). Pour que la procédure d'essai puisse être exécutée rapidement et à peu de frais, plusieurs générateurs d'échantillons d'essai (TGM1...TGM4) produisent des signaux numériques pseudo-aléatoires adaptés au composant à tester et aux bus utilisés (DB, AB, SB) dans le cadre d'un système à microprocesseur. L'invention s'applique principalement aux ensembles électroniques à microprocesseurs.
PCT/DE1988/000577 1987-09-25 1988-09-16 Ensemble electronique avec circuit d'autocontrole Ceased WO1989003088A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19873732429 DE3732429A1 (de) 1987-09-25 1987-09-25 Elektronische baugruppe mit einem selbsttestschaltkreis
DEP3732429.2 1987-09-25

Publications (1)

Publication Number Publication Date
WO1989003088A1 true WO1989003088A1 (fr) 1989-04-06

Family

ID=6336924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1988/000577 Ceased WO1989003088A1 (fr) 1987-09-25 1988-09-16 Ensemble electronique avec circuit d'autocontrole

Country Status (4)

Country Link
EP (1) EP0381679A1 (fr)
JP (1) JPH03500344A (fr)
DE (1) DE3732429A1 (fr)
WO (1) WO1989003088A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113742147A (zh) * 2021-08-06 2021-12-03 珠海格力电器股份有限公司 一种电器设备自检方法及装置
US11460502B2 (en) * 2017-06-20 2022-10-04 Phosphil Inc. Processor-based measuring method for testing device under test, and measuring device using same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619512A (en) * 1993-11-08 1997-04-08 Nippondenso Co., Ltd. Integrated circuit having self-testing function

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
EP0135009A2 (fr) * 1983-08-12 1985-03-27 Siemens Aktiengesellschaft Agencement et procédé de test d'un système à microprocesseur
US4670877A (en) * 1983-09-26 1987-06-02 Kabushiki Kaisha Toshiba LSI circuit with self-checking facilitating circuit built therein

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
EP0135009A2 (fr) * 1983-08-12 1985-03-27 Siemens Aktiengesellschaft Agencement et procédé de test d'un système à microprocesseur
US4670877A (en) * 1983-09-26 1987-06-02 Kabushiki Kaisha Toshiba LSI circuit with self-checking facilitating circuit built therein

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11460502B2 (en) * 2017-06-20 2022-10-04 Phosphil Inc. Processor-based measuring method for testing device under test, and measuring device using same
CN113742147A (zh) * 2021-08-06 2021-12-03 珠海格力电器股份有限公司 一种电器设备自检方法及装置
CN113742147B (zh) * 2021-08-06 2024-02-23 珠海格力电器股份有限公司 一种电器设备自检方法及装置

Also Published As

Publication number Publication date
EP0381679A1 (fr) 1990-08-16
DE3732429A1 (de) 1989-04-06
JPH03500344A (ja) 1991-01-24

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