WO1989003088A1 - Electronic assembly with self-test circuit - Google Patents

Abstract

A self-test circuit (STS) for electronic assemblies generates test patterns for the components of the assembly to be tested ($g(m)P, ROM, RAM) outside the normal operation of the assembly and carries out an internal evaluation by means of a test data evaluation circuit (TDA). In order to carry out the testing procedure quickly and at low cost, a plurality of test pattern generators (TGM 1...TGM4) generate pseudo-random digital signals adapted to the component to be tested and to the buses (DB, AB, SB) employed in a microprocessor system. The invention can above all be applied to electronic assemblies comprising microprocessors.

Description

 Electronic assembly with a self-test circuit

The invention relates to an electronic assembly according to the features of the preamble of claim 1.

To ensure and assess their functionality, electronic assemblies are subjected to repeated tests during their manufacture and use. For this purpose, the modules are caused to output test data (sequences of output data) by applying suitable test patterns (sequences of input data). A comparison with the target test data determines whether the circuit under test is error-free or not. It is possible, for example, to feed the test samples from an automatic test machine via the test object's input pins and to query the test data via the output pins by the automatic test machine. In this case, both the generation of the test samples and the evaluation of the test data take place outside the test object. The possibility of being able to directly address those circuit parts for test purposes that are not directly accessible from the outside is offered by test methods that provide for internal loading and evaluation of the test pattern.

It is already known from DE ^ PS 29 02 375 to use a circuit as a self-test circuit, which consists of a series of flip-flop circuits which are arranged one behind the other for step-by-step operation. There are also direct inputs so that the output state of the circuit depends on current and previous input signals. The output of a circuit is connected to a data input of a digital logic device to be tested, and the output of the digital logic device is connected to the input of a second circuit. The output signals of the The first circuit is thus supplied to the logic module, and each output signal of the logic module is fed to an input of the second circuit, the state of which represents the response of the logic module to each input signal from the first circuit. At the end of the test procedure, there is a state at the output of the second circuit which depends on the last input signal and all preceding input signals of the second circuit. This creates a unique output signature, which is characteristic of the successive responses of the logic circuit to the entire test sequence. This output signature can then be compared with a specified test signature at the end of the test sequence in order to determine that the digital logic circuit is free of errors. The coincidence or difference of the output test signature with the given test signature determines whether the circuit is working properly or not.

The known test circuit is arranged on the same integrated circuit module as the microprocessor or other components of the microprocessor. The control signal for generating the test signals must, however, be supplied from outside the module, and the second circuit output must be read and processed outside the module in order to evaluate the test results. Furthermore, since the known self-test circuit does not offer any addresses or control information to the circuit to be tested, it is not suitable for checking the functions of an entire microprocessor system. The checking of the functions of an entire microprocessor system requires commands, the generation of addresses and test data and the checking of signals which arise in the entire system.

In a further known arrangement (EA-0 135 009), when a microprocessor system is tested with a main microprocessor and an associated main memory, a control is micro-controlled. processor provided with a memory in such a way that the detection of errors and the nature of these errors within the main microprocessor, the main memory and the test arrangement is possible via a display unit and that an interface circuit for establishing a connection between the control microprocessor and those to be tested Circuits are provided so that the control microprocessor can transmit test sequences to the remaining parts of the test arrangement, to the main microprocessor and to the main memory for their checking. A disadvantage of this known arrangement is that a complete control microprocessor with the necessary circuitry is required which carries out a complete test program which is embedded in the main program of the microprocessor to be tested. In addition, in the case of more complex microprocessor systems, an extraordinarily large number of functions (instructions, operands) and memory spaces are to be tested, which make reliable testing very time-consuming and costly.

The invention has for its object to provide an electronic module with a self-test circuit, in which a quick and safe test of modules with complex microprocessor systems is possible with little effort.

To solve the problem, an electronic assembly of the type mentioned has the features of the characterizing part of claim 1. The arrangement according to the invention can advantageously be used to enable reliable checking of the components of the assembly by using pseudo-random digital signals as the test pattern. By separately applying the buses in the microprocessor system with specific test patterns, an optimal adaptation to the functions to be tested is guaranteed. No separate test microprocessor is required to generate the test patterns, which uses parts of the main program in the microprocessor of the module, which makes the self-test circuit very independent of the building blocks to be tested. For example, the test procedure described can also be carried out during other test phases (aging, heat test) by simply attaching the power supply. The circuit design of the test pattern generators, for example as a shift register circuit, is known per se from Tietze / Schenk "Semiconductor Circuit Technology", 5th edition, Springer-Verlag 1980, pages 509 to 512.

An advantageous development of the arrangement according to the invention is specified with the features of claim 2.

The electronic assembly works particularly advantageously with the self-test circuit if the test procedure according to claim 3 runs in four stages, which are processed one after the other. In each test level, the buses that are important for the components to be tested are loaded with specific pseudo-random test patterns. In this way, control functions can also be tested in a simple manner via the control bus and a sensible check of the memory locations including their neighboring areas can be carried out in the memory modules (ROM, RAM).

The invention is explained on the basis of the figures, FIG. 1 being a diagram for the test sequence,

2 shows a block diagram of the self-test circuit with the components to be tested, FIG. 3 shows a known embodiment of a test pattern generator and FIG. 4 shows an embodiment of a test data evaluation.

In the diagram according to FIG. 1, the sequence of test stages 1 to 4 is indicated by interactions between a self-test circuit STS and the components μP, ROM, RAM of an electronic assembly to be tested. In the first test stage after the electronic module is switched on

Self-test of the self-test circuit STS, in which the most important system functions of the self-test circuit STS, for example the correct output of a test pattern, are tested. In test stage 2, the processor module μP is subjected to a corresponding test pattern consisting of pseudo-random instruction sequences, pseudo-random operands and pseudo-random control signals. In test stage 3, the read modules ROM in the exemplary embodiment are supplied with pseudo-random addresses, the contents of which are used to form a signature. In the last test stage 4, the read / write modules RAM are tested with a test pattern that consists of pseudo-random addresses with which a memory area is addressed, pseudo-random data that are written into the memory area, and pseudo-random read / write cycles ¬ stands.

In FIG. 2, the necessary elements of the self-test circuit STS are shown in corresponding blocks in connection with the modules μP, ROM, RAM to be tested. A first test pattern generator TMG1 is connected to the processor module μP via a data bus DB; In the same way, a second test pattern generator TMG2 is connected to the processor module μP via a control bus SB. The processor module μP is connected to a test data evaluation circuit TDA via the data bus DB, an address bus AB and the control bus SB. Another test pattern generator TMG3, which in its simplest form can also be a digital counter module, is connected via address bus AB to the read module ROM, which also makes the data to be read available to the test data evaluation circuit TDA via a data bus DB poses. Furthermore, a fourth test pattern generator TMG4, which in the simplest case can also be a digital counter or a linear feedback shift register, is connected via the address bus AB to the read / write module RAM, which also reads the read data via the data bus DB of the test data evaluation circuit - TDA provides. In the exemplary embodiment shown, the test pattern is thus applied with the aid of a multi-generator concept, in which the data bus DB, the address bus AB and the control bus SB are each subjected to corresponding and different test patterns. The most extensive test pattern is required by the processor module μP, which therefore requires its own test pattern generator TMG1 for the data bus and another test pattern generator TMG2 for the control bus. The test pattern for the data bus can also be used for the data to be read in for the RAM read / write module. According to the exemplary embodiment shown, a test pattern for the address bus AB is generated with the test pattern generator TMG3, which, as indicated by the dashed connecting line between the output of the test pattern generator TMG2 and the test pattern generator TMG4, also for the

Addressing of the RAM read / write module can be used.

FIG. 3 shows a known embodiment of a test pattern generator (compare, for example, Tietze / Schenk "semiconductor circuit technology", 5th edition, Springer-Verlag 1980, pages 509 to 512). There are four flip-flop modules FI ... F4 connected in series, which are supplied with a clock T at their clock inputs C. The state variables x, ... x are located at the outputs Q of the flip-flop modules FI ... F4. on. The quantities x and x are fed back to the data input D of the first flip-flop module FI via an EXCLUSIVE / * ΘDER circuit EXO. The outputs of the flip-flop circuits are each connected to the subsequent input D of the flip-flop modules F2, F3, F4. A state table of the state variables x, .... and the size y attributed to the flip-flop module FI must be specified as follows. It is assumed here that in the first state the quantity x, = 1 and the other state quantities x ₂ , X, X = 0.

With each clock pulse, the information is thus shifted one place to the right. It can be seen from the exemplary embodiment shown that the initial state is restored here after every 15th clock pulse; In order to obtain longer period lengths, accordingly longer shift registers must be used.

In the right half of FIG. 4, a detailed representation of an embodiment of the test data evaluation circuit TDA is shown, in which the individual signatures are each evaluated in a linear feedback shift register LFSR, the outputs of which are fed to a further linear feedback shift register LFSR via a multiplexer MUX, which then forms a system signature. The test result can thus be displayed in the form of this system signature.

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3 claims

4 figures

Claims

Claims 1. Electronic assembly - with a self-test circuit which generates off-line internal test signals as test patterns for the modules of the assembly to be tested in each case and carries out an internal evaluation of the result signal, whereby the self-test circuit contains a test data evaluation circuit which contains linear feedback shift registers for generating result signatures, and - The electronic assembly contains at least one microprocessor, that is, that - The test signals are pseudo-random digital signals and that - Test pattern generators (TMG1 ...) are present in the self-test circuit which generate the test patterns specific for the modules to be tested, each with a test pattern generator for the address bus (AB), the data bus (DB) and the control bus (SB) is available. 2. Electronic assembly according to claim 1, d a d u r c h g e k e n n z e i c h n e t that - The result signals of the modules to be tested (μP, ROM, RAM) are each guided via a linear feedback shift register (LFSR) to a multiplexer (MUX) and that - A system signature is formed in another lineaj: feedback shift register following the multiplexer (MUX). 3. Electronic assembly according to claim 1 or 2, d a ¬ d u r c h g e k e n n z e i c h n e t that - in a first test stage after switching on the module, the self-test circuit carries out a self-test, - In a second test stage, the processor (μP) with a test pattern sequence for the data bus (DB), which consists of a pseudo-random instruction sequence and pseudo-random operands exists, and pseudo-random ^' control signals are applied to the control bus (SB), - In a third test stage, the read modules (ROM) are supplied with pseudo-random addresses via the address bus (AB), the contents of which are used to form a signature, and that - In a fourth test stage, the read / write modules (RAM) are tested using a test pattern sequence consisting of: - pseudo-random addresses for the address bus (AB), with which a memory area is addressed, - pseudo-random data, which are read into the memory area via the data bus (DB), and - Pseudo-random read / write cycles that are transmitted via the control bus.