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EP0381679A1 - Ensemble electronique avec circuit d'autocontrole - Google Patents

Ensemble electronique avec circuit d'autocontrole

Info

Publication number
EP0381679A1
EP0381679A1 EP19880907624 EP88907624A EP0381679A1 EP 0381679 A1 EP0381679 A1 EP 0381679A1 EP 19880907624 EP19880907624 EP 19880907624 EP 88907624 A EP88907624 A EP 88907624A EP 0381679 A1 EP0381679 A1 EP 0381679A1
Authority
EP
European Patent Office
Prior art keywords
test
pseudo
random
self
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19880907624
Other languages
German (de)
English (en)
Inventor
Joachim Mucha
Hans-Peter Klug
Sven-Axel Nilsson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0381679A1 publication Critical patent/EP0381679A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]

Definitions

  • the electronic assembly works particularly advantageously with the self-test circuit if the test procedure according to claim 3 runs in four stages, which are processed one after the other.
  • the buses that are important for the components to be tested are loaded with specific pseudo-random test patterns.
  • control functions can also be tested in a simple manner via the control bus and a sensible check of the memory locations including their neighboring areas can be carried out in the memory modules (ROM, RAM).
  • FIG. 2 shows a block diagram of the self-test circuit with the components to be tested
  • FIG. 3 shows a known embodiment of a test pattern generator
  • FIG. 4 shows an embodiment of a test data evaluation.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Microcomputers (AREA)

Abstract

Circuit d'autocontrôle (STS) pour un ensemble électronique permettant non seulement d'assurer le fonctionnement normal de l'ensemble, mais aussi de produire des échantillons d'essai pour les composants à tester (muP, ROM, RAM) de cet ensemble et d'effectuer une évaluation interne au moyen d'un circuit d'évaluation de données d'essai (TDA). Pour que la procédure d'essai puisse être exécutée rapidement et à peu de frais, plusieurs générateurs d'échantillons d'essai (TGM1...TGM4) produisent des signaux numériques pseudo-aléatoires adaptés au composant à tester et aux bus utilisés (DB, AB, SB) dans le cadre d'un système à microprocesseur. L'invention s'applique principalement aux ensembles électroniques à microprocesseurs.
EP19880907624 1987-09-25 1988-09-16 Ensemble electronique avec circuit d'autocontrole Ceased EP0381679A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3732429 1987-09-25
DE19873732429 DE3732429A1 (de) 1987-09-25 1987-09-25 Elektronische baugruppe mit einem selbsttestschaltkreis

Publications (1)

Publication Number Publication Date
EP0381679A1 true EP0381679A1 (fr) 1990-08-16

Family

ID=6336924

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880907624 Ceased EP0381679A1 (fr) 1987-09-25 1988-09-16 Ensemble electronique avec circuit d'autocontrole

Country Status (4)

Country Link
EP (1) EP0381679A1 (fr)
JP (1) JPH03500344A (fr)
DE (1) DE3732429A1 (fr)
WO (1) WO1989003088A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619512A (en) * 1993-11-08 1997-04-08 Nippondenso Co., Ltd. Integrated circuit having self-testing function
KR102039112B1 (ko) * 2017-06-20 2019-10-31 포스필 주식회사 피시험 디바이스를 테스트하기 위한 프로세서 기반의 계측 방법 및 이를 이용한 계측 장치
CN113742147B (zh) * 2021-08-06 2024-02-23 珠海格力电器股份有限公司 一种电器设备自检方法及装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
EP0135009A2 (fr) * 1983-08-12 1985-03-27 Siemens Aktiengesellschaft Agencement et procédé de test d'un système à microprocesseur
JPS6068624A (ja) * 1983-09-26 1985-04-19 Toshiba Corp Ｌｓｉの自己検査装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8903088A1 *

Also Published As

Publication number Publication date
WO1989003088A1 (fr) 1989-04-06
DE3732429A1 (de) 1989-04-06
JPH03500344A (ja) 1991-01-24

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19900307

AK Designated contracting states

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Designated state(s): DE FR GB IT NL

17Q First examination report despatched

Effective date: 19910627

STAA Information on the status of an ep patent application or granted ep patent

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18R Application refused

Effective date: 19911229