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US20230133883A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20230133883A1
US20230133883A1 US17/918,839 US202117918839A US2023133883A1 US 20230133883 A1 US20230133883 A1 US 20230133883A1 US 202117918839 A US202117918839 A US 202117918839A US 2023133883 A1 US2023133883 A1 US 2023133883A1
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electrode
heterojunction
layer
semiconductor device
substrate
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Zilan Li
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Guangdong Zhineng Technologies Co Ltd
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Guangdong Zhineng Technologies Co Ltd
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    • H01L29/7783—
    • H01L29/41—
    • H01L29/66462—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/477—Vertical HEMTs or vertical HHMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/478—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H10P54/00—
    • H10P95/11—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H10W72/01904—
    • H10W72/01951—
    • H10W72/0198—
    • H10W72/944—
    • H10W72/952—

Definitions

  • the present disclosure relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.
  • Group III nitride semiconductors are important semiconductor materials, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, and the like. Due to the advantages of direct band gap, wide band gap, and high breakdown electric field strength, group III nitride semiconductors represented by GaN have broad application prospects in light emitting devices, power electronics, radio frequency devices and other fields.
  • Polar semiconductors have many unique properties. It is particularly important that there are fixed polarized charges on the surface of the polar semiconductor or at the interface of two different polar semiconductors. The presence of these fixed polarized charges can attract movable electron or hole carriers to form two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG. The generation of these two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG does not require an additional electric field, nor does it depend on the doping effect in the semiconductor, and is generated spontaneously.
  • the two-dimensional electron gas or the two-dimensional hole gas at the polar semiconductor interface may have a high surface charge density.
  • the ion scattering and other effects of the two-dimensional electron gas or two-dimensional hole gas are also greatly reduced, so it has high mobility.
  • the high surface charge density and mobility enable the spontaneously generated two-dimensional electron or hole gas at the interface to have good conduction capability and high response speed.
  • this two-dimensional electron gas or two-dimensional hole gas can be used to make high mobility transistors, and its neutral energy is significantly superior to traditional Si or GaAs devices in high energy, high voltage or high frequency applications.
  • the existing structure has many defects, which seriously restricts its application.
  • the present disclosure provides a semiconductor device, comprising: a first channel layer; a first barrier layer, wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode positioned on an upper side of the first heterojunction and configured to have electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the first electrode is connected to a first external voltage above the first heterojunction; and a second electrode positioned at a lower side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the second electrode is connected to a second external voltage below the first heterojunction.
  • the upper side is a portion above the center line position of the first heterojunction; and the lower side is a portion below the center line position of the first heterojunction.
  • the semiconductor device as described above, further comprising a substrate is included below the second electrode.
  • the semiconductor device as described above, wherein the first electrode and the first heterojunction are in Schottky contact; the second electrode is in Ohmic contact with the first heterojunction.
  • the semiconductor device as described above further comprises a third electrode positioned between the first electrode and the second electrode and configured to control a current between the first electrode and the second electrode.
  • the semiconductor device as described above further includes a first nucleation layer configured to form the first channel layer from a substrate.
  • the second electrode is in electrical contact with 2DEG or 2DHG in the first heterojunction through the first nucleation layer.
  • the first nucleation layer is doped.
  • the substrate is a silicon substrate.
  • the semiconductor device as described above further comprises a first interconnection layer, which is positioned above the first heterojunction and electrically connected to the first electrode; and a second interconnection layer positioned below the first heterojunction and electrically connected to the second electrode.
  • the semiconductor device as described above further comprises a third interconnection layer electrically connected to the third electrode.
  • the semiconductor device as described above further comprises a second channel layer; and a second barrier layer, wherein a second heterojunction having a vertical interface is formed between the second channel layer and the second barrier layer, and a vertical 2DEG or 2DHG is formed in the second heterojunction; wherein the first electrode is positioned on an upper side of the second heterojunction and configured to electrically contact 2DEG or 2DHG within the second heterojunction; the second electrode is positioned at a lower side of the second heterojunction and is configured to make electrical contact with 2DEG or 2DHG within the second heterojunction.
  • a method for manufacturing a semiconductor device comprises forming a first nucleation layer at a vertical interface of a substrate; epitaxially growing a first channel layer from the first nucleation layer; epitaxially growing a first barrier layer from the first channel layer, wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; forming a first electrode and a second electrode on an upper side and a lower side of the first heterojunction, respectively, wherein the first electrode is in electrical contact with 2DEG or 2DHG in the first heterojunction, and the second electrode is in electrical contact with 2DEG or 2DHG in the first heterojunction; connecting the first electrode to a first external voltage above the first heterojunction; and connecting the second electrode to a second external voltage below the first heterojunction.
  • the method as described above further comprises forming a third electrode between the first electrode and the second electrode, wherein the third electrode is configured to control a current between the first electrode and the second electrode.
  • the method as described above further comprises connecting the third electrode to a third external voltage above the first heterojunction.
  • the method as described above further comprises forming the second electrode on the lower side of the first heterojunction, forming an insulating layer above the second electrode, and forming the first electrode above the insulating layer.
  • the method as described above further comprises inverting the substrate, forming a hole on the substrate, and exposing the second electrode.
  • the method as described above further comprises turning over the substrate, removing part of the substrate, exposing the first heterojunction, and forming a second electrode on the exposed first heterojunction.
  • the method as described above further comprises turning over the substrate, is removing all the substrates, exposing the first heterojunction, and forming a second electrode on the exposed first heterojunction.
  • the method further comprises turning over the substrate, removing all the substrate and the first nucleation layer, exposing the first heterojunction, and forming a second electrode on the exposed first heterojunction.
  • the method further comprises turning over the substrate, removing all or part of the substrate, exposing the first nucleation layer, and forming a second electrode on the exposed first nucleation layer.
  • the method as described above further comprises forming a second nucleation layer at a vertical interface of the substrate; epitaxially growing a second channel layer from the second nucleation layer; and epitaxially growing a second barrier layer from the second channel layer, wherein a second heterojunction having a vertical interface is formed between the second channel layer and the second barrier layer, and a vertical 2DEG or 2DHG is formed in the second heterojunction; wherein the first electrode is in electrical contact with 2DEG or 2DHG in the second heterojunction, and the second electrode is in electrical contact with 2DEG or 2DHG in the second heterojunction.
  • the semiconductor device of the present disclosure can not only improve the withstand voltage of the device, but also facilitate the circuit interconnection of the semiconductor device.
  • FIG. 1 is a structural diagram of an HEMT according to one embodiment of the present disclosure
  • FIG. 2 A is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure.
  • FIG. 2 B is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure.
  • FIG. 5 AA to FIG. 5 VB are schematic flow charts of a method for preparing a dual channel HEMT according to an embodiment of the present disclosure.
  • FIGS. 6 A- 6 G are flowcharts of a substrate removal method according to one embodiment of the present disclosure.
  • the present disclosure provides a semiconductor device, wherein two electrodes are respectively positioned on both sides of the semiconductor device.
  • a structure can not only improve the withstand voltage of the semiconductor device, but also facilitate the circuit interconnection of the semiconductor device.
  • the substrate can be partially or completely removed, thereby reducing or avoiding the influence of the substrate (especially the heterogeneous substrate, such as a silicon substrate) on the device performance.
  • the semiconductor device proposed by the present disclosure can be a Schottky diode, HEMT, HHMT or other semiconductor devices.
  • HEMT Schottky diode
  • HHMT HHMT or other semiconductor devices.
  • FIG. 1 is a schematic structural diagram of a HEMT according to an embodiment of the present disclosure.
  • the HEMT 100 is a dual-channel device, which includes two vertical two-dimensional electron gas 2DEGs as conductive channels.
  • 2DEGs as conductive channels.
  • FIG. 1 those skilled in the art can fully obtain a single-channel device including only one vertical 2DEG, which is also within the protection scope of the present disclosure.
  • the HEMT 100 includes a substrate 101 , a first nucleation layer 102 A and a second nucleation layer 102 B.
  • the first nucleation layer 102 A and the second nucleation layer 102 B are formed on the opposite vertical interface of the substrate 101 .
  • the nucleation layers 102 A and 102 b may be AlN.
  • the nucleation layer may also include a buffer layer (not shown).
  • the buffer layer may have a single-layer or multi-layer structure, including one or more of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN.
  • the first channel layer 103 A and the second channel layer 103 B are formed by epitaxial growth from the nucleation layers 102 A and 102 B, respectively. Further, the first barrier layer 104 A and the second barrier layer 104 B are formed by epitaxial growth from the first channel layer 103 A and the second channel layer 103 B, respectively.
  • the first barrier layer 104 A is formed on the right side of the first channel layer 103 A, and the two are arranged horizontally to form a first heterojunction therebetween, and a vertical 2DEG is formed in the first heterojunction.
  • the second barrier layer 104 B is formed on the left side of the second channel layer 103 B, and the two are arranged horizontally to form a second heterojunction therebetween, and a vertical 2DEG is formed in the second heterojunction.
  • the surface of the channel layer and the barrier layer grown on the Si (111), Al2O3 (0001) and SiC (0001) planes is the (0001) plane, that is, the direction from the Si substrate to the channel layer and the barrier layer is the ⁇ 0001> crystal direction. In such a crystal direction, there is 2DEG in the channel layer near the interface between the channel layer and the barrier layer.
  • first barrier layer 104 A is formed on the left side of the first channel layer 103 A, or the second barrier layer 104 B is formed on the right side of the second channel layer 103 B, there are two-dimensional hole gas 2DHG in the channel layer near the interface between the channel layer and the barrier layer according to the crystal direction.
  • a dual channel HHMT can be obtained.
  • the first channel layer 103 A and the second channel layer 103 B are partially formed on the side surfaces of the nucleation layers 102 A and 102 B, and extend to occupy the space between the nucleation layers 102 A and 102 B.
  • other portions before the nucleation layers 102 A and 102 B may be filled with an insulating material 112 , such as SiO2 or the like.
  • the portions of the substrate 101 that extend horizontally below and above the nucleation layers 102 A and 102 B may include spacer layers 111 A and 111 B, respectively, to cover the horizontal surface of the substrate 101 and separate the substrate 101 from other parts of the device, thereby further improving the withstand voltage capability.
  • the spacer layers 111 A and 111 B are electrically insulating and include one or more of silicon oxide, silicon nitride, and the like.
  • the shielding layer 113 may be included above the partition layer 111 B extending horizontally above the nucleation layer 102 A.
  • An insulating layer 114 may be included on the shielding layer 113 .
  • the shielding layer 113 and the insulating layer 114 can provide support and protection for the device.
  • the shielding layer 113 and the insulating layer 114 are electrically insulated and include one or more of silicon oxide, silicon nitride, and the like.
  • the first and second channel layers 103 A and 103 B may be defined by holes.
  • the shielding layer 113 may be deposited. The height of the shielding layer 113 may be determined according to the height of the desired heterojunction.
  • a first hole and a second hole may be formed on the shielding layer 113 .
  • the first hole extends downward to expose the nucleation layer 102 A.
  • the first hole extends downward to expose the nucleation layer 102 B.
  • the first and second channel layers 103 A and 103 B may be epitaxially grown from the nucleation layers 102 A and 102 B, and the first and second holes may be filled.
  • the shapes of the first and second channel layers 103 A and 103 B may be defined by the first and second holes.
  • first and second barrier layers 104 A and 104 B may be defined by holes.
  • two other third and fourth holes are formed on the shield layer 113 , exposing the left and right sides of the first and second channel layers 103 A and 103 B, respectively; then, the first and second barrier layers 104 A and 104 B may be epitaxially grown on the side surface of the channel layer exposed in the hole, respectively, and the hole may be filled.
  • the shapes of the first and second barrier layers 104 A and 104 B may also be defined by holes.
  • the heterojunction structure defined by the hole according to the present disclosure has the following advantages: according to the actual needs, a hole structure that can meet the needs can be formed first, and then devices that are difficult to realize by conventional means can be gradually formed in the hole. For example, in the prior art, it is easy to form a structure with a low aspect ratio by epitaxial growth; however, it is often difficult to form a structure with an aspect ratio. When its vertical height is high and its width is small, the traditional epitaxial growth method is difficult to achieve. As disclosed in some embodiments of the present disclosure, such a structure can be easily realized by the hole structure proposed by the present disclosure. On the other hand, a 2DEG having a high height can be formed by groove definition. In the HEMT formed in this way, when the horizontal projection distance between the electrodes is constant, the on current between the source and drain stages is larger, so that it is easier to obtain a high-power HEMT.
  • the aspect ratio of the channel layer to the barrier layer of the semiconductor device of the present disclosure may be 1:2, 1:5, or 1:20.
  • the length of the bottom of both the channel layer and the barrier layer is 1 1 ⁇ m (micrometer)
  • the height of the channel layer 103 and the barrier layer 104 may be 2 ⁇ m, 5 ⁇ m, 20 ⁇ m.
  • any desired aspect ratio can be realized with the help of the hole.
  • the channel layer and the barrier layer are lower than or equal to the height of the hole defined therein.
  • the channel layer and the barrier layer may also extend higher than these holes.
  • the growth of the channel layer and the barrier layer may be more difficult to control due to the loss of the limitation of the hole. Therefore, even if the channel layer and the barrier layer are higher than these holes, the higher height will be limited.
  • the HEMT 100 includes a first electrode 107 and a second electrode 108 .
  • the first electrode 107 is positioned on the upper side of the first heterojunction and is in electrical contact with the 2DEG in the first heterojunction.
  • the upper side mentioned here refers to the part above the center line of the first heterojunction.
  • the horizontal line position at 1 ⁇ 2 of the height is the center line position of the first heterojunction. Refer to the position of the dotted line in FIG. 1 .
  • the region above the center line position is the upper side of the first heterojunction.
  • the first electrode may be positioned at any position on the upper side that can make electrical contact with the vertical 2DEG of the first heterojunction.
  • the first electrode 107 may be in contact with the vertical 2DEG from the upper surface of the first heterojunction as shown in FIG. 1 ; alternatively, the first electrode 107 may be in electrical contact with the 2DEG perpendicular to the first heterojunction from the first barrier layer side; alternatively, the first electrode 107 may be in electrical contact with the 2DEG perpendicular to the first heterojunction from the first channel layer side.
  • the present disclosure is not limited thereto.
  • the second electrode 108 is positioned on the lower side of the first heterojunction and is in electrical contact with the 2DEG within the first heterojunction.
  • the lower side mentioned here refers to the part below the center line of the first heterojunction.
  • the second electrode 108 is in electrical contact with the 2DEG perpendicular to the first heterojunction from the side of the first barrier layer.
  • the first electrode 107 and the second electrode 108 are as far away as possible to maximize the length of the vertical conductive channel and improve the voltage withstand performance of the device.
  • the projection of the first electrode and its connecting conductor on the vertical channel plane does not overlap the projection of the second electrode and its connecting conductor on the vertical channel plane. Further, on the third plane perpendicular to the vertical channel plane and the horizontal plane, the projection of the first electrode and its connecting conductor on the vertical channel plane does not overlap with the projection of the second electrode and its connecting conductor on the vertical channel plane.
  • the first electrode 107 and the second electrode 108 are also in electrical contact with the vertical 2DEG of the second heterojunction as the other channel, thereby forming a dual channel semiconductor device.
  • the increased conductive channel can increase the on current and thus have higher power; moreover, the double conductive channel has better pressure resistance and heat resistance than the single conductive channel
  • the same attribute electrodes of the double conductive channel structure may be shared.
  • the first electrode 107 in FIG. 1 includes two parts corresponding to the first heterojunction and the second heterojunction, these two parts are electrically connected to the same conductor interconnection layer, and thus can be considered as one electrode.
  • one of the first electrode 107 and the second electrode 108 may be in ohmic contact with the first and second heterojunction; the other is in contact with the first and second heterojunction Schottky, and forms a Schottky diode by using the characteristics of the Schottky contact, which is also a semiconductor device protected by the present disclosure.
  • a first conductor interconnection layer 131 is included, which is electrically connected to the first electrode 107 .
  • the first conductor interconnection layer 131 is also positioned on the upper side of the first heterojunction. The fabrication and interconnection of the first conductor interconnection layer 131 are well known to those skilled in the art and will not be described here again.
  • the lower part of the first heterojunction shown in FIG. 1 includes a second conductor interconnection layer 132 , which is electrically connected to the second electrode 108 .
  • the second conductor interconnection layer 132 is also positioned on the lower side of the second heterojunction.
  • the second conductor interconnection layer 132 can be formed in various ways and electrically connected to the second electrode 108 .
  • the semiconductor device shown in FIG. 1 the semiconductor device shown in FIG.
  • the second conductor interconnection layer 132 may be formed on the substrate 101 by depositing metal or the like, and the through hole may be filled to electrically connect the second conductor interconnection layer 132 and the second electrode 108 , thereby obtaining the structure shown in FIG. 1 .
  • the HEMT 100 further includes a third electrode 109 .
  • the third electrode 109 is provided between the first electrode 107 and the second electrode 108 .
  • As a gate electrode it is possible to control the current intensity between the first electrode 107 and the second electrode 108 to form a HEMT structure.
  • the voltage of the third electrode 109 can control the depth of the heterojunction potential well formed by the channel layer barrier layer, control the surface charge density of 2DEG in the potential well, and further control the working current between the first electrode 107 and the second electrode 108 .
  • the length of the third electrode 109 extending horizontally is not less than the length of the 2DEG 105 A to realize the control of the current path between the first electrode 107 and the second electrode 108 .
  • the second electrode 108 is in ohmic contact with the first and second channel layers 103 A and 103 B and the first and second barrier layers 104 A and 104 B, and is preferably connected to a high voltage as a drain.
  • the first electrode 107 is also in ohmic contact, and is preferably used as a source electrode as far as possible from the drain electrode of the second electrode.
  • the center line position of the third electrode 109 is also positioned on the upper side of the first heterojunction, and is as close to the first electrode 107 as possible, so as to increase the distance between the drain and the gate, and effectively improve the withstand voltage performance of the HEMT 100 .
  • a third conductor interconnection layer 133 is included, which is electrically connected to the third electrode 109 .
  • the third conductor interconnection layer 133 is also positioned on the upper side of the first heterojunction. The fabrication and interconnection of the third conductor interconnection layer 133 are well known to those skilled in the art and will not be described here. Referring to FIG. 1
  • the projection of the third electrode and its connecting conductor on the vertical channel plane does not overlap with the projection of the second electrode and its connecting metal on the vertical channel plane
  • the projection of the third electrode and its connecting conductor on the third plane does not overlap with the projection of the second electrode and its connecting metal on the third plane.
  • the interconnection structure of the third electrode 109 passes through the interconnection structure of the first electrode 107 , and the entire interconnection structure is positioned within the area defined by the first electrode 107 . In this way, there is no need to occupy additional chip area and is conducive to improving the integration of the device.
  • FIGS. 2 A and 2 B are schematic structural diagrams of an HEMT according to another embodiment of the present disclosure.
  • HEMT 200 is also a dual channel device.
  • the structure of the HEMT 200 is similar to that of the HEMT 100 shown in FIG. 1 , and includes a substrate 201 , first and second nucleation layers 202 A and 202 B, first and second channel layers 203 A and 203 B, and first and second barrier layers 204 A and 204 B; Wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers 203 A and 203 B and the first and second barrier layers 204 A and 204 B, respectively.
  • portions of the substrate 201 extending horizontally above and below the first and second nucleation layers 202 A and 202 B include separation layers 211 A and 211 B, respectively, to separate the substrate 201 from other portions of the device.
  • the HEMT 200 further includes an insulating material 212 between the first and second barrier layers 204 A and 204 B, and a shielding layer 213 above the spacer layer 211 B and a protective layer 214 above the shielding layer 213 .
  • the HEMT 200 further includes a first electrode 207 , a second electrode 208 and a third electrode 209 . Parts similar to the structure of the embodiment shown in FIG. 1 have similar functions, and will not be described here.
  • the difference from the embodiment shown in FIG. 1 is that the first and second channel layers 203 A and 203 B and the first and second barrier layers 204 A and 204 B are positioned above the first and second nucleation layers 202 A and 202 B, so that the first and second heterojunctions are further away from the substrate 201 . This can further improve the performance of the HEMT 200 .
  • the second conductor interconnection layer 232 is shown in FIGS. 2 A and 2 B , but the first and third conductor interconnection layers are not shown.
  • the manufacturing of the second conductor interconnection layer 232 and the interconnection with the second electrode 208 may be similar to the embodiment of FIG. 1 .
  • the difference between FIG. 2 A and FIG. 2 B is that in FIG.
  • the second electrode is positioned below the first and second nucleation layers 202 A and 202 B, and electrically contacts the first and second heterojunction through the first and second nucleation layers 202 A and 202 B, respectively.
  • the first and second nucleation layers 202 A and 202 B are doped to have improved conductivity.
  • the first and second nucleation layers 202 A and 202 B are doped immediately after the vertical sides of the substrate 201 are formed, and then the first and second channel layers 203 A and 203 B are formed.
  • the first and second nucleation layers 202 A and 202 B are doped after being inverted and exposed again.
  • the first and second nucleation layers 202 A and 202 B may be the same nucleation layer, and there is no insulating material between them.
  • the insulating material 212 between the entire substrate 201 and the first and second nucleation layers 202 A and 202 B and between them can be removed without affecting the structure above them.
  • the influence of the heterogeneous substrate, such as the silicon substrate, on the device performance can be completely avoided.
  • FIG. 3 is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure. In order to more clearly illustrate the structure of this embodiment, three dual channel HEMTs 300 A- 300 C are shown in FIG. 3 .
  • HEMT 300 A its structure is similar to that of HEMT 100 shown in FIG. 1 , including substrate 301 , first and second nucleation layers 302 A and 302 B, first and second channel layers 303 A and 303 B, and first and second barrier layers 304 A and 304 B; wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers 303 A and 303 B and the first and second barrier layers 304 A and 304 B, respectively.
  • portions of the substrate 301 horizontally extending above and below the first and second nucleation layers 302 A and 302 B include separation layers 311 A and 311 B, respectively, to separate the substrate 301 from other portions of the device.
  • the HEMT 300 further includes an insulating material 312 between the first and second barrier layers 304 A and 304 B and a shielding layer 313 above the separation layer 311 B. Parts similar to the structure of the embodiment shown in FIG. 1 have similar functions, and will not be described here. Unlike the embodiment of FIG. 1 , the first and second channel layers 303 A and 303 B are covered with a protective layer 314 to provide further protection.
  • the HEMT 300 further includes a first electrode 307 , a second electrode 308 and a third electrode 309 .
  • the first electrode 307 and the third electrode 309 are similar to the embodiment of FIG. 1 .
  • the second electrode 308 can be manufactured in different ways. For example, the semiconductor device shown in FIG. 2 may be inverted, and then a hole may be formed on the substrate 301 to expose the first and second heterojunctions after the inversion; next, the second electrode 308 may be formed on the first and second heterojunctions by depositing metal or the like. Filling the hole with an insulating material 315 after forming the second electrode; Then, through holes are formed in the insulating material 315 .
  • the substrate 301 only serves as a device support and is sufficiently separated from the active part of the semiconductor device, so that the influence on the device can be further reduced and the performance of the device can be greatly improved.
  • FIG. 4 is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure. In order to more clearly explain the structure of this embodiment, three dual channel HEMTs 400 A- 400 C are shown in FIG. 4 .
  • HEMT 400 A its structure is similar to that of HEMT 100 shown in FIG. 1 , including first and second nucleation layers 402 A and 402 B, first and second channel layers 403 A and 403 B, and first and second barrier layers 404 A and 404 B; wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers 403 A and 403 B and the first and second barrier layers 404 A and 404 B, respectively.
  • the spacer layers 411 A and 411 B extending horizontally are included above and below the first and second nucleation layers 402 A and 402 B.
  • the HEMT 400 further includes an insulating material 412 between the first and second barrier layers 404 A and 404 B and a shielding layer 414 above the separation layer 411 B.
  • the HEMT 400 further includes a first electrode 407 , a second electrode 408 and a third electrode 409 .
  • the first electrode 407 and the third electrode 409 are similar to the embodiment of FIG. 1 . Parts similar to the structure of the embodiment shown in FIG. 1 have similar functions, and will not be described here.
  • the first and second channel layers 403 A and 403 B are covered with a protective layer 414 to provide further protection.
  • the embodiment shown in FIG. 4 is different from the embodiment shown in FIGS. 1 - 3 in that the substrate is completely removed.
  • a manufacturing method of the embodiment of FIG. 4 will be described based on the embodiment shown in FIG. 2 .
  • the semiconductor device shown in FIG. 1 may be inverted, the substrate 401 may be thinned first, and then the entire semiconductor device may be placed in an etching liquid to completely remove the substrate 401 , and the first and second heterojunctions after the inversion may be exposed; next, the second electrode 408 may be formed on the first and second heterojunctions by depositing metal or the like, and then the second conductor interconnection layer 432 may be further formed to obtain the structure shown in FIG. 4 .
  • the hole between the respective HEMTs may be filled with an insulating material 415 .
  • This step may be performed before or after the second electrode 408 is formed.
  • FIG. 4 shows the spacer layer 411 A and the insulating material 415 filled after the removal of the parallel substrate, this schematic illustration cannot be used due to the thin thickness of the spacer layer 411 A represents the actual structure.
  • FIG. 4 shows a semiconductor device formed by removing a substrate from the structure of FIG. 2 .
  • the substrate, the nucleation layer and the insulating material between the nucleation layers may also be completely removed, and only the part above the substrate in the structure shown in FIG. 2 may be retained; and then the second electrode and the second conductor interconnection layer are formed.
  • a semiconductor device after substrate removal can also be obtained.
  • the present disclosure also includes a method for manufacturing a semiconductor device. Taking the manufacturing process of the dual channel HEMT shown in FIG. 4 as an example, the manufacturing method of the semiconductor device of the present disclosure will be described. Semiconductor devices of other structures can also be manufactured by similar methods.
  • FIG. 5 AA - FIG. 5 VB are flow charts of a manufacturing method of a high electron mobility transistor HEMT according to an embodiment of the present disclosure
  • FIG. 5 AA - FIG. 5 VA are top views of each step of a HEMT manufacturing method according to an embodiment of the present disclosure
  • FIG. 5 AB - FIG. 5 VB are cross-sectional views of each step of a HEMT manufacturing method according to an embodiment of the present disclosure.
  • a semiconductor device is fabricated on a silicon substrate.
  • other substrates such as intrinsic GaN, Al 2 O 3 (sapphire), SiC, etc. can also realize similar structures.
  • the preparation method 500 of HEMT includes: in step 5001 , as shown in FIGS. 5 AA and 5 AB , a Si substrate 501 is provided.
  • a plurality of first holes are formed on the substrate, as shown in FIGS. 5 BA and 5 BB .
  • the substrate 501 is etched by photolithography, and a plurality of rectangular first holes 521 are formed on the substrate 501 to expose the vertical interfaces 541 and 542 of the substrate 501 ; wherein, the substrate vertical interfaces 541 and 542 in the first hole 521 are (111) planes of the Si substrate.
  • the substrate vertical interfaces 541 and 542 in the first hole 521 are (111) planes of the Si substrate.
  • the number of the first holes provided on the same substrate depends on the specific requirements of integration and pressure resistance.
  • only three holes are taken as an example.
  • the method according to the present disclosure can pre configure the shape and size of the hole according to the actual needs. For example, when forming a semiconductor device with high withstand voltage, the hole depth is also deep.
  • a protective layer 531 is formed on the substrate and the first hole surface on the substrate, as shown in FIGS. 5 CA and 5 CB .
  • a SiN protective layer 531 is grown on the substrate 501 using a technique such as LPCVD to cover the surfaces of the substrate 501 and the plurality of holes 521 .
  • step 5004 the protective layer 531 horizontally extending on the bottom surface of the first hole and the upper surface of the substrate is removed, and the protective layer 531 on the sidewall of the first hole is retained, as shown in FIGS. 5 DA and 5 DB .
  • the Si substrate 501 on the bottom surface of the hole 521 is exposed by the etching technique having the vertical orientation, leaving only the protective layer 531 formed of SiN on the vertical interfaces 541 and 542 .
  • the protective layer 531 covers the substrate vertical interfaces 541 and 542 of the substrate hole 521 .
  • a first spacer layer is formed on the substrate and the first hole, as shown in FIGS. SEA and SEB.
  • the partition layer 511 is covered on the bottom surface of the first hole 521 .
  • SiO 2 may be formed using a deposition technique to form the first spacer layer 515 on the substrate 501 . Since the vertical interfaces 541 and 542 of the substrate 501 are covered with the protective layer 531 , the vertical interfaces 541 and 542 of the substrate 501 are substantially free of the growth separation layer 515 .
  • step 5006 the protective layer of the hole sidewall is removed, as shown in FIGS. 5 FA and 5 FB .
  • the spacer layer 511 over the substrate 501 covers a mask, and the protective layer 531 on the sidewall of the first hole 521 is partially etched by a selective etching technique.
  • etching may include removing a portion of the sidewall of the first hole 521 .
  • the vertical interfaces 541 and 542 of the substrate 501 are exposed.
  • a first nucleation layer and a second nucleation layer are formed at the vertical interface, as shown in FIGS. 5 GA and 5 GB .
  • the first and second nucleation layers 502 A and 502 B are grown on the exposed vertical surfaces 541 and 542 of the substrate 501 .
  • the nucleation layers 502 A and 502 B include AlN.
  • one or more buffer materials of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN may be further grown.
  • the nucleation layer may grow in the vertical direction (not shown) while growing horizontally. Through the control of process parameters, the growth of nucleation layer can be made as horizontal as possible. Moreover, although there is growth in the vertical direction, it does not affect the device structure.
  • a shielding layer is formed on the entire surface of the device, as shown in FIGS. 5 HA and 5 HB .
  • the SiO 2 shielding layer 512 is formed by a deposition process.
  • the shielding layer 512 fills the hole 521 and forms a SiO 2 shielding layer 512 of a certain height on the substrate. In some embodiments, if it is desired to form a semiconductor device with a large aspect ratio, the height of the shielding layer 512 will be correspondingly increased.
  • the shielding layer is patterned to form a plurality of second holes, as shown in FIGS. 5 IA and 5 IB .
  • the vertical second holes 523 and 524 are etched on the shield layer 512 by a vertical etching technique. Basically, the second holes 523 and 524 define the height of the second layer of the semiconductor device and limit the height of the nucleation layer to the first layer. At the bottom of the holes 523 and 524 , the upper surfaces and side surfaces of the nucleation layers 502 A and 502 B are exposed.
  • nucleation layers 502 A and 502 B are formed on the surface of the Si substrate (111), so the nucleation layers 502 A and 502 B have hexagonal symmetry.
  • Other structures formed in the holes 523 and 524 also have hexagonal symmetry after exposing the upper surfaces and side surfaces of the nucleation layers 502 A and 502 B.
  • the first and second channel layers are grown in the plurality of second holes, as shown in FIGS. 5 JA and 5 JB .
  • Channel layers 503 A and 503 B are formed on the nucleation layer 502 by epitaxial growth.
  • the horizontal growth is not easy to control, so it is difficult for the semiconductor structure to maintain completely vertical growth, and multiple growth planes may appear.
  • the structure of the invention can maintain the continuous growth of the same surface and improve the electrical characteristics of the device.
  • a third hole is formed between the first channel layer and the second channel layer, as shown in FIGS. 5 KA and 5 KB .
  • the shield layer 512 between the nucleation layers 503 A and 503 B is etched to form the third hole 525 . Since the third hole 525 is formed between the two second holes 523 and 524 , it can be considered that the third hole 545 and the second holes 523 and 524 together form a larger hole with the shielding layer as the sidewall.
  • a first barrier layer and a second barrier layer are formed on one side of the first channel layer and the second channel layer, respectively, as shown in FIGS. 5 LA and 5 LB .
  • Barrier layers 504 A and 504 B are formed by epitaxial growth in the third hole 525 .
  • a barrier layer may be grown to fill the third hole 525 , and then the barrier layers 504 A and 504 B may be formed by etching the barrier layers 504 A and 504 B.
  • the barrier layer may be the same height as the channel layer.
  • two barrier layers are epitaxially grown from the channel layers on both sides of the third hole 525 to reserve the space between the two barrier layers.
  • part of the barrier layer is also formed on the upper surface of the channel layer.
  • a second spacer layer is formed on the entire device, as shown in FIGS. 5 MA and 5 MB .
  • SiO 2 is deposited on the semiconductor device by a deposition process to fill the space between the barrier layers 504 A and 504 B and partially cover the channel layer and the barrier layer to form the second spacer layer 513 .
  • step 5014 the second spacer layer is patterned, and part of the second spacer layer between the first barrier layer 504 a and the second barrier layer 504 b is removed, as shown in FIGS. 5 NA and 5 NB .
  • a portion of the second partition layer 513 between the barrier layers 504 A and 504 B is partially removed by a vertical etching technique.
  • a third electrode is formed between the first barrier layer and the second barrier layer, as shown in FIGS. 5 OA and 5 OB .
  • the third electrode 509 is formed on the separation layer 513 remaining between the first and second barrier layers by an electrode deposition method.
  • the electrode 509 as a gate is arranged closer to the upper position, and the electrode 509 as a gate is as far away from the second electrode 508 (drain) as possible to improve the overall voltage resistance of the device.
  • a third spacer layer is formed on the third electrode, as shown in FIGS. 5 PA and 5 PB .
  • SiO 2 is deposited on the third electrode 509 by a deposition process to fill the space between the first barrier layer and the second barrier layer above the third electrode 509 to form the third partition layer 515 .
  • step 5017 the upper surfaces of the first and second heterojunctions are exposed, and a first electrode 507 is formed on the first and second heterojunctions, as shown in FIGS. 5 QA and 5 QB .
  • the upper surfaces of the first and second heterojunctions are exposed by removing the second partition layer above the first and second heterojunctions and the possible horizontally extending first and second barrier layers by patterning. In some embodiments, portions of the first and second channel layers and the first and second barrier layers may be further removed to ensure good electrical contact.
  • the first electrode 507 is formed by filling the electrode material. Although the first electrode 507 shown in the figure includes two parts respectively contacting the first heterojunction and the second heterojunction, these two parts are electrically connected to the same interconnection layer, and thus can be considered as the same electrode.
  • the subsequent steps include forming the first conductor interconnection layer and the third conductor interconnection layer and electrically connecting them to the first electrode and the third electrode, respectively. These steps are well known to those skilled in the art and will not be described here.
  • step 5018 the entire semiconductor device is turned over and the substrate 501 is removed, as shown in FIGS. 5 RA and 5 RB .
  • the substrate 501 faces upward.
  • the substrate 501 is first thinned, and then the entire substrate 501 is removed from the semiconductor device by wet etching.
  • step 5019 the first heterojunction and the second heterojunction are exposed, as shown in FIG. 5 SA and FIG. 5 SB .
  • the spacer layer above the first and second heterojunctions and part of the insulating material between them are removed to expose the first and second heterojunctions.
  • over etching may be appropriately performed to ensure good electrical contact.
  • the second electrode 508 is formed, as shown in FIG. 5 TA and FIG. 5 TB .
  • a metal electrode i.e., a second electrode 508
  • the second electrode 508 is in electrical contact with the vertical 2DEG in both the first heterojunction and the second heterojunction.
  • a passivation layer is formed, and then part of the passivation layer is etched to expose the second electrode 508 , as shown in FIGS. 5 UA and 5 UB .
  • a passivation layer is formed by depositing SiO 2 to fill the space between each HEMT.
  • SiO 2 is also partially deposited on the second electrode 508 .
  • SiO 2 on the second electrode 508 is removed by an etching technique to expose the second electrode.
  • a second conductor interconnection layer is formed, as shown in FIG. 5 VA and FIG. 5 VB .
  • a second conductor interconnection layer is formed by depositing metal to electrically connect the plurality of electrodes 508 .
  • the electrode of the second electrode 508 and the second conductor interconnection layer may be the same material.
  • the step of forming the second conductor interconnection layer is not necessary.
  • the second electrode 508 and the second conductor interconnection layer may be formed simultaneously.
  • the shapes of the first and second channel layers 503 A and 503 B and the first and second barrier layers 504 A and 504 B are defined by holes. As mentioned above, such a structure has many advantages.
  • the first and second channel layers 503 A and 503 B and the first and second barrier layers 504 A and 504 B may not be defined by holes, but the epitaxial growth of the first and second channel layers and the first and second barrier layers may be controlled by adjusting process parameters.
  • FIGS. 5 AA- 5 VB is only an exemplary method for manufacturing the semiconductor device according to the present disclosure. There are other manufacturing processes and methods in the art, which can also be applied to obtain the semiconductor device of the present disclosure. These methods are also within the scope of the present disclosure.
  • the height of the vertical channel semiconductor device formed on the substrate of the present disclosure is generally limited.
  • the height of the semiconductor device is small compared to the height of the substrate.
  • the height of the substrate is generally more than 500 microns, while the height of the semiconductor device is generally several to several tens of microns.
  • a problem caused by this is that the semiconductor device itself is thin, the mechanical strength is insufficient, the self-supporting force is weak, and it is easy to be damaged in the process of removing the substrate.
  • the prior art method is to fix the wafer including the substrate and the semiconductor device on a temporary substrate before removing the substrate. After removing the substrate and forming the second electrode and the second conductor interconnection layer, the temporary substrate is removed.
  • the mechanical strength of the semiconductor device can be improved by thickening the metal of the conductor interconnection layer, and the semiconductor device itself can have better self-supporting ability after completing the process.
  • the present disclosure provides a process that can achieve better support strength and complete the process without temporary substrate.
  • FIGS. 6 A- 6 G are flowcharts of a substrate removal method according to one embodiment of the present disclosure.
  • FIG. 6 A shows a state of the wafer before substrate removal.
  • the wafer includes a substrate 601 and a semiconductor device layer 602 above it.
  • the semiconductor device layer 602 includes the vertical channel semiconductor device of the present disclosure, including, but not limited to, one or more of Schottky diode, HEMTs and HHMTs.
  • a plurality of first conductor interconnection layers 603 e.g., source interconnection layers
  • a plurality of third conductor interconnection layers 604 are included over the semiconductor device layer 602 .
  • the substrate removal method of this embodiment includes the following steps: in step 610 , a plurality of metal pillars, such as copper pillars, are formed on the plurality of first electrode interconnection layers 603 and the plurality of third electrode interconnection layers 604 ; as shown in FIG. 6 B .
  • a plurality of metal pillars are formed on each electrode interconnection layer and electrically connected to each electrode interconnection layer.
  • the height of the metal column is high to provide sufficient supporting force in subsequent steps. In some embodiments, the height of the metal pillar is greater than 50 microns, 80 microns, or 100 microns.
  • the third electrode interconnection layer 604 does not appear on the semiconductor device. Therefore, the third electrode interconnection layer 604 is not necessary.
  • an insulating material is injected between the plurality of metal columns by an injection molding process, as shown in FIG. 6 C .
  • the insulating material includes two states of flow state and condensed state. During the injection molding process, the insulating material is in a flow state, and flows between the metal columns after injection. After a period of time, the insulating material turns into a solid state, which has good mechanical strength and can provide support in the subsequent substrate removal step.
  • the insulating material includes at least one or more organic materials, such as epoxy resin EP, polystyrene PS, ABS, polycarbonate PC, high density polyethylene HDPE, polypropylene PP, and polyvinyl chloride PVC.
  • injection molding process is a traditional process, easy to integrate with semiconductor process, and relatively low cost.
  • the insulating material is heated to become a flow state. However, the temperature of the insulating material does not cause damage to the semiconductor device.
  • the insulating material enters between the plurality of metal columns and is distributed around the plurality of metal columns. The insulating material becomes a solid state as the temperature decreases, which can not only protect the metal column, but also provide sufficient mechanical strength without using a temporary substrate.
  • phase change of insulating material caused by temperature change is only one way.
  • phase change of insulating materials including but not limited to: ultraviolet irradiation, laser curing, chemical reaction, etc.
  • these kinds of insulating materials can also be selected.
  • step 630 part of the insulating material is removed and a plurality of metal pillars are exposed, as shown in FIG. 6 D .
  • This step can also be completed in a later step. Exposing a plurality of metal pillars can prepare for subsequent electrical connection. Similarly, for the metal column and insulating material formed on the other side, a similar method can be adopted to remove part of the insulating material and expose the metal column to ensure electrical connection.
  • step 640 the silicon substrate is removed, as shown in FIG. 6 E .
  • the wafer still has a good mechanical strength due to the support of a plurality of metal columns and solid insulating materials.
  • the substrate is not easily damaged in the process of removing the substrate.
  • the entire wafer is turned over and supported in a support device; then the substrate is thinned first, and then the whole substrate is removed by wet etching. In the process of substrate removal, since the insulating material provides sufficient mechanical strength, the entire wafer is supported in the support device without causing damage.
  • a second electrode and a second electrode interconnection layer are formed, as shown in FIG. 6 F .
  • the formation of the second electrode and the formation of the second electrode interconnection layer can be completed in the same step; or may be completed in different steps.
  • the second electrode may be formed at an appropriate position of the exposed half electrode device layer 602 , thereby forming the second electrode interconnection layer 632 electrically connected to the second electrode.
  • other steps may be included between forming the second electrode and forming the second electrode interconnection layer. These steps include, but are not limited to, depositing an insulating material such as SiO 2 to form a passivation layer.
  • the wafer can be cut after step 650 .
  • the semiconductor device layer is cut, one or more semiconductor devices are separated.
  • a packaging step may also be included to obtain a semiconductor device capable of practical application.
  • a plurality of metal pillars such as copper pillars, are formed on the second electrode interconnection layer; then, an injection molding process is used to inject insulating materials between the metal columns, as shown in FIG. 6 G
  • a plurality of metal pillars may also be formed on one side of the second electrode and an insulating material may be injected to further improve the physical strength of the half electrode device.
  • the insulating material also encloses the entire semiconductor device layer.
  • subsequent packaging steps can be saved.
  • the wafer can be cut after step 660 .
  • one or more semiconductor devices after dicing may also be packaged again, so as to obtain a semiconductor device that can be applied in practice.

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169012A1 (en) * 2007-10-04 2011-07-14 Hersee Stephen D NANOWIRE AND LARGER GaN BASED HEMTS
US20140084299A1 (en) * 2012-09-21 2014-03-27 Robert Bosch Gmbh Vertical microelectronic component and corresponding production method
US20140103357A1 (en) * 2012-10-17 2014-04-17 Imec Schottky diode structure and method of fabrication
US20150325689A1 (en) * 2012-06-25 2015-11-12 Seoul Semiconductor Co., Ltd. Iii-v transistor and method for manufacturing same
US20190334024A1 (en) * 2016-02-24 2019-10-31 Quanzhong Jiang Layered vertical field effect transistor and methods of fabrication
US20200058782A1 (en) * 2016-12-30 2020-02-20 Intel Corporation Stacked group iii-nitride transistors for an rf switch and methods of fabrication
US20210028303A1 (en) * 2018-03-29 2021-01-28 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for fabricating the same
US20210091219A1 (en) * 2019-09-25 2021-03-25 Stmicroelectronics S.R.L. High electron mobility transistor (hemt) devices and methods

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563186A (ja) * 1991-09-02 1993-03-12 Fuji Electric Co Ltd Ｍｏｓ駆動型サイリスタ
US7247517B2 (en) * 2003-09-30 2007-07-24 Intel Corporation Method and apparatus for a dual substrate package
US7098093B2 (en) * 2004-09-13 2006-08-29 Northrop Grumman Corporation HEMT device and method of making
US7863189B2 (en) * 2007-01-05 2011-01-04 International Business Machines Corporation Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
TW200937574A (en) * 2007-09-28 2009-09-01 Toshiba Kk Semiconductor device and method for manufacturing same
JP2011210751A (ja) * 2010-03-26 2011-10-20 Nec Corp Ｉｉｉ族窒化物半導体素子、ｉｉｉ族窒化物半導体素子の製造方法、および電子装置
US8772144B2 (en) * 2011-11-11 2014-07-08 Alpha And Omega Semiconductor Incorporated Vertical gallium nitride Schottky diode
KR101920715B1 (ko) 2012-03-06 2018-11-21 삼성전자주식회사 고 전자 이동도 트랜지스터 및 그 제조방법
US9276097B2 (en) * 2012-03-30 2016-03-01 Infineon Technologies Austria Ag Gate overvoltage protection for compound semiconductor transistors
CN103730490A (zh) * 2012-10-16 2014-04-16 浙江大学苏州工业技术研究院 一种具有垂直导电沟道的半导体装置及其制备方法
CN104037212B (zh) * 2013-03-05 2019-03-22 首尔半导体株式会社 氮化物半导体元件及其制造方法
US9087828B2 (en) * 2013-03-12 2015-07-21 Alpha & Omega Semiconductor Incorporated Semiconductor device with thick bottom metal and preparation method thereof
US9269789B2 (en) * 2013-03-15 2016-02-23 Semiconductor Components Industries, Llc Method of forming a high electron mobility semiconductor device and structure therefor
US9425301B2 (en) * 2014-04-30 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall passivation for HEMT devices
JP6287629B2 (ja) * 2014-06-26 2018-03-07 日亜化学工業株式会社 ヘテロ接合電界効果トランジスタ
JP2016063167A (ja) * 2014-09-19 2016-04-25 株式会社東芝 半導体装置
US9601610B1 (en) 2015-06-18 2017-03-21 Hrl Laboratories, Llc Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas
US11018253B2 (en) * 2016-01-07 2021-05-25 Lawrence Livermore National Security, Llc Three dimensional vertically structured electronic devices
KR102467034B1 (ko) * 2016-05-17 2022-11-14 삼성전자주식회사 반도체 패키지
CN106098664A (zh) * 2016-06-12 2016-11-09 华天科技（昆山）电子有限公司 一种埋入式半导体芯片扇出型封装结构及其制作方法
CN106549038B (zh) * 2016-12-09 2019-08-02 宁波海特创电控有限公司 一种垂直结构的氮化镓异质结hemt
CN106601808B (zh) * 2016-12-19 2019-09-06 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法
DE102017102035A1 (de) * 2017-02-02 2018-08-02 Infineon Technologies Ag Halbleitervorrichtung, Verfahren zum Fertigen einer Halbleitervorrichtung und Verfahren zum Verstärken eines Die in einer Halbleitervorrichtung
IT201700064147A1 (it) * 2017-06-09 2018-12-09 St Microelectronics Srl Transistore hemt normalmente spento con generazione selettiva del canale 2deg e relativo metodo di fabbricazione
US11121258B2 (en) 2018-08-27 2021-09-14 Micron Technology, Inc. Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods
CN109300976B (zh) * 2018-09-29 2021-11-23 广东省半导体产业技术研究院 半导体器件及其制作方法
KR102541564B1 (ko) * 2018-10-04 2023-06-08 삼성전자주식회사 반도체 패키지
US20200312734A1 (en) * 2019-03-25 2020-10-01 Powertech Technology Inc. Semiconductor package with an internal heat sink and method for manufacturing the same
CN117317001A (zh) 2019-04-12 2023-12-29 广东致能科技有限公司 一种半导体器件及其制造方法
CN111816701B (zh) 2019-04-12 2024-12-27 广东致能科技有限公司 一种半导体器件及其制造方法
CN110400776A (zh) 2019-07-02 2019-11-01 珠海格力电器股份有限公司 一种功率芯片及其制备方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169012A1 (en) * 2007-10-04 2011-07-14 Hersee Stephen D NANOWIRE AND LARGER GaN BASED HEMTS
US20150325689A1 (en) * 2012-06-25 2015-11-12 Seoul Semiconductor Co., Ltd. Iii-v transistor and method for manufacturing same
US20140084299A1 (en) * 2012-09-21 2014-03-27 Robert Bosch Gmbh Vertical microelectronic component and corresponding production method
US20140103357A1 (en) * 2012-10-17 2014-04-17 Imec Schottky diode structure and method of fabrication
US20190334024A1 (en) * 2016-02-24 2019-10-31 Quanzhong Jiang Layered vertical field effect transistor and methods of fabrication
US20200058782A1 (en) * 2016-12-30 2020-02-20 Intel Corporation Stacked group iii-nitride transistors for an rf switch and methods of fabrication
US20210028303A1 (en) * 2018-03-29 2021-01-28 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and method for fabricating the same
US20210091219A1 (en) * 2019-09-25 2021-03-25 Stmicroelectronics S.R.L. High electron mobility transistor (hemt) devices and methods

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