TWI885679B - High voltage device - Google Patents

Abstract

A high voltage device includes: a high voltage junction termination (HVJT) element, and a transistor extended along a ring shape of the high voltage junction termination element. The transistor has one or more first U-shape segments from top view. Each first U-shape segment includes: a first linear portion, a second linear portion disposed corresponding to the first linear portion, and a first arc portion connecting the first linear portion and the second linear portion.

Description

High voltage device

The present invention relates to high voltage devices, and in particular to optimizing the routing design of transistors.

In most switching applications, switching efficiency depends on switching loss and switching speed. One way to supply power to a high-voltage circuit of a gate driver is to use a bootstrap circuit, which has the advantages of simplicity and low cost. The bootstrap circuit includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR), which can provide the voltage level of the high-voltage circuit.

Although existing high voltage devices have generally met their original purpose, they are not satisfactory in all aspects. For example, the forward current needs to be further improved. Therefore, there are still some problems to be overcome regarding high voltage devices and manufacturing technology.

A high voltage device includes: a high voltage junction boundary element, and a transistor extending in a ring shape along the high voltage junction boundary element. From a top view, the transistor has one or more first U-shaped segments. Each first U-shaped segment includes: a first linear portion, a second linear portion corresponding to the first linear portion, and a first arc portion connecting the first linear portion and the second linear portion.

10: High voltage device

20: High voltage device

30: High voltage device

40: High voltage device

50: Forward current-size curve

100: High voltage junction boundary element

100A: High voltage area

100B: Low pressure area

200: Isolation diode

300: Transistor

300A: Recessed corner

300B: convex corner

300U: U-shaped segment

300U’: U-shaped segment

300U-1: Linear part

300U-2: Linear part

300U-3: Arc section

320: Source area

340: Drain area

360: Gate structure

400:Level shifter

The following will be described in detail with the accompanying drawings to illustrate various aspects of the embodiments of the present invention. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale. In fact, the sizes of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

Figure 1 is a top view of a high-voltage device based on a comparison example.

Figures 2 and 3 are top views of the high-voltage device according to some embodiments of the present invention.

Figures 4 and 5 are top views of high-pressure devices with various designs according to other embodiments of the present invention.

Figure 6 is a forward current-size curve of a high voltage device according to some embodiments of the present invention.

The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are directly in contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the present invention may repeat component symbols and/or letters in various examples. Such repetition is for the purpose of simplification and clarity, and does not itself dominate the relationship between the various embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to bonding and connection, such as "connection", "interconnection", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures.

Furthermore, spatially relative terms such as "below", "below", "below", "above", "above", and similar terms may be used herein to describe the relationship between an element or component and other elements or components as shown in the figures. These spatial terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the figures. When the device is rotated to other orientations (rotated 90° or other orientations), the spatially relative descriptions used herein may also be interpreted based on the rotated orientation.

The terms "about", "approximately" and "generally" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The numerical values given here are approximate values, that is, in the absence of specific description of "about", "approximately" and "generally", the given numerical values may still imply the meaning of "about", "approximately" and "generally".

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Additional components may be added to the high voltage device structure. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those with ordinary knowledge in the technical field to which the present invention belongs. It is understood that these terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

In order to improve the switching efficiency, a bootstrap circuit can be incorporated into the high voltage device, which includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR). The key parameters of the bootstrap diode in the bootstrap circuit are reverse recovery time, forward conduction voltage drop, and reverse blocking voltage. In traditional designs, the bootstrap diode is generally configured separately. The separately configured bootstrap diode is placed outside the high voltage device and is individually connected to the high voltage (high side) area and the low voltage (low side) area of the high voltage device. In order to meet the cut-off withstand voltage requirement, the self-lifting diode must be achieved by relaxing the design rules, which results in a larger component size. Since the separated self-lifting diode is not integrated into the high-voltage device, it may occupy too much space and increase the cost of the additional bill of materials (BOM). Therefore, the above problem can be solved by using an embedded self-lifting diode integrated into the high-voltage device. However, compared to the self-lifting diode in a separate configuration, the self-lifting diode in a buried configuration may generate a forward leakage current from the anode end to the substrate (vertical bipolar junction) during operation, while the cathode end has no bipolar junction and no significant reverse leakage current. Therefore, an isolation component (such as a buried layer) can be further added to the self-lifting diode in a buried configuration to reduce the generation of forward leakage current.

When a high voltage device integrates a self-lifting diode and a high voltage junction termination (HVJT) element in a buried configuration, the transistor in the self-lifting diode can utilize the annular contour of the high voltage junction termination element and extend along the annular shape to save excess space. It should be understood that when the extended size of the transistor (such as the trace width) is larger, the forward current of the transistor can also be increased to drive the self-lifting diode. In order to cope with the extended size of the transistor, the annular shape of the high voltage junction termination element must also occupy a larger chip area. However, generally speaking, the components required for the high voltage region do not occupy too much space, so that a high proportion of the space in the oversized ring will not be used, resulting in a waste of chip area. The inventors found that the high voltage junction boundary element and the corresponding transistor profile can be designed to have a U-shaped segment (such as a hairpin bend shape) to save space in the high voltage region while maintaining the required extension size of the transistor.

FIG. 1 is a top view of a high voltage device 10 according to a comparative example. In some embodiments, the high voltage device may generally include any number of active components and passive components. The active component includes a metal-oxide semiconductor (MOS) transistor, a complementary metal-oxide semiconductor (CMOS) transistor, a laterally diffused metal-oxide semiconductor (LDMOS) transistor, a bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistor, a bipolar junction transistor (BJT), a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAA FET), other similar devices, or a combination thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures.

1, the high voltage device 10 may include a high voltage junction boundary element 100, an isolation diode 200, a transistor 300, and a plurality of level shifters 400. In some embodiments, the high voltage junction boundary element 100 may be designed to be ring-shaped. A high voltage region 100A may be defined within the ring of the high voltage junction boundary element 100, and a low voltage region 100B may be defined outside the ring of the high voltage junction boundary element 100. Furthermore, the isolation diode 200 and the transistor 300 may constitute a self-lifting diode in an embedded configuration. The transistor 300 and the multiple level shifters 400 can be integrated into the ring of the high voltage junction boundary element 100, thereby effectively saving the overall area of the high voltage device 10. In addition, the integrated configuration makes the high voltage junction boundary element 100, the isolation diode 200, the transistor 300, and the multiple level shifters 400 electrically coupled to each other, thereby omitting wire bonding and opening formation, resulting in improved reliability.

Continuing to refer to FIG. 1, although the high voltage junction boundary element 100 is shown as a rectangular ring, the embodiments of the present invention are not limited thereto. For example, the high voltage junction boundary element 100 may be a circular ring, an elliptical ring, a square ring, a triangular ring, or any suitable closed geometric ring. The ring-shaped configuration makes the integration of the high voltage junction boundary element 100 with the isolation diode 200, the transistor 300, and the plurality of level shifters 400 more efficient without occupying additional chip area. The high voltage junction boundary element 100 physically and electrically separates the high voltage region 100A and the low voltage region 100B. The high voltage region 100A can accommodate components operating at a high voltage level, while the low voltage region 100B can accommodate components operating at a low voltage level. Generally speaking, "high voltage" refers to a voltage above 300V, such as between 300V and 1200V, between 300V and 750V, or between 750V and 1200V. "Low voltage" refers to a voltage below 20V, such as between 1V and 20V, between 1V and 10V, or between 10V and 20V. In a specific embodiment of the present invention, the high voltage region 100A and the low voltage region 100B operate at voltages of 600V and 15V, respectively.

Referring to FIG. 1 , an isolation diode 200 may be disposed in the low voltage region 100B. In some embodiments, the isolation diode 200 may be electrically connected to the transistor 300. As previously mentioned, in order to avoid forward leakage current generated from the anode terminal to the substrate (vertical bipolar junction), a buried layer, for example, may be added to suppress the leakage current of the substrate to less than 1%. As a result, the device structure in which the isolation diode 200 and the transistor 300 are coupled can withstand a reverse blocking voltage of 650V and a forward current of 17mA. In addition, the recovery time required for the isolation diode 200 to switch from the on state to the off state may be between 10nsec and 50nsec.

1, the transistor 300 may extend along the ring of the high voltage junction boundary element 100. It should be understood that both the transistor 300 and the plurality of level shifters 400 are integrated with the ring of the high voltage junction boundary element 100. Thus, the plurality of level shifters 400 occupy a portion of the ring of the high voltage junction boundary element 100, while the transistor 300 traverses the remaining portion of the ring of the high voltage junction boundary element 100. The transistor 300 may be designed in a depletion mode (normally open and conducting at a gate voltage of 0V), or may be designed in an enhancement mode (normally off at a gate voltage of 0V). In a specific embodiment of the present invention, transistor 300 may be a lateral diffused metal oxide semiconductor transistor. For example, when the gate voltage is 20V, transistor 300 is in a forward mode, so that current can flow. In contrast, when the gate voltage is 0V, transistor 300 is in a reverse mode, so that current does not flow. It should be understood that when a lateral diffused metal oxide semiconductor transistor is used, the forward current of the self-lifting diode will be limited by the internal resistance of the lateral diffused metal oxide semiconductor transistor.

In some embodiments, the transistor 300 may include a source region 320, a drain region 340, and a gate structure 360. The source region 320 may be disposed near the low voltage region 100B, the drain region 340 may be disposed near the high voltage region 100A, and the gate structure 360 may be disposed between the source region 320 and the drain region 340. In addition, the isolation diode 200 may be located between the source region 320 of the transistor 300 and the main region (not shown) of the substrate ground terminal. During operation of transistor 300, current can flow from isolation diode 200 through source region 320 and the region below gate structure 360 to drain region 340, and its flow rate can be controlled by gate structure 360. Without integration with high voltage junction boundary element 100, transistor 300 can have a circular design, such as a central circle with drain region 340, and a ring of gate structure 360 surrounding drain region 340 in sequence, a ring of source region 320, and a ring of main region (if any). Such a design can avoid sharp edge effects, which can cause device failure. In addition, the circular design can also make the electric field distribution more uniform.

1 , a plurality of level shifters 400 may be integrated into the ring of the high voltage junction boundary element 100. From another perspective, the plurality of level shifters 400 may be located on the ring of the high voltage junction boundary element 100. As previously mentioned, the plurality of level shifters 400 occupy a portion of the ring of the high voltage junction boundary element 100, and the transistor 300 traverses the remaining portion of the ring of the high voltage junction boundary element 100. It is noteworthy that the plurality of level shifters 400 are separated from each other, and the plurality of level shifters 400 are separated from the transistor 300. Although FIG. 1 shows two level shifters 400, embodiments of the present invention are not limited thereto. For example, any number of level shifters 400 may be configured, depending on the application and design requirements. According to some embodiments of the present invention, the level shifter 400 may convert a signal between the high voltage region 100A and the low voltage region 100B. For example, the level shifter 400 may receive a signal from a control logic (not shown) to perform voltage switching from the high voltage region 100A to the low voltage region 100B, or from the low voltage region 100B to the high voltage region 100A.

According to some embodiments of the present invention, the transistor 300 and the level shifter 400 may have the same conductivity type, for example, both may be N-type. According to alternative embodiments of the present invention, the transistor 300 and the level shifter 400 may have another conductivity type, for example, both may be P-type. In some embodiments, the P-type and the N-type may be doped with appropriate dopants (or impurities) respectively. The P-type doping may include boron (B), indium (In), aluminum (Al), or gallium (Ga), and the N-type doping may include phosphorus (P) or arsenic (As).

In a conventional manufacturing process, the extended dimension (e.g., trace width) of the transistor 300 (including the source region 320, the drain region 340, and the gate structure 360) can be increased to increase the forward current of the transistor 300 and better avoid leakage current. The trace width required for the transistor 300 can be determined based on the performance requirements of the high voltage device 10. When determining the trace width of the transistor 300, the ring shape of the high voltage junction boundary element 100 also needs to be adjusted conformably to accommodate the transistor 300. More precisely, the extended dimension (e.g., trace width) of the high voltage junction boundary element 100 can be the sum of the trace width of the transistor 300 and the dimensions of multiple level shifters 400, as shown in FIG. 1. The ring shape of the high voltage junction boundary element 100 may occupy a relatively large chip area, while the components of the high voltage region 100A may occupy a relatively small chip area (such as the local space near the multiple level shifters 400). As a result, a large proportion of the space within the ring shape of the high voltage junction boundary element 100 will not be used, resulting in a waste of chip area.

For simplicity, only major components of the high voltage device 10 are shown, such as the high voltage junction boundary element 100, the isolation diode 200, the transistor 300 (including the source region 320, the drain region 340, and the gate structure 360), and a plurality of level shifters 400. For example, the structure of the high voltage device 10 may further include a substrate, a buried layer, an epitaxial layer, and an interlayer dielectric (ILD) layer. The substrate, the epitaxial layer, and the interlayer dielectric layer may cross the entire circuit surface area, and the buried layer may be disposed in one or more of the major components. In other words, each of the high voltage junction boundary element 100, the isolation diode 200, the transistor 300, and the level shifter 400 may include a substrate, an epitaxial layer, and an interlayer dielectric layer (and/or a buried layer).

In some embodiments, the substrate may be, for example, a wafer or a crystal grain, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AAsP) alloy, or a plurality of other semiconductors. arsenide, AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and/or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

In other embodiments, the substrate may also be a semiconductor on insulator (SOI) substrate. The SOI substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. For example, the substrate may be a P-type, and its doping concentration may be between 1×10 ¹⁴ cm ^-3 and 3×10 ¹⁴ cm ^-3 .

In other embodiments, the substrate may include an isolation structure (not shown) to define the active region and electrically isolate the active region components within or on the substrate, but the embodiments of the present invention are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate, selectively etching the insulating layer and the substrate to form a trench extending from the top surface of the substrate to a position within the substrate, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a nitrogen-rich liner (e.g., silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (e.g., silicon dioxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Thereafter, an annealing process is performed on the insulating material in the trench, and a planarization process (e.g., chemical mechanical polishing (CMP)) is performed on the substrate to remove excess insulating material so that the insulating material in the trench is flush with the top surface of the substrate.

In some embodiments, an epitaxial layer is formed on a substrate. For example, the epitaxial layer may be N-type, and its doping concentration may be between 1.13×10 ¹⁵ cm ^-3 and 2.30×10 ¹⁵ cm ^-3 . In other words, the substrate and the epitaxial layer may have different conductivity types, and the doping concentration of the substrate is less than the doping concentration of the epitaxial layer. The material of the epitaxial layer may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer may be between 3μm and 7μm. The epitaxial layer may be formed by an epitaxial process, and the epitaxial process may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

In some embodiments, a buried layer may be disposed in the substrate. The buried layer may directly contact the epitaxial layer. According to some embodiments of the present invention, the buried layer helps to reduce leakage current from the upper surface of the epitaxial layer to the substrate, increase the channel space to withstand higher currents, and form a substrate for the high voltage region 100A. For example, the buried layer may be N-type, and its doping concentration may be between 6.4×10 ¹⁶ cm ^-3 and 9.6×10 ¹⁶ cm ^-3 . The vertical dimension of the buried layer may be between 1 μm and 2 μm. The method for forming the buried layer may include, before forming the epitaxial layer, ion implanting N-type dopants (e.g., phosphorus or arsenic) in the substrate, performing a heat treatment to drive the implanted ions into the substrate, and then forming the epitaxial layer on the substrate. In some embodiments, since the epitaxial layer is formed under high temperature conditions, the implanted ions diffuse into the epitaxial layer. The buried layer is located near the interface between the substrate and the epitaxial layer, and has a portion in the substrate and another portion in the epitaxial layer. In other words, the buried layer may extend upward from the interface between the substrate and the epitaxial layer.

In some embodiments, high-voltage well regions, deep well regions, well regions, and doped regions of various conductivity types (e.g., P-type or N-type) may be formed in the epitaxial layer. The high-voltage well regions, deep well regions, well regions, and doped regions may be formed by, for example, ion implantation and/or diffusion processes. In alternative embodiments, instead of using ion implantation and/or diffusion processes, the high-voltage well regions, deep well regions, well regions, and doped regions may be doped in situ during the growth of the epitaxial layer. In other embodiments, in situ and implantation doping may be used together.

As shown in FIG. 1 , a source region 320 and a drain region 340 may be disposed in the epitaxial layer (not shown). The source region 320 and the drain region 340 may extend vertically from the upper surface of the epitaxial layer into the epitaxial layer. According to some embodiments of the present invention, the source region 320 and the drain region 340 may serve as a source terminal and a drain terminal of the transistor 300, respectively. The source region 320 and the drain region 340 may be N-type, and their doping concentration may be between 4.0×10 ²⁰ cm ^-3 and 6.0×10 ²⁰ cm ^-3 . Since the source region 320 and the drain region 340 are N-type, the transistor 300 may be N-type. The thickness of the source region 320 and the drain region 340 may be between 0.09 μm and 0.11 μm. The formation method of the source region 320 and the drain region 340 may be similar to the formation method of the high-pressure well region, deep well region, well region, and doped region, and the details thereof will not be repeated here.

As shown in FIG. 1 , a gate structure 360 may be disposed on the epitaxial layer. As previously mentioned, the gate structure 360 may be located between the source region 320 and the drain region 340 in the horizontal direction. According to some embodiments of the present invention, the gate structure 360 may serve as a gate terminal of the transistor 300 and may modulate the electric field of the channel region below. It should be understood that in high voltage operation, the drain region 340 may gather an excessively high electric field. In order to adjust the distribution of the electric field, the gate structure 360 is not disposed at the center point between the source region 320 and the drain region 340 in the horizontal direction. The gate structure 360 may be closer to the source region 320 and farther from the drain region 340. The thickness of the gate structure 360 may be between 3.5 μm and 4.0 μm.

The material of the gate structure 360 may include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicide (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbide (such as tantalum carbide (TaC), tantalum carbonitride (tantalum carbonitride, TaCN, or other similar materials), metal oxides, and metals. The metal may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, combinations thereof, or multiple layers thereof. The gate structure 360 may be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other suitable processes, or a combination thereof.

In some embodiments, an interlayer dielectric layer may be formed on the epitaxial layer. The interlayer dielectric layer may cover the epitaxial layer and the gate structure 360. In addition to providing mechanical protection and insulation to the components below, the interlayer dielectric layer may also isolate different levels of conductive materials. The material of the interlayer dielectric layer may include silicon oxide (SiO), silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO _x N _y C _1-xy , where x and y are in the range of 0 to 1), tetraethoxysilane (tetra ethyl ortho silicate, TEOS), undoped silica glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass, BSG), or other similar materials), low-k dielectric materials, or other suitable dielectric materials.

The thickness of the interlayer dielectric layer may be between 1000 μm and 1200 μm. The interlayer dielectric layer may be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Next, the interlayer dielectric layer may be subjected to a planarization process (such as chemical mechanical polishing) so that the interlayer dielectric layer has a flat top surface.

Figures 2 and 3 are top views of a high voltage device 20 according to some embodiments of the present invention. Compared to the high voltage device 10 of Figure 1, the transistor 300 of the high voltage device 20 of Figure 2 includes one or more U-shaped segments 300U. Figure 3 shows one arrangement of the high voltage device 20. For simplicity, the features of the high voltage junction boundary element 100, the isolation diode 200, the transistor 300 (including the source region 320, the drain region 340, and the gate structure 360), and the multiple level shifters 400 are similar to those shown in Figure 1, and the details will not be repeated here.

Referring to FIG. 2 , each U-shaped segment 300U may include a linear portion 300U-1, a linear portion 300U-2, and an arcuate portion 300U-3. In some embodiments, the arcuate portion 300U-3 is close to the low-pressure area 100B. It is worth noting that the ring shape of the high-pressure contact boundary element 100 conformsly extends along the contour of one or more U-shaped segments 300U. The linear portion 300U-1 and the linear portion 300U-2 of each U-shaped segment 300U may be arranged correspondingly, and the arcuate portion 300U-3 may connect the linear portion 300U-1 and the linear portion 300U-2. For example, the arcuate portion 300U-3 may extend from the end point of the linear portion 300U-1 to the end point of the linear portion 300U-2, thereby forming a U-shaped contour. The U-shaped segment 300U is characterized by having a slender outline, thereby saving the space occupied by the entire ring. The transistor 300 (including the source region 320, the drain region 340, and the gate structure 360) can extend along the linear portion 300U-1 toward the arc portion 300U-3, pass through the arc portion 300U-3, and then extend away from the arc portion 300U-3 along the linear portion 300U-2, thus completing a loop of the U-shaped segment 300U. It is worth noting that when each U-shaped segment 300U has a certain length as a whole, it can contribute to the extension size of the transistor 300 (such as the trace width) reaching at least twice the length.

It should be understood that, since one or more U-shaped segments 300U contribute a considerable extension dimension (e.g., trace width) to the transistor 300, the size of the rectangular portion of the original ring can be compressed, thereby saving the space occupied by the entire ring. Each U-shaped segment 300U can extend outward from the opposite side of the rectangular portion relative to the multiple level shifters 400. For example, the multiple level shifters 400 are located on the upper side of the rectangular portion, and one or more U-shaped segments 300U can extend downward from the lower side of the rectangular portion. Although FIG. 2 shows three U-shaped segments 300U (located at the left end, the middle point, and the right end of the lower side of the rectangular portion, respectively), the embodiment of the present invention is not limited thereto. For example, any number of U-shaped segments 300U may be configured, depending on the application and design requirements. The space between the linear portion 300U-1 and the linear portion 300U-2 is very limited, thereby further limiting the space occupied by the overall ring. According to a specific embodiment of the present invention, the linear portion 300U-1 may be directly adjacent to the linear portion 300U-2, so that there is no space between the linear portion 300U-1 and the linear portion 300U-2 (making the U-shaped segment 300U present a hairpin-like shape). When the linear portion 300U-1 is directly adjacent to the linear portion 300U-2, the drain region 340 of the linear portion 300U-1 and the drain region 340 of the linear portion 300U-2 face each other and merge into a single component. In other words, the linear portion 300U-1 and the linear portion 300U-2 can share a single drain region 340.

Continuing with reference to FIG. 2, the transistor 300 may extend to have a concave corner 300A and a convex corner 300B as viewed from the high voltage region 100A. Specifically, the concave corner 300A of the transistor 300 is recessed outwardly away from the center of the high voltage region 100A, while the convex corner 300B of the transistor 300 is convex inwardly toward the center of the high voltage region 100A. It should be understood that when the transistor 300 extends along a rectangular ring, the transistor 300 has only a concave corner. However, when the ring includes a U-shaped segment 300U, the connection between the U-shaped segment 300U and the other segments of the ring has a convex corner 300B. Therefore, the concave corner 300A is away from the U-shaped segment 300U, while the convex corner 300B is close to the U-shaped segment 300U. According to some embodiments of the present invention, the number and curvature of the concave corners 300A and the convex corners 300B can be designed to adjust the electric field distribution, thereby improving the breakdown voltage.

Referring to FIG. 3 , two structures of the high voltage device 20 are shown arranged together. Although the ring of the transistor 300 is included in the U-shaped segment 300U to save the area of the entire ring on the chip, the space between adjacent U-shaped segments 300U is relatively small and difficult to be effectively used, thus still resulting in a waste of chip area. According to some embodiments of the present invention, the U-shaped segments 300U of the two structures can face each other so that the U-shaped segment 300U of one structure can extend into the space between the U-shaped segments 300U of the other structure. In other words, the U-shaped segment 300U of one structure is arranged crosswise with the U-shaped segment 300U of the other structure, thereby achieving a more effective use of the chip area.

FIGS. 4 and 5 are top views of high voltage devices 30 and 40 with various designs according to other embodiments of the present invention. Compared to the high voltage device 20 of FIG. 2, the transistor 300 of the high voltage devices 30 and 40 may include a plurality of U-shaped segments 300U arranged in a continuous manner. For simplicity, the features of the high voltage junction boundary element 100, the isolation diode 200, the transistor 300 (including the source region 320, the drain region 340, and the gate structure 360), and the plurality of level shifters 400 are similar to those shown in FIG. 2, and the details thereof will not be repeated here.

Referring to FIG. 4 , a high voltage device 30 is illustrated. A plurality of U-shaped segments 300U of the high voltage device 30 may be arranged continuously along the rectangular portion of the ring relative to the opposite sides where the plurality of level shifters 400 are located. The plurality of U-shaped segments 300U arranged continuously may present a shape similar to a winding snake. According to some embodiments of the present invention, the continuous arrangement of the plurality of U-shaped segments 300U may further increase the extension size (e.g., trace width) of the transistor 300 while saving the area of the entire ring on the chip. As previously mentioned, each U-shaped segment 300U may include a linear portion 300U-1, a linear portion 300U-2, and an arcuate portion 300U-3 (not labeled for simplicity). Due to the continuous arrangement, the linear portion 300U-1 of each U-shaped segment 300U can be directly adjacent to the linear portion 300U-2 of the left U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U can be directly adjacent to the linear portion 300U-1 of the right U-shaped segment 300U. In order to make the extension of the transistor 300 uninterrupted, the linear portion 300U-1 of each U-shaped segment 300U needs to be adjacent to the linear portion 300U-2 of the left U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U needs to be adjacent to the linear portion 300U-1 of the right U-shaped segment 300U.

Continuing with reference to FIG. 4 , when adjacent U-shaped segments 300U are connected, multiple U-shaped segments 300U’ in a flip-chip arrangement may be indirectly formed. In some embodiments, each U-shaped segment 300U’ may include two linear portions and an arc portion connecting the two linear portions. For example, when the linear portion 300U-2 of the left U-shaped segment 300U is connected to the linear portion 300U-1 of the right U-shaped segment 300U, the linear portion 300U-2 of the left U-shaped segment 300U and the linear portion 300U-1 of the right U-shaped segment 300U may be respectively regarded as two linear portions of the U-shaped segment 300U’, and the two linear portions of the U-shaped segment 300U’ are connected through the arc portion of the U-shaped segment 300U’. In some embodiments, the arc portion of the U-shaped segment 300U' is close to the high voltage region 100A. When the two linear portions of the U-shaped segment 300U' are directly adjacent, the two source regions 320 of the two linear portions of the U-shaped segment 300U' face each other and merge into a single component. In other words, the two linear portions of the U-shaped segment 300U' can share a single source region 320. Since the multiple U-shaped segments 300U are arranged continuously, the multiple U-shaped segments 300U' are also arranged continuously. The arc portion of each U-shaped segment 300U' forms a convex corner 300B, and the concave corner 300A is far away from the U-shaped segment 300U'.

Referring to FIG. 5 , a high voltage device 40 is shown. The multiple U-shaped segments 300U of the high voltage device 40 may be arranged continuously along the two sides adjacent to the multiple level shifters 400. The multiple U-shaped segments 300U arranged continuously may present a shape similar to a winding snake. According to some embodiments of the present invention, the multiple U-shaped segments 300U arranged continuously may further increase the extended size (e.g., the trace width) of the transistor 300, while saving the area of the entire ring on the chip. On the left side of the loop, the linear portion 300U-1 of each U-shaped segment 300U may be directly adjacent to the linear portion 300U-2 of the upper U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U may be directly adjacent to the linear portion 300U-1 of the lower U-shaped segment 300U. On the right side of the loop, the linear portion 300U-1 of each U-shaped segment 300U may be directly adjacent to the linear portion 300U-2 of the lower U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U may be directly adjacent to the linear portion 300U-1 of the upper U-shaped segment 300U. In order to ensure that the transistor 300 extends uninterruptedly, the linear portion 300U-1 of each U-shaped segment 300U needs to be adjacent to the linear portion 300U-2 of the adjacent U-shaped segment 300U, and the linear portion 300U-2 of the U-shaped segment 300U needs to be adjacent to the linear portion 300U-1 of the adjacent U-shaped segment 300U.

Continuing to refer to FIG. 5 , when multiple U-shaped segments 300U are connected, multiple U-shaped segments 300U′ in a flip-chip arrangement can be indirectly formed. Since multiple U-shaped segments 300U are arranged continuously, multiple U-shaped segments 300U′ are also arranged continuously. As mentioned previously, each U-shaped segment 300U′ may include two linear portions and an arc portion connecting the two linear portions. For example, when the linear portion 300U-2 of the lower U-shaped segment 300U is connected to the linear portion 300U-1 of the upper U-shaped segment 300U (on the right side of the ring), the linear portion 300U-2 of the lower U-shaped segment 300U and the linear portion 300U-1 of the upper U-shaped segment 300U can be respectively regarded as two linear portions of the U-shaped segment 300U', and the two linear portions of the U-shaped segment 300U' are connected through the arc portion of the U-shaped segment 300U'. As mentioned above, the arc portion 300U-3 of the U-shaped segment 300U is close to the low pressure area 100B, and the arc portion of the U-shaped segment 300U' is close to the high pressure area 100A. Furthermore, the linear portion 300U-1 and the linear portion 300U-2 of the U-shaped segment 300U are directly adjacent to and share a single drain region 340, and the two linear portions of the U-shaped segment 300U' are directly adjacent to and share a single source region 320. The arc portion of each U-shaped segment 300U' forms a convex corner 300B. Since multiple U-shaped segments 300U' cross the two side neighbors where multiple level shifters 400 are located, the transistor 300 of the high voltage device 40 does not have a concave corner 300A.

FIG. 6 is a forward current-dimension curve 50 of a high voltage device according to some embodiments of the present invention. According to some embodiments of the present invention, the forward current-dimension curve 50 shows the effect of the extended dimension (e.g., trace width) of the transistor 300 on the forward current of the transistor 300. It should be understood that the first three points (indicated by dashed lines) of the forward current-dimension curve 50 are actually measured data points, which are then extrapolated toward the positive horizontal axis using a linear model. As shown in the forward current-dimension curve 50, if the transistor 300 is to achieve a forward current of 100 mA, the transistor 300 needs to have an extended dimension (e.g., trace width) of about 5500 μm. Depending on the application and design requirements, the trace width of the transistor 300 can be designed to cope with the desired forward current. In addition, by using any of the designs of Figures 2 to 5 with a U-shaped segment 300U (and/or a U-shaped segment 300U'), the trace width of the transistor 300 can be increased while saving the area of the entire ring on the chip.

The high voltage device of the present invention integrates a self-lifting diode and a high voltage junction boundary element in an embedded configuration. The transistor in the self-lifting diode can extend along the ring shape of the high voltage junction boundary element to have a relatively large extension dimension (e.g., trace width). It should be understood that when the extension dimension of the transistor (e.g., trace width) is larger, the forward current of the transistor is also higher, thereby driving the self-lifting diode. In order to cope with the required extension dimension of the transistor, the ring shape of the high voltage junction boundary element must also be designed to occupy a larger chip area, resulting in a waste of chip area. The inventors found that the contour of the ring can be designed to have one or more U-shaped segments (presenting a shape similar to a hairpin bend) or multiple U-shaped segments arranged continuously (presenting a shape similar to a winding snake). The U-shaped segment is characterized by having a slender contour, thereby saving the space occupied by the entire ring. Furthermore, since the U-shaped segment has two correspondingly arranged linear parts, it can contribute to the wiring width of the transistor to at least twice the overall length of the U-shaped segment. In this way, the wiring width of the transistor arranged along the ring can be increased, while at the same time saving the area of the entire ring on the chip. As a result, the forward current of the transistor increases, thereby more effectively avoiding leakage current.

The above summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the perspectives of the embodiments of the present invention. Those with ordinary knowledge in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

20: High voltage device

100: High voltage junction boundary element

100A: High voltage area

100B: Low pressure area

200: Isolation diode

300: Transistor

300A: Recessed corner

300B: convex corner

300U: U-shaped segment

300U-1: Linear part

300U-2: Linear part

300U-3: Arc section

320: Source area

340: Drain area

360: Gate structure

400:Level shifter

Claims (18)

A high voltage device comprises: a high voltage junction termination (HVJT) element; a transistor extending along a ring of the high voltage junction termination element, wherein the transistor has one or more first U-shaped segments from a top view, wherein each first U-shaped segment comprises: a first linear portion; a second linear portion arranged corresponding to the first linear portion; and a first arcuate portion connecting the first linear portion and the second linear portion; and an isolation diode electrically connected to the transistor, wherein the isolation diode and the transistor constitute a bootstrap diode (BSD). A high voltage device as claimed in claim 1, wherein the first linear portion is directly adjacent to the second linear portion. The high voltage device of claim 1 further comprises a plurality of level shifters located on the ring of the high voltage junction boundary element. A high voltage device as claimed in claim 3, wherein the level shifters are separated from each other. A high voltage device as claimed in claim 3, wherein the level shifters are isolated from the transistor. A high voltage device as claimed in claim 3, wherein the transistor and the level shifters have the same conductivity type. A high voltage device as claimed in claim 1, wherein the ring shape of the high voltage junction boundary element defines a high pressure (high side) region and a low pressure (low side) region, respectively inside the ring shape and outside the ring shape. A high voltage device as claimed in claim 7, wherein the isolation diode is located in the low voltage region. A high voltage device as claimed in claim 7, wherein the transistor extending from the high voltage region has a concave corner and a convex corner. A high-pressure device as claimed in claim 9, wherein the concave corner is far away from the first U-shaped segments, and the convex corner is close to the first U-shaped segments. A high voltage device as claimed in claim 7, wherein the transistor further comprises: a source region disposed near the low voltage region; a drain region disposed near the high voltage region; and a gate structure disposed between the source region and the drain region. A high voltage device as claimed in claim 11, wherein the transistor is a laterally diffused metal-oxide semiconductor (LDMOS) transistor. A high voltage device as claimed in claim 11, wherein the first linear portion and the second linear portion share a single drain region. A high-pressure device as claimed in claim 11, wherein the first U-shaped segments are arranged continuously, and the first arc portion of each first U-shaped segment is close to the low-pressure area. A high voltage device as claimed in claim 14, wherein the transistor has a plurality of second U-shaped segments, wherein each second U-shaped segment comprises: a third linear portion; a fourth linear portion, arranged corresponding to the third linear portion; and a second arcuate portion, connecting the third linear portion and the fourth linear portion. A high voltage device as claimed in claim 15, wherein the third linear portion is directly adjacent to the fourth linear portion. A high voltage device as claimed in claim 16, wherein the third linear portion and the fourth linear portion share a single source region. A high-pressure device as claimed in claim 15, wherein the second U-shaped segments are arranged continuously, and the second arc portion of each second U-shaped segment is close to the high-pressure area.

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