TWI850054B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes: a substrate having a first conductive type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductive type different from the first conductive type; a buried layer structure disposed in the substrate and having the second conductive type; a well region disposed in the epitaxial layer and having the second conductive type; a drift region disposed in the epitaxial layer and having the first conductive type; a source region and a drain region disposed respectively in the well region and the drift region, and having the first conductive type; and first high-voltage well regions disposed in the epitaxial layer and having the first conductive type. The first high-voltage well regions are simultaneously in direct contact with the buried layer structure and the well region, or simultaneously in direct contact with the buried layer structure and the drift region.

Description

Semiconductor Devices

The present invention relates to semiconductor devices, and more particularly to buried layer structures and high-pressure well configurations.

High voltage semiconductor device technology is applicable to microwave/RF power amplifiers. Traditional high voltage semiconductor devices, such as vertically diffused metal-oxide semiconductor (VDMOS) transistors and laterally diffused metal-oxide semiconductor (LDMOS) transistors, are mainly used in device applications above 12V. The advantages of high voltage semiconductor devices are cost-effectiveness and compatibility with other processes. They have been widely used in display driver integrated circuit devices, power supplies, power management, communications, automotive electronics, or industrial control.

Although existing high voltage semiconductor devices have generally met their original purposes, they are not satisfactory in all aspects. For example, the breakdown voltage, vertical punch-through voltage, and on-state resistance need to be further improved. Therefore, there are still some problems to be overcome in high voltage semiconductor devices and manufacturing technology.

A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer structure disposed in the substrate, wherein the buried layer structure has the second conductivity type; a well region disposed in the epitaxial layer, wherein the well region has the second conductivity type; a drift region disposed in the epitaxial layer, wherein the drift region has the first conductivity type; a source region and a drain region disposed in the well region and in the drift region, respectively, wherein the source region and the drain region have the first conductivity type; and a plurality of first high-voltage well regions disposed in the epitaxial layer, wherein the first high-voltage well regions have the first conductivity type. The first high-pressure well region directly contacts the buried structure and the well region at the same time, or directly contacts the buried structure and the drift region at the same time.

The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description of a first component formed on a second component may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the present invention may repeat component symbols and/or letters in various examples. Such repetition is for the purpose of simplification and clarity, and does not itself dominate the relationship between the various embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to bonding and connection, such as "connected", "interconnected", etc., unless specifically defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, wherein other structures are disposed between the two structures.

Furthermore, spatially relative terms may be used herein, such as "below," "below," "below," "above," "above," and the like, to describe the relationship between an element or component and other elements or components as shown in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is rotated to other orientations (rotated 90° or other orientations), the spatially relative descriptions used herein may also be interpreted based on the rotated orientation.

The terms "about", "approximately" and "generally" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The numerical values given herein are approximate values, that is, in the absence of specific description of "about", "approximately" or "generally", the given numerical values may still imply the meaning of "about", "approximately" or "generally".

Some embodiments of the present invention are described below. Additional steps may be provided before, during, and/or after the various stages described in these embodiments. Additional components may be added to the semiconductor device structure. Some of the components described may be replaced or omitted in different embodiments. Although some embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those of ordinary skill in the art to which the present invention belongs. It is understood that these terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

The semiconductor device of the present invention is an embodiment of a high voltage integrated circuit, in particular, an embodiment of a laterally diffused metal-oxide semiconductor (LDMOS) transistor. In the prior art, the doping concentration and structural profile of each semiconductor region of the LDMOS transistor are usually adjusted during the manufacturing process so that the LDMOS transistor generates a sufficiently high breakdown voltage and vertical punch-through voltage, as well as a sufficiently low on-state resistance, so as to further optimize the overall performance. However, in actual manufacturing processes, such as the integrated bipolar complementary metal oxide semiconductor - double diffused metal oxide semiconductor (BCD) process, adjusting the doping concentration or structural profile of the semiconductor region may require the use of additional masks, which increases the overall manufacturing cost. In addition, in order to achieve effective isolation and electrical grounding, a large area is generally consumed to form one or more well regions. In this way, although the semiconductor device can be ensured to have acceptable performance, it cannot meet the market's demand for device size miniaturization.

In order to improve the breakdown voltage, vertical punchthrough voltage, and on-resistance of a laterally diffused metal oxide semiconductor transistor, the prior art adds a double diffused buried layer structure with a stepped profile to the diffused metal oxide semiconductor transistor. In addition to crossing the source and drain regions of the transistor, the buried layer structure also includes components extending downward to different junction depths. In other words, the buried layer structure can simultaneously add a vertically assisted depletion layer (VADL) and a laterally assisted depletion layer (LADL), thereby improving the breakdown voltage, vertical punchthrough voltage, and on-resistance of the overall device.

In the embodiment of the present invention, the original first high voltage well region is designed into a plurality of slot components in the diffused metal oxide semiconductor transistor. The inventors have found that the multiple first high voltage well regions in the epitaxial layer contact the buried layer structure and the well region and drift region above (which include the source region and the drain region respectively), which can further improve the breakdown voltage, vertical punch-through voltage, and on-resistance of the overall device. Lateral diffused metal oxide semiconductor transistors with high breakdown voltage and vertical punch-through voltage and low on-resistance can also be widely used in lighting, flat panel display, audio, switch mode power supply, power control and other fields.

FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments of the present invention. In some embodiments, the semiconductor device may include any number of active components and passive components. The active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, laterally diffused metal-oxide semiconductor transistors, bipolar-complementary metal-oxide semiconductor-bisporus metal-oxide semiconductor transistors, planar transistors, fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA FETs), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures. For simplicity, FIG. 1 only shows an exemplary LDMOS transistor.

1 , the semiconductor device 10 may include a substrate 100, an epitaxial layer 102, a buried structure 104, a first isolation structure 132a, a second isolation structure 132b, a third isolation structure 132c, a fourth isolation structure 132d, a gate structure 136, an interlayer dielectric layer 140, a first via 142, a second via 144, a third via 146, a substrate electrode 152, a source electrode 154, and a drain electrode 156. In some embodiments, the epitaxial layer 102 may include a plurality of first high voltage well regions 110, a second high voltage well region 112, a third high voltage well region 114, a well region 116, a drift region 118, and a well region 120. The third high voltage well region 114 may include a doped region 122. The well region 116 may include a heavily doped region 124 and a source region 126. The drift region 118 may include a drain region 128. Furthermore, the buried layer structure 104 may include a first buried layer 106 and a second buried layer 108.

Referring to FIG. 1 , the substrate 100 may be, for example, a wafer or a die, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor including germanium (Ge); a compound semiconductor including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AAs), and/or indium antimonide (InSb). AlInAs alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and/or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In addition, the substrate 100 may be a first conductivity type or a second conductivity type different from the first conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may be doped with appropriate dopants (or impurities) individually. P-type dopants may include boron (B), indium (In), aluminum (Al), and gallium (Ga), while N-type dopants may include phosphorus (P) and arsenic (As). In a specific embodiment of the present invention, the substrate 100 may be of a first conductivity type (P-type) with a doping concentration between 1×10 ¹⁹ cm ^-3 and 3×10 ¹⁹ cm ^-3 .

In other embodiments, the substrate 100 may include an isolation structure (not shown) to define the active region and electrically isolate the active region components within or on the substrate 100, but the embodiments of the present invention are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form a trench extending from the top surface of the substrate 100 to a position within the substrate 100, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a nitrogen-rich liner (e.g., silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (e.g., silicon dioxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Thereafter, an annealing process is performed on the insulating material in the trench, and a planarization process (e.g., chemical mechanical polishing (CMP)) is performed on the substrate 100 to remove excess insulating material, so that the insulating material in the trench is flush with the top surface of the substrate 100.

Continuing with reference to FIG. 1 , an epitaxial layer 102 is formed on the substrate 100. According to some embodiments of the present invention, the epitaxial layer 102 has a second conductivity type (N-type) and a doping concentration thereof is between 1.13×10 ¹⁵ cm ^-3 and 2.30×10 ¹⁵ cm ^-3 . In a specific embodiment of the present invention, the substrate 100 and the epitaxial layer 102 may have different conductivity types, and the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 102. The material of the epitaxial layer 102 may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer 102 may be between 3 μm and 7 μm. The epitaxial layer 102 may be formed by an epitaxial process, and the epitaxial process may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

1 , the semiconductor device 10 includes a buried structure 104 disposed in a substrate 100 and an epitaxial layer 102, which includes a first buried layer 106 and a second buried layer 108. Since the second buried layer 108 and the drift region 118 above can be formed by the same mask, even if the buried structure 104 has two different components, the number of masks required for the semiconductor device 10 as a whole will not increase, and thus the manufacturing cost or cycle will not increase significantly. In some embodiments, the first buried layer 106 and the second buried layer 108 have a second conductivity type (N type). According to some embodiments of the present invention, the first buried layer 106 is laterally adjacent to the second buried layer 108, and the bottom surface of the second buried layer 108 is lower than the bottom surface of the first buried layer 106. In some alternative embodiments, the first buried layer 106 and the second buried layer 108 may be laterally separated, depending on the application and design requirements.

The method for forming the first buried layer 106 and the second buried layer 108 may include, before forming the epitaxial layer 102, ion implanting N-type dopants (such as phosphorus or arsenic) in the substrate 100, performing a heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 102 on the substrate 100. In some embodiments, since the epitaxial layer 102 is formed under high temperature conditions, the implanted ions diffuse into the epitaxial layer 102. As shown in FIG. 1 , the first buried layer 106 and the second buried layer 108 are located near the interface between the substrate 100 and the epitaxial layer 102, and have a portion in the substrate 100 and another portion in the epitaxial layer 102. In other words, the buried structure 104 may extend upward from the interface between the substrate 100 and the epitaxial layer 102. Since the first buried layer 106 and the second buried layer 108 are diffused in the same epitaxial process, the entire top of the buried structure 104 may have a planarized surface.

The function of the first buried layer 106 is to provide a more complete isolation below the source region, which helps to prevent leakage current and further improve the breakdown voltage of the entire device. The location of the first buried layer 106 can be regarded as a high-side region of the semiconductor device 10. In some embodiments, the doping concentration of the first buried layer 106 can be between 1×10 ¹⁵ cm ^-3 and 5×10 ¹⁵ cm ^-3 . According to some embodiments of the present invention, the doping concentration of the first buried layer 106 is higher than the doping concentration of the second buried layer 108. By design, in addition to having a relatively high doping concentration, the first buried layer 106 has a denser distribution of dopants. Therefore, the vertical dimension of the first buried layer 106 is smaller than the vertical dimension of the second buried layer 108. The vertical dimension of the first buried layer 106 may be between 4 μm and 5 μm. The lateral dimension of the first buried layer 106 may cross the second high voltage well region 112 and the well region 116 in the epitaxial layer 102. The extent of the lateral extension depends on the need for depletion region isolation. According to some embodiments, a complete depletion region can reduce leakage current and improve the breakdown voltage, vertical breakdown voltage, and on-resistance of the overall device.

The function of the second buried layer 108 is to provide a larger junction depth below the drift region 118 so that the depletion region can expand in the vertical direction to increase the vertical punch-through voltage. The location of the second buried layer 108 can be regarded as a low-side region of the semiconductor device 10. Furthermore, the junction depth can be the junction area from the epitaxial layer 102 to the substrate 100, which is defined by the buried layer structure 104. In some embodiments, the doping concentration of the second buried layer 108 can be between 1.5×10 ¹⁵ cm ^-3 and 4.5×10 ¹⁵ cm ^-3 . As mentioned above, the doping concentration of the first buried layer 106 is higher than the doping concentration of the second buried layer 108. By design, the second buried layer 108 has a relatively low doping concentration and a more dispersed distribution of dopants. Therefore, the vertical dimension of the second buried layer 108 is about twice that of the first buried layer 106, that is, it has a wider junction, which can more effectively prevent leakage current between the drift region 118 and the substrate 100 below. It is worth noting that since the plurality of first high-voltage well regions 110 formed on the second buried layer 108 have a very high doping concentration, the dopant of the second buried layer 108 will not diffuse upward, but diffuse into the substrate 100 below with a lower doping concentration. That is, the top surface of the first buried layer 106 and the top surface of the second buried layer 108 may be maintained substantially coplanar with each other.

According to some embodiments of the present invention, the first buried layer 106 and the second buried layer 108 of the buried structure 104 have different doping distributions, so a stepped profile is formed at the bottom. The buried structure 104 can simultaneously maintain the characteristics of a continuous structure and double diffusion. The junction depth of the second buried layer 108 is greater than the junction depth of the first buried layer 106, so that the portion of the depletion region located below the drift region 118 can be further expanded downward. In some embodiments, the drift region 118 can be regarded as a region between the gate terminal and the drain terminal, and thus has a critical impact on the overall device performance. As the depletion region below the drift region 118 expands downward, the area between the drift region 118 and the depletion region below it becomes larger, thereby creating a larger electric field. The reduced surface field (RESURRF) effect on the epitaxial layer 102 can also be enhanced. The buried structure 104 realizes a continuous structure, a gradual change in doping concentration, and an expansion of the depletion region. When the doping concentration and the electric field can be controlled to be more balanced, the depletion region can be "exhausted" more completely, which helps to optimize the characteristics of the overall device.

Continuing to refer to FIG. 1 , a plurality of first high-pressure well regions 110, second high-pressure well regions 112, third high-pressure well regions 114, well regions 116, drift regions 118, and well regions 120 may be formed in the epitaxial layer 102. The second high-pressure well regions 112 and the third high-pressure well regions 114 extend vertically from the upper surface of the epitaxial layer 102 to the interface between the substrate 100 and the epitaxial layer 102, or to the interface between the epitaxial layer 102 and the buried structure 104. The well regions 116 and the drift regions 118 extend vertically from the upper surface of the epitaxial layer 102 into the epitaxial layer 102. The well region 120 extends vertically downward from the lower surface of the drift region 118 into the epitaxial layer 102. The plurality of first high-voltage well regions 110 are vertically located between the buried structure 104 and the well region 116, or vertically located between the buried structure 104 and the drift region 118. In some embodiments, the plurality of first high-voltage well regions 110 directly contact the first buried layer 106 and the well region 116 of the buried structure 104, or directly contact the second buried layer 108 and the drift region 118 of the buried structure 104. According to some embodiments of the present invention, the first high-voltage well region 110, the third high-voltage well region 114, the drift region 118, and the well region 120 may be of a first conductivity type (P type), and the second high-voltage well region 112 and the well region 116 may be of a second conductivity type (N type). Since the semiconductor regions with the first conductivity type and the semiconductor regions with the second conductivity type are alternately arranged in the horizontal direction and in the vertical direction, a bipolar (PNP) junction is formed, which can further improve the charge balance state, so that the expected depletion region will be more completely "depleted".

The plurality of first high pressure well regions 110, second high pressure well regions 112, third high pressure well regions 114, well regions 116, drift regions 118, and well regions 120 may be formed by, for example, ion implantation and/or diffusion processes. In alternative embodiments, instead of using ion implantation and/or diffusion processes, the plurality of first high pressure well regions 110, second high pressure well regions 112, third high pressure well regions 114, well regions 116, drift regions 118, and well regions 120 may be doped in situ during the growth of the epitaxial layer 102. In other embodiments, both in situ and implantation doping may be used together.

In the conventional design, the first high-voltage well region 110 is a single component, extending vertically from the upper surface of the epitaxial layer 102 to the interface between the substrate 100 and the epitaxial layer 102, or extending to the interface between the epitaxial layer 102 and the buried structure 104. Then, a well region 116 and a drift region 118 can be formed in the first high-voltage well region 110. Since the first high-voltage well region 110 of the single component extends too far, the depletion region cannot be completely "depleted", especially the region near the drain end. In addition, the impact ionization between electrons and holes cannot be concentrated at the drain end, which easily causes leakage current.

According to some embodiments of the present invention, the first high-pressure well region 110 can be configured as a plurality of slot-type components. Each first high-pressure well region 110 can be laterally surrounded by the epitaxial layer 102 with a lower doping concentration. Although one first high-pressure well region 110 is shown to directly contact the first buried layer 106 and the well region 116 at the same time, and two first high-pressure well regions 110 are directly contacted with the second buried layer 108 and the drift region 118 at the same time, the embodiments of the present invention are not limited thereto. Any number of first high-pressure well regions 110 can be set between the first buried layer 106 and the well region 116, or between the second buried layer 108 and the drift region 118, depending on the application and design requirements. In some embodiments, the doping concentration of the first high-pressure well region 110 may be between 7×10 ¹⁵ cm ^-3 and 9×10 ¹⁵ cm ^-3 . Multiple first high-pressure well regions 110 may allow the depletion region to be more completely "depleted", especially the region near the drain end. In addition, the collision ionization between electrons and holes may be more concentrated at the drain end, thereby avoiding leakage current.

In some embodiments, the second high-pressure well region 112 may be laterally located between the well region 116 and the third high-pressure well region 114. As shown in FIG. 1 , the second high-pressure well region 112 is not in direct contact with the plurality of first high-pressure well regions 110. In some embodiments, the doping concentration of the second high-pressure well region 112 may be between 1×10 ¹⁶ cm ^-3 and 3×10 ¹⁶ cm ^-3 . The first buried layer 106 may partially extend below the second high-pressure well region 112. As previously mentioned, the extension of the first buried layer 106 may provide more complete isolation, which helps prevent leakage current.

In some embodiments, the third high voltage well region 114 may be laterally adjacent to the second high voltage well region 112. In some embodiments, the doping concentration of the third high voltage well region 114 may be between about -5×10 ¹⁷ cm ^-3 and -1×10 ¹⁷ cm ^-3 . The third high voltage well region 114 may include a doped region 122 formed subsequently. Since the substrate 100, the third high voltage well region 114, and the doped region 122 are all of the first conductivity type (P type), the substrate electrode 152 formed subsequently may allow the semiconductor device 10 to be grounded from the top or from the bottom.

In some embodiments, the well region 116 may be located above the first buried layer 106 of the buried structure 104. The well region 116 may extend downward from the upper surface of the epitaxial layer 102, and the first high-voltage well region 110 may be vertically located between the first buried layer 106 of the buried structure 104 and the well region 116. According to some embodiments of the present invention, the first high-voltage well region 110 directly contacts the first buried layer 106 and the well region 116 at the same time. In some embodiments, the doping concentration of the well region 116 may be between 1×10 ¹⁶ cm ^-3 and 2×10 ¹⁶ cm ^-3 . The thickness of the well region 116 may be between 2.0 μm and 2.5 μm. As previously mentioned, the well region 116 may include a heavily doped region 124 and a source region 126 .

In some embodiments, the drift region 118 may be located above the second buried layer 108 of the buried structure 104. The drift region 118 may extend downward from the upper surface of the epitaxial layer 102, and the first high-pressure well region 110 may be vertically located between the second buried layer 108 of the buried structure 104 and the drift region 118. According to some embodiments of the present invention, the first high-pressure well region 110 directly contacts the second buried layer 108 and the drift region 118 at the same time. The well region 116 and the drift region 118 are separated laterally. As previously mentioned, the drift region 118 and the second buried layer 108 may have the same lateral size, so the same mask can be used in the manufacturing process to further reduce the manufacturing cost. The drift region 118 can enable the semiconductor device 10 to generate a very long depletion region under high voltage operation, thereby reducing the phenomenon of excessive electric field concentration to increase the breakdown voltage. In addition, the doping of the drift region 118 will also determine the on-resistance of the semiconductor device 10. In some embodiments, the doping concentration of the drift region 118 can be between -8×10 ¹⁵ cm ^-3 and -7×10 ¹⁵ cm ^-3 . The thickness of the drift region 118 can be between 2μm and 4μm. As mentioned previously, the drift region 118 can include a drain region 128.

In some embodiments, the well region 120 may be located below the drift region 118. The well region 120 may extend downward from the lower surface of the drift region 118. According to some embodiments of the present invention, the well region 120 is a key region that helps to improve the quasi-saturation problem of the saturated drain current, thereby improving the breakdown voltage. The well region 120 may directly contact the drift region 118, but does not touch the second buried layer 108 of the buried structure 104. The first high voltage well region 110 and the well region 120 are separated laterally. In some embodiments, the doping concentration of the well region 120 may be between -4×10 ¹⁵ cm ^-3 and -5×10 ¹⁵ cm ^-3 . The thickness of the well region 120 may be between 3.6 μm and 4 μm.

Referring to FIG. 1 , a heavily doped region 124 and a source region 126 may be formed in the well region 116, and may extend downward from the upper surface of the well region 116. According to some embodiments of the present invention, the heavily doped region 124 may be of the second conductivity type (N type), and the source region 126 may be of the first conductivity type (P type). The heavily doped region 124 and the source region 126 are laterally adjacent to each other. The formation method of the heavily doped region 124 and the source region 126 may be similar to the formation method of the plurality of first high voltage well regions 110, the second high voltage well region 112, the third high voltage well region 114, the well region 116, the drift region 118, and the well region 120, and the details thereof will not be repeated herein.

In some embodiments, the doping concentration of the heavily doped region 124 may be between 1.0×10 ¹⁹ cm ^-3 and 1.5×10 ¹⁹ cm ^-3 . The heavily doped region 124 may be coupled to the source electrode 154 simultaneously with the source region 126. The thickness of the heavily doped region 124 may be between 0.2 μm and 0.5 μm. According to some embodiments of the present invention, the heavily doped region 124 having the second conductivity type may achieve charge balance with the source region 126 having the first conductivity type and provide an ohmic contact of the second conductivity type to the source electrode 154. In addition, since the well region 116 and the heavily doped region 124 have the same conductivity type, the heavily doped region 124 can serve as a source terminal body connected to the source region 126 and play a key role in the electrical grounding of the source terminal.

In some embodiments, the doping concentration of the source region 126 may be between 2×10 ¹⁸ cm ^-3 and 2×10 ¹⁹ cm ^-3 . The thickness of the source region 126 may be between 0.2 μm and 0.5 μm. According to some embodiments of the present invention, the well region 116 and the source region 126 may define a channel with sufficient width to avoid parasitic conduction problems or short channel effects.

Continuing with reference to FIG. 1 , a drain region 128 may be formed in the drift region 118 and may extend downward from the upper surface of the drift region 118 . According to some embodiments of the present invention, the drain region 128 may be of the first conductivity type (P-type). In some embodiments, the doping concentration of the drain region 128 may be between 2×10 ¹⁸ cm ^-3 and 2×10 ¹⁹ cm ^-3 . The thickness of the drain region 128 may be between 0.3 μm and 0.6 μm. The drain region 128 may be coupled to the drain electrode 156 . The formation method of the drain region 128 may be similar to the formation method of the first high pressure well region 110, the second high pressure well region 112, the third high pressure well region 114, the well region 116, the drift region 118, and the well region 120, and the details thereof will not be repeated here.

1 , a first isolation structure 132a, a second isolation structure 132b, a third isolation structure 132c, and a fourth isolation structure 132d may be formed on the epitaxial layer 102. Specifically, since the manufacturing process thereof involves high temperature treatment, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d are partially embedded in the epitaxial layer 102. According to some embodiments of the present invention, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d may be drift oxide (DOX) for isolating various conductive components to prevent an electrical short circuit from occurring during operation of the semiconductor device 10.

As shown in FIG. 1 , the doped region 122 in the third high voltage well region 114 may be laterally located between the first isolation structure 132a and the second isolation structure 132b. The second isolation structure 132b may laterally isolate the doped region 122 from the well region 116. The heavily doped region 124 and the source region 126 in the well region 116, as well as the gate structure 136 may be laterally located between the second isolation structure 132b and the third isolation structure 132c. It should be noted that the gate structure 136 may extend over a portion of the surface of the third isolation structure 132c. The drain region 128 in the drift region 118 may be laterally located between the third isolation structure 132c and the fourth isolation structure 132d.

In some embodiments, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d may be formed by silicon oxide (SiO), which may be a silicon partial oxidation isolation structure formed by thermal oxidation. In other embodiments, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d may be a shallow trench isolation structure formed by etching, oxidation, and deposition processes.

Continuing to refer to FIG. 1 , after forming the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d, a gate structure 136 may be formed on the epitaxial layer 102. The gate structure 136 may extend horizontally from the well region 116 through the epitaxial layer 102 and reach the drift region 118. The portion of the epitaxial layer 102 or the portion of the well region 116 contacted by the gate structure 136 may be regarded as a channel region of the semiconductor device 10, and the gate structure 136 may serve as a gate terminal of an active component. According to some embodiments of the present invention, the source region 126, the drain region 128, and the gate structure 136 may form a transistor of a first conductivity type (P-type), such as a lateral diffused metal oxide semiconductor transistor. The transistor has a channel region of a second conductivity type (N-type). The thickness of the gate structure 136 may be between 0.25 μm and 0.30 μm. In some embodiments, the gate structure 136 may include a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer. In other embodiments, the semiconductor device 10 may have a transistor of the second conductivity type (N type) and a channel region of the first conductivity type (P type), and a buried layer structure of the first conductivity type (P type), but such a configuration is relatively rare in the industry.

The material of the gate dielectric layer may include a high-k dielectric material (e.g., a material having a K value greater than 7), which may include hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (Al ₂ O ₃ ), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO ₂ ), titanium oxide (TiO), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), silicon oxynitride, or other suitable high dielectric constant materials. The gate dielectric layer of the gate structure 136 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), other similar methods, or a combination thereof.

The material of the gate electrode may include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicide (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbide (such as tantalum carbide (TaC), tantalum carbonitride (tantalum carbonitride, TaCN, or other similar materials), metal oxides, and metals. The metal may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, combinations thereof, or multiple layers thereof. The gate electrode of the gate structure 136 may be formed by physical vapor deposition (PVD), atomic layer deposition, plating, other suitable processes, or a combination thereof.

1 , an interlayer dielectric layer 140 may be formed on the epitaxial layer 102. In some embodiments, the interlayer dielectric layer 140 may cover the epitaxial layer 102, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, the fourth isolation structure 132d, and the gate structure 136. In addition to providing mechanical protection and insulation for the components below, the interlayer dielectric layer 140 may also isolate different levels of conductive materials. The material of the interlayer dielectric layer 140 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO _x N _y C _1-xy , where x and y are in the range of 0 to 1), tetraethoxysilane (tetra ethyl ortho silicate, TEOS), undoped silica glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low dielectric constant (low-k) dielectric material, or other suitable dielectric materials.

The thickness of the interlayer dielectric layer 140 may be between 6000 Å and 8000 Å. The interlayer dielectric layer 140 may be formed by spin-on coating, chemical vapor deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Next, a planarization process (such as chemical mechanical polishing) may be performed on the interlayer dielectric layer 140 to make the interlayer dielectric layer 140 have a flat top surface.

Continuing with reference to FIG. 1 , a first via 142, a second via 144, and a third via 146 may be formed through the interlayer dielectric layer 140. The first via 142, the second via 144, and the third via 146 may respectively physically contact the doped region 122, the heavily doped region 124, the source region 126, and the drain region 128. In addition, a base electrode 152, a source electrode 154, and a drain electrode 156 may be formed on the interlayer dielectric layer 140. In some embodiments, the base electrode 152 is electrically coupled to the doped region 122 through the first via 142, the source electrode 154 is electrically coupled to the heavily doped region 124 and the source region 126 through the second via 144, and the drain electrode 156 is electrically coupled to the drain region 128 through the third via 146. As mentioned previously, the base electrode 152 can serve as an electrical ground for the semiconductor device 10. The source electrode 154 and the drain electrode 156 can serve as a source terminal and a drain terminal of a transistor, respectively.

The first via 142, the second via 144, the third via 146, the base electrode 152, the source electrode 154, and the drain electrode 156 may be formed in one piece and thus include the same material, which may be similar to the material of the gate electrode of the gate structure 136, and the details thereof will not be repeated here. First, a plurality of openings may be formed in the interlayer dielectric layer 140, corresponding to the doped region 122, the heavily doped region 124, the source region 126, and the drain region 128, respectively. Then, the above materials may be blanket deposited on the interlayer dielectric layer 140 by a suitable deposition process. In addition to being formed on the surface of the interlayer dielectric layer 140, the above-mentioned materials are also filled into all the openings to form the first via 142, the second via 144, and the third via 146. The deposited film layer can be patterned by a lithography process followed by an etching process to form a base electrode 152, a source electrode 154, and a drain electrode 156. The lithography process may include coating photoresist, soft baking, exposure, post-exposure baking, development, other similar methods, or a combination thereof. The etching process may include dry etching, wet etching, other similar methods, or a combination thereof. Based on the integrated forming process, the base electrode 152, the source electrode 154, and the drain electrode 156 may have substantially the same thickness, which may be between 4000Å and 5000Å.

FIG. 2 is a drain current-voltage curve 20 of a semiconductor device according to some embodiments of the present invention. According to some embodiments of the present invention, the drain current-voltage curve 20 compares the breakdown voltage of two semiconductor devices in the off state. The conventional design (represented by the dotted line) may be a first high voltage well region 110 having a single component, such as extending vertically from the upper surface of the epitaxial layer 102 to the interface between the substrate 100 and the epitaxial layer 102, or extending to the interface between the epitaxial layer 102 and the buried structure 104. The new design (represented by the solid line) may be the semiconductor device 10 disclosed in the present invention, which configures the first high voltage well region 110 into multiple socket-type components. Since the multiple first high-voltage well regions 110 can make the depletion region more completely “exhausted”, the new design (such as the semiconductor device 10) can significantly reduce the leakage current, thereby increasing the breakdown voltage in the off state by about 24%.

FIG. 3 is a drain current-voltage curve 30 of a semiconductor device according to some embodiments of the present invention. According to some embodiments of the present invention, the drain current-voltage curve 30 compares the breakdown voltage of two semiconductor devices in the on state. The conventional design (represented by the dashed line) may be a first high voltage well region 110 having a single component, such as extending vertically from the upper surface of the epitaxial layer 102 to the interface between the substrate 100 and the epitaxial layer 102, or extending to the interface between the epitaxial layer 102 and the buried structure 104. The new design (represented by the solid line) may be the semiconductor device 10 disclosed in the present invention, which configures the first high voltage well region 110 into multiple socket-type components. Since the plurality of first high-voltage well regions 110 can make the depletion region more completely “exhausted”, the new design (such as the semiconductor device 10) can significantly reduce the leakage current at a relatively high voltage, thereby increasing the breakdown voltage of the on-state by about 54%.

In a specific embodiment, the performance of the conventional design and the new design are compared. The structural characteristics and electrical parameters are analyzed by simulation software. The relevant data are summarized in Table 1. Table 1 Structure Critical voltage Breakdown voltage (off) Breakdown voltage (conduction) On resistance Traditional design -0.69V -129V -98V 1212 mΩ-mm ² New design -0.68V -160V -151V 771 mΩ-mm ²

The critical voltage of the novel design of the present invention (e.g., semiconductor device 10) can be maintained at the same level as the critical voltage of the conventional design. As mentioned previously, the off-state breakdown voltage and on-state breakdown voltage of the novel design can be improved by 24% and 54%, respectively. In addition to the excellent breakdown voltage performance, the on-resistance of the novel design can also be improved by about 36%.

FIG. 4 is an electric field-position curve 40 of a semiconductor device according to some embodiments of the present invention. According to some embodiments of the present invention, the electric field-position curve 40 compares the performance of two semiconductor devices. The conventional design (represented by the dotted line) may be a first high voltage well region 110 having a single component, for example, extending vertically from the upper surface of the epitaxial layer 102 to the interface between the substrate 100 and the epitaxial layer 102, or extending to the interface between the epitaxial layer 102 and the buried structure 104. The new design (represented by the solid line) may be the semiconductor device 10 disclosed in the present invention, which configures the first high voltage well region 110 into multiple slot-type components. It is worth noting that the breakdown voltage of the transistor depends on the integral value of the overall electric field curve. In some embodiments, the peak value of the electric field spike should not exceed 3.0×10 ⁵ V/cm, otherwise it is easy to cause device damage. When the electric field peak is too high, it is necessary to optimize the overall electric field to obtain a better balanced distribution.

Referring to FIG. 4 , the peak of the new design in the drift region can be slightly lower than the peak of the traditional design in the drift region, and its electric field peak value is about 2.6×10 ⁵ V/cm. In the drain region of the traditional design, the electric field becomes very weak because the depletion region of the traditional design has not been completely "depleted" and the collision ionization between electrons and holes cannot be concentrated. However, the multiple first high-voltage well regions 110 of the new design can make the depletion region more completely "depleted", and the collision ionization between electrons and holes can be more concentrated in the drain region, thereby avoiding leakage current. The electric field in the drain region of the new design can be significantly improved. As the integral value of the electric field curve increases, the breakdown voltage (off state and on state) of the new design also improves accordingly.

The diffused metal oxide semiconductor transistor of the present invention configures the original first high-voltage well region into a plurality of slot-type components to match the buried structure at the interface between the substrate and the epitaxial layer. The buried structure realizes a continuous structure, a gradual change in doping concentration, and an expansion of the depletion region. Multiple first high-voltage well regions can be arranged in the epitaxial layer to simultaneously contact the buried structure and various semiconductor regions above, so that the depletion region can be further "exhausted" more completely, especially near the drain end. In addition, the collision and ionization between electrons and holes can be more concentrated at the drain end, thereby avoiding leakage current. As a result, the breakdown voltage, vertical breakdown voltage, and on-resistance of the overall device can be further improved.

The above summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the perspectives of the embodiments of the present invention. Those with ordinary knowledge in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

10: Semiconductor devices

20: Drain current-voltage curve

30: Drain current-voltage curve

40: Electric field-position curve

100: Base

102: Epitaxial layer

104:Buried layer structure

106: First buried layer

108: Second buried layer

110: The first high-pressure well area

112: Second High-pressure Well Area

114: The third high-pressure well area

116: Well Area

118: Drift Zone

120: Well Area

122: Mixed Area

124:Heavy Mixing Area

126: Source region

128: Drain area

132a: First isolation structure

132b: Second isolation structure

132c: The third isolation structure

132d: Fourth isolation structure

136: Gate structure

140: Interlayer dielectric layer

142: First guide hole

144: Second guide hole

146: Third guide hole

152: Base electrode

154: Source electrode

156: Drain electrode

The following will be described in detail with the accompanying drawings of various aspects of the embodiments of the present invention. It should be noted that, according to standard practices in the industry, various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present invention. Figure 2 is a drain current-voltage curve diagram of a semiconductor device according to some embodiments of the present invention. Figure 3 is a drain current-voltage curve diagram of a semiconductor device according to some embodiments of the present invention. Figure 4 is an electric field-position curve diagram of a semiconductor device according to some embodiments of the present invention.

10: Semiconductor devices

100: Base

102: Epitaxial layer

104:Buried layer structure

106: First buried layer

108: Second buried layer

110: The first high-pressure well area

112: The second high-pressure well area

114: The third high-pressure well area

116: Well area

118: Drift Zone

120: Well area

122: Mixed area

124:Heavy mixing area

126: Source region

128: Drain area

132a: First isolation structure

132b: Second isolation structure

132c: The third isolation structure

132d: The fourth isolation structure

136: Gate structure

140: Interlayer dielectric layer

142: First guide hole

144: Second guide hole

146: The third guide hole

152: Base electrode

154: Source electrode

156: Drain electrode

Claims (20)

A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer structure disposed in the substrate, wherein the buried layer structure has the second conductivity type; a well region disposed in the epitaxial layer, wherein the well region has the second conductivity type; a drift region disposed in the epitaxial layer, wherein the drift region has the first conductivity type; a source region and a drain region, respectively disposed in the well region and the drift region, wherein the source region and the drain region have the first conductivity type; and a plurality of first high-voltage well regions, disposed in the epitaxial layer, wherein the first high-voltage well regions have the first conductivity type, wherein at least one of the first high-voltage well regions directly contacts the buried structure and the well region at the same time, or directly contacts the buried structure and the drift region at the same time, wherein each of the first high-voltage well regions is laterally surrounded by the epitaxial layer. A semiconductor device as claimed in claim 1, wherein the well region and the drift region extend downward from the upper surface of the epitaxial layer, and the buried layer structure extends upward from the interface between the substrate and the epitaxial layer. A semiconductor device as claimed in claim 2, wherein the first high-voltage well regions are vertically located between the buried structure and the well region. A semiconductor device as claimed in claim 2, wherein the first high-voltage well regions are vertically located between the buried structure and the drift region. A semiconductor device as claimed in claim 1, wherein the buried layer structure further comprises: a first buried layer located below the well region; and a second buried layer laterally adjacent to the first buried layer. A semiconductor device as claimed in claim 5, wherein the bottom surface of the second buried layer is lower than the bottom surface of the first buried layer. A semiconductor device as claimed in claim 6, wherein the bottom of the buried structure has a stepped shape. A semiconductor device as claimed in claim 5, wherein the top of the buried structure has a planarized surface. A semiconductor device as claimed in claim 5, wherein the doping concentration of the first buried layer is higher than the doping concentration of the second buried layer. A semiconductor device as claimed in claim 5, wherein the first high-voltage well regions are in direct contact with the first buried layer and the second buried layer of the buried layer structure. A semiconductor device as claimed in claim 5, wherein the second buried layer is located below the drift region. A semiconductor device as claimed in claim 11, wherein the lateral dimension of the second buried layer is equal to the lateral dimension of the drift region. The semiconductor device of claim 1 further comprises: a second high-voltage well region disposed in the epitaxial layer and having the second conductivity type, wherein the second high-voltage well region is adjacent to the well region; and a third high-voltage well region disposed in the epitaxial layer and having the first conductivity type, wherein the third high-voltage well region is adjacent to the second high-voltage well region. A semiconductor device as claimed in claim 13, wherein the second high-voltage well region is laterally located between the well region and the third high-voltage well region. The semiconductor device of claim 13 further includes a doped region located in the third high voltage well region, wherein the doped region has the first conductivity type. The semiconductor device of claim 15 further includes a heavily doped region laterally adjacent to the source region. The semiconductor device of claim 16 further includes an interlayer dielectric (ILD) layer covering the epitaxial layer. The semiconductor device of claim 17 further comprises: a first via hole, which is arranged to pass through the interlayer dielectric layer and physically contact the doped region; a second via hole, which is arranged to pass through the interlayer dielectric layer and physically contact the heavily doped region and the source region; and a third via hole, which is arranged to pass through the interlayer dielectric layer and physically contact the drain region. A semiconductor device as claimed in claim 18, wherein: a base electrode is electrically coupled to the doped region through the first via; a source electrode is electrically coupled to the heavily doped region and the source region through the second via; and a drain electrode is electrically coupled to the drain region through the third via. The semiconductor device of claim 1 further includes a gate structure laterally disposed between the source region and the drain region.

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