TWI884751B - High voltage device and method forming the same - Google Patents

Abstract

A high voltage device includes: a substrate having a first conductive type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductive type different from the first conductive type; a buried layer disposed in the substrate; a first deep well region disposed in the epitaxial layer and having the second conductive type, wherein the first deep well region is in direct contact with the buried layer; a first well region disposed in the first deep well region and having the second conductive type; and a first doped region and a second doped region disposed in the first well region and both having the second conductive type. The first doped region and the second doped region are vertically in direct contact.

Description

High voltage device and method of forming the same

The present invention relates to a high voltage device and a method for forming the same, and more particularly to a design for improving leakage current.

In most switching applications, switching efficiency is determined by switching loss and switching speed. One way to supply power to a high voltage circuit of a gate driver is to use a bootstrap circuit, which has the advantages of simplicity and low cost. The bootstrap circuit includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR), which can provide the voltage level of the high voltage circuit.

Although existing high voltage devices have generally met their original purpose, they are not satisfactory in all aspects. For example, substrate leakage needs to be further improved. Therefore, there are still some problems to be overcome regarding high voltage devices and manufacturing technology.

A high voltage device includes: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer disposed in the substrate; a first deep well region disposed in the epitaxial layer and having a second conductivity type, wherein the first deep well region directly contacts the buried layer; a first well region disposed in the first deep well region and having the second conductivity type; and a first doped region and a second doped region disposed in the first well region and both having the second conductivity type. The first doped region and the second doped region directly contact each other in a vertical direction.

A method for forming a high voltage device includes: providing a substrate; forming an epitaxial layer on the substrate; forming a first deep well region in the epitaxial layer; forming a first well region in the first deep well region; forming a first doped region in the first well region; and forming a second doped region in the first well region. The second doped region extends from the top surface of the first doped region to the top surface of the first well region.

The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description of a first component formed on a second component may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present invention may repeat component symbols and/or letters in various examples. Such repetition is for the purpose of simplification and clarity, and does not itself dominate the relationship between the various embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to bonding and connection, such as "connected", "interconnected", etc., unless specifically defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, wherein other structures are disposed between the two structures.

Furthermore, spatially relative terms may be used herein, such as "below," "below," "below," "above," "above," and the like, to describe the relationship between an element or component and other elements or components as shown in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is rotated to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein may also be interpreted based on the rotated orientation.

The terms "about", "approximately" and "generally" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The numerical values given herein are approximate values, that is, in the absence of specific description of "about", "approximately" or "generally", the given numerical values may still imply the meaning of "about", "approximately" or "generally".

Some embodiments of the present invention are described below. Additional steps may be provided before, during, and/or after the various stages described in these embodiments. Additional components may be added to the high-voltage device structure. Some of the components may be replaced or omitted in different embodiments. Although some embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as those commonly understood by those of ordinary skill in the art to which the present invention belongs. It is understood that these terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

In order to improve the switching efficiency, a bootstrap circuit can be incorporated into the high voltage device, which includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR). The key parameters of the bootstrap diode in the bootstrap circuit are reverse recovery time, forward conduction voltage drop, and reverse blocking voltage. In traditional designs, the bootstrap diode is generally configured separately. The separated bootstrap diode is set separately from other components of the high voltage device. In order to meet the cut-off withstand voltage requirement, the self-lifting diode must be achieved by relaxing the design rules, which results in a larger component size. Since the separated self-lifting diode is not integrated with other components of the high-voltage device, it may occupy too much space and increase the cost of the additional bill of materials (BOM). Therefore, the above problem can be solved by using an embedded self-lifting diode (that is, a configuration integrated with other components). However, compared to the separated self-lifting diode, the buried self-lifting diode may generate a forward leakage current from the anode terminal to the substrate (vertical bipolar junction or horizontal bipolar junction) during operation, while the cathode terminal has no bipolar junction and no significant reverse leakage current.

A typical high voltage device may include a high voltage junction termination (HVJT) element, at least one pair of level shifters, and at least one pair of high voltage metal oxide semiconductor transistors. The high voltage junction boundary element may have a ring-shaped profile that physically and electrically separates a high voltage (high side) region and a low voltage (low side) region. The high voltage region may accommodate components that operate at a high voltage level, and the low voltage region may accommodate components that operate at a low voltage level. Generally speaking, "high voltage" refers to voltages above 300V, such as between 300V and 1200V, between 300V and 750V, or between 750V and 1200V. "Low voltage" generally refers to voltages below 20V, such as between 1V and 20V, between 1V and 10V, or between 10V and 20V. A pair of high voltage metal oxide semiconductor transistors can be coupled to the high voltage region and the low voltage region, respectively. Furthermore, a pair of level shifters can be integrated in the ring of the high voltage junction boundary element. The level shifter can convert signals between the high voltage region and the low voltage region. For example, the level shifter can receive a control logic signal from the low voltage region and convert it into an input signal for the high voltage region.

When a high voltage device is incorporated into a self-lifting circuit, the power supply can be boosted, and the boosted voltage value is the charging voltage. The potential of the high voltage region can be raised through the self-lifting capacitor, making the circuit conductive. First, during the charging period, the high voltage metal oxide semiconductor transistor coupled to the low voltage region is turned on. The self-lifting diode needs to provide sufficient charging current to increase the charging efficiency. Then, during the discharge period, the high voltage metal oxide semiconductor transistor coupled to the high voltage region is turned on, so that the voltage at the end of the high voltage region reaches more than 600V. In order to improve the charging efficiency and withstand voltages above 600V, the self-lifting diode needs to have a high conduction current and a low base leakage current.

When the self-lifting diode conducts the desired current through the diode (PN) junction path, the unwanted parasitic bipolar (PNP) junction path may also conduct and generate leakage current. Through the parasitic bipolar (PNP) junction path, the leakage current can flow from the well region of the anode end to the well region of the substrate end in the horizontal direction, and can also flow from the well region of the anode end to the substrate below in the vertical direction. The inventors have found that an additional doping structure can be configured between the anode end and the substrate end to limit the leakage current in the horizontal direction, and a buried layer can be configured directly below the anode end to limit the leakage current in the vertical direction. This allows the self-lifting diode to achieve a 1A on-state current and suppress the leakage current to less than 10% (the standard required by the customer).

FIG. 1 is a top view of a high-pressure device 10 according to some embodiments of the present invention. FIG. 2 is a cross-sectional schematic diagram of a high-pressure device 10 according to some embodiments of the present invention. It should be noted that FIG. 2 is a cross-sectional schematic diagram obtained by line segment A-A' of FIG. 1. In some embodiments, the high-pressure device may generally include any number of active components and passive components. The active component includes a metal-oxide semiconductor (MOS) transistor, a complementary metal-oxide semiconductor (CMOS) transistor, a laterally diffused metal-oxide semiconductor (LDMOS) transistor, a bipolar complementary metal oxide semiconductor - double diffused metal oxide semiconductor (BCD) transistor, a bipolar junction transistor (BJT), a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAA FET), other similar devices, or a combination thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures.

Referring to FIGS. 1 and 2 , the high voltage device 10 includes an innovative self-erecting diode. For simplicity, FIG. 1 only shows the layout of all active regions (e.g., doped regions) in the self-erecting diode. Without integration with a high voltage junction boundary element, the self-erecting diode may have a circular design, such as a center circle with a cathode end, and a ring of conductive structures surrounding the cathode end, a ring of an anode end, and a ring of a base end in sequence (described in detail below). Such a design can avoid sharp edge effects, which can cause component failure. In addition, the circular design can also make the electric field distribution more uniform.

Continuing to refer to FIGS. 1 and 2 , the structure of the high voltage device 10 may include a substrate 100, a buried layer 200, an epitaxial layer 300, an isolation structure 500a, an isolation structure 500b, an isolation structure 500c, an isolation structure 500d, an isolation structure 500e, an isolation structure 500f, a conductive structure 600, an interlayer dielectric (ILD) layer 700, a via 710, a via 740, a via 750, a via 760, a via 780, a metal layer 820, a metal layer 840, a metal layer 860, and a metal layer 880.

In some embodiments, the epitaxial layer 300 may include a high-pressure well region 320, a deep well region 340, and a deep well region 360. The high-pressure well region 320 may include a well region 322. The deep well region 340 may include a well region 342 and a well region 344. The deep well region 360 may include a well region 362. The well region 322 may include a doped region 410. The well region 342 may include a doped region 420 and a doped region 430. The well region 344 may include a doped region 440 and a doped region 450. The well region 362 may include a doped region 460. It is noted that the edge of the buried layer 200 laterally extends beyond the edge of the doped region 450 to a spacing D.

In some embodiments, the substrate 100 may be, for example, a wafer or a die, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor including germanium (Ge); a compound semiconductor including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AAs), and/or indium antimonide (InSb). AlInAs alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and/or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In addition, the substrate 100 may be a first conductivity type or a second conductivity type different from the first conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may be doped with appropriate dopants (or impurities) respectively. The P-type dopant may include boron (B), indium (In), aluminum (Al), or gallium (Ga), while the N-type dopant may include phosphorus (P) or arsenic (As). In a specific embodiment of the present invention, the substrate 100 may be of a first conductivity type (P-type) with a doping concentration between 1×10 ¹⁹ cm ^-3 and 3×10 ¹⁹ cm ^-3 .

In other embodiments, the substrate 100 may include an isolation structure (not shown) to define the active region and electrically isolate the active region components within or on the substrate 100, but the embodiments of the present invention are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form a trench extending from the top surface of the substrate 100 to a position within the substrate 100, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a nitrogen-rich liner (e.g., silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (e.g., silicon dioxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Thereafter, an annealing process is performed on the insulating material in the trench, and a planarization process (e.g., chemical mechanical polishing (CMP)) is performed on the substrate 100 to remove excess insulating material, so that the insulating material in the trench is flush with the top surface of the substrate 100.

1 and 2, an epitaxial layer 300 is formed on a substrate 100. According to some embodiments of the present invention, the epitaxial layer 300 may have a second conductivity type (N-type) with a doping concentration between 1.13×10 ¹⁵ cm ^-3 and 2.30×10 ¹⁵ cm ^-3 . In a specific embodiment of the present invention, the substrate 100 and the epitaxial layer 300 may have different conductivity types. The material of the epitaxial layer 300 may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer 300 may be between 3 μm and 7 μm. The epitaxial layer 300 may be formed by an epitaxial process, and the epitaxial process may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

Continuing with reference to FIGS. 1 and 2 , a buried layer 200 is formed in the substrate 100. The buried layer 200 may directly contact the deep well region 340 of the epitaxial layer 300. According to some embodiments of the present invention, the buried layer 200 may limit leakage current in the vertical direction. The buried layer 200 has a second conductivity type (N-type). The doping concentration of the buried layer 200 may be between 6.4×10 ¹⁶ cm ^-3 and 9.6×10 ¹⁶ cm ^-3 . The vertical dimension of the buried layer 200 may be between 1 μm and 2 μm. The lateral dimension of the buried layer 200 may be smaller than the lateral dimension of the deep well region 340.

The method for forming the buried layer 200 may include, before forming the epitaxial layer 300, ion implanting N-type dopants (e.g., phosphorus or arsenic) in the substrate 100, performing a heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 300 on the substrate 100. In some embodiments, since the epitaxial layer 300 is formed under high temperature conditions, the implanted ions diffuse into the epitaxial layer 300. As shown in FIG. 2 , the buried layer 200 is located near the interface between the substrate 100 and the epitaxial layer 300, and has a portion in the substrate 100 and another portion in the epitaxial layer 300. In other words, the buried layer 200 may extend upward from the interface between the substrate 100 and the epitaxial layer 300.

1 and 2 , a high-pressure well region 320, a deep well region 340, and a deep well region 360 may be formed in the epitaxial layer 300. In some embodiments, the high-pressure well region 320, the deep well region 340, and the deep well region 360 are laterally spaced apart from each other, and the deep well region 340 may be located between the high-pressure well region 320 and the deep well region 360. It should be understood that, from a top view, the deep well region 340 surrounds the deep well region 360, and the high-pressure well region 320 surrounds the deep well region 340. The high-pressure well region 320 and the deep well region 360 may extend vertically from the upper surface of the epitaxial layer 300 to the interface between the epitaxial layer 300 and the substrate 100. The deep well region 340 may extend vertically from the upper surface of the epitaxial layer 300 to the interface between the epitaxial layer 300 and the substrate 100, or the interface between the epitaxial layer 300 and the buried layer 200. According to some embodiments of the present invention, the high voltage well region 320 may be of the first conductivity type (P type), and the deep well region 340 and the deep well region 360 may be of the second conductivity type (N type).

The high pressure well region 320, the deep well region 340, and the deep well region 360 may be formed by, for example, ion implantation and/or diffusion processes. In alternative embodiments, instead of using ion implantation and/or diffusion processes, the high pressure well region 320, the deep well region 340, and the deep well region 360 may be doped in situ during the growth of the epitaxial layer 300. In other embodiments, both in situ and implantation doping may be used together.

In some embodiments, the high pressure well region 320 may laterally surround the deep well region 340. The doping concentration of the high pressure well region 320 may be between 1.6×10 ¹⁶ cm ⁻³ and 2.4×10 ¹⁶ cm ⁻³ . As previously mentioned, the high pressure well region 320 may include a well region 322.

In some embodiments, the deep well region 340 may laterally surround the deep well region 360 and may be located above the buried layer 200. More specifically, the deep well region 340 may be in direct contact with the buried layer 200 in the vertical direction. The doping concentration of the deep well region 340 may be between 1.6×10 ¹⁶ cm ^-3 and 2.4×10 ¹⁶ cm ^-3 . As previously mentioned, the deep well region 340 may include a well region 342 and a well region 344. It should be understood that, from the top view, the well region 342 surrounds the well region 344.

In some embodiments, the deep well region 360 may be located at the center circle of the self-lifting diode. The doping concentration of the deep well region 360 may be between 1.6×10 ¹⁶ cm ⁻³ and 2.4×10 ¹⁶ cm ⁻³ . As mentioned previously, the deep well region 360 may include a well region 362 .

Continuing with reference to FIGS. 1 and 2 , a well region 322 may be provided in the high voltage well region 320. In some embodiments, the well region 322 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The well region 322 may be of a first conductivity type (P-type). According to some embodiments of the present invention, the well region 322 may reduce the series resistance of the ground terminal. The doping concentration of the well region 322 may be between 3.6×10 ¹⁶ cm ^-3 and 5.4×10 ¹⁶ cm ^-3 . The thickness of the well region 322 may be between 0.2 μm and 0.6 μm. The lateral dimension of the well region 322 may be between 1 μm and 2 μm. The formation method of the well region 322 may be similar to the formation method of the high pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated here.

1 and 2, a well region 342 and a well region 344 may be provided in the deep well region 340. In some embodiments, the well region 342 and the well region 344 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The well region 342 may be laterally located between the well region 322 and the well region 344. According to some embodiments of the present invention, the well region 342 may be of the second conductivity type (N type), and the well region 344 may be of the first conductivity type (P type). The formation method of the well region 342 and the well region 344 may be similar to the formation method of the high-pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated here.

In some embodiments, the well region 342 may overlap with the buried layer 200. According to some embodiments of the present invention, the function of the well region 342 may be to suppress leakage current in the horizontal direction. The doping concentration of the well region 342 may be between 4.5×10 ¹⁶ cm ^-3 and 6.8×10 ¹⁶ cm ^-3 . The thickness of the well region 342 may be between 0.2 μm and 0.6 μm. The lateral size of the well region 342 may be between 1 μm and 2 μm.

In some embodiments, the well region 344 may partially overlap with the buried layer 200. According to some embodiments of the present invention, the well region 344 may be used to form a P-type semiconductor structure of a diode. The doping concentration of the well region 344 may be between 3.6×10 ¹⁶ cm ^-3 and 5.4×10 ¹⁶ cm ^-3 . The thickness of the well region 344 may be between 0.2 μm and 0.6 μm. The lateral size of the well region 344 may be between 1 μm and 2 μm.

Continuing with reference to FIGS. 1 and 2 , a well region 362 may be provided in the deep well region 360. The well region 362 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The well region 362 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the well region 362 may reduce the series resistance at the cathode end. The doping concentration of the well region 362 may be between 4.5×10 ¹⁶ cm ^-3 and 6.8×10 ¹⁶ cm ^-3 . The thickness of the well region 362 may be between 0.2 μm and 0.6 μm. The lateral dimension of the well region 362 may be between 1 μm and 2 μm. The formation method of the well region 362 may be similar to the formation method of the high pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated here.

1 and 2, a doped region 410 may be disposed in the well region 322. The doped region 410 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 410 may laterally surround the doped region 420 (and the doped region 430). The doped region 410 may be of the first conductivity type (P-type). According to some embodiments of the present invention, since the substrate 100, the high voltage well region 320, the well region 322, and the doped region 410 are all of the first conductivity type (P-type), the subsequently formed metal layer 820 may allow the high voltage device 10 to be electrically grounded from the top or from the bottom. The doping concentration of the doping region 410 may be between 4.0×10 ²⁰ cm ^-3 and 6.0×10 ²⁰ cm ^-3 . The thickness of the doping region 410 may be between 0.09 μm and 0.11 μm. The formation method of the doping region 410 may be similar to the formation method of the high pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated here.

Continuing with reference to FIGS. 1 and 2 , a doped region 420 and a doped region 430 may be disposed in the well region 342. In some embodiments, the doped region 420 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300, and the doped region 430 may extend vertically from the lower surface of the doped region 420 into the epitaxial layer 300. From another perspective, the doped region 420 directly contacts the doped region 430 in the vertical direction, and the bottom surface of the doped region 420 is adjacent to the top surface of the doped region 430. In other words, the doped region 420 may extend from the top surface of the doped region 430 to the top surface of the well region 342. According to some embodiments of the present invention, the doped region 420 and the doped region 430 may both be of the second conductivity type (N type). The formation method of the doped region 420 and the doped region 430 may be similar to the formation method of the high-pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated here.

In some embodiments, the doped region 420 may overlap with the buried layer 200. According to some embodiments of the present invention, the doped region 420 may enhance the suppression of surface leakage current in the horizontal direction. The doping concentration of the doped region 420 may be between 4.0×10 ²⁰ cm ^-3 and 6.0×10 ²⁰ cm ^-3 . The thickness of the doped region 420 may be between 0.09 μm and 0.11 μm.

In some embodiments, the doped region 430 may overlap with the buried layer 200. The doped region 420 and the doped region 430 may surround the doped region 440 laterally. According to some embodiments of the present invention, the doped region 430 may enhance the suppression of surface leakage current in the horizontal direction. The doping concentration of the doped region 430 may be between 2.0×10 ¹⁸ cm ^-3 and 7.0×10 ¹⁸ cm ^-3 . The doping concentration of the doped region 420 is greater than the doping concentration of the doped region 430. The thickness of the doped region 430 may be between 0.09 μm and 0.11 μm.

As mentioned above, in a conventional self-lifting diode structure, leakage current can flow horizontally from the anode end to the well region at the substrate end. In other words, the well region 344 (P-type), the deep well region 340 (N-type), and the high-voltage well region 320 (P-type) of the conventional structure can form a parasitic double carrier (PNP) junction, so that leakage current can flow from the well region 344 to the high-voltage well region 320. According to some embodiments of the present invention, an additional well region 342 (which includes the doping region 420 and the doping region 430) can be provided in the deep well region 340. Since the buried layer 200, the deep well region 340, the well region 342, the doped region 420, and the doped region 430 are all of the second conductivity type (N type), there is no bipolar junction, so that the leakage current cannot pass easily. In other words, the doped structure of the buried layer 200, the deep well region 340, the well region 342, the doped region 420, and the doped region 430 can effectively prevent unwanted leakage current from contacting the high voltage well region 320. During the operation of the high voltage device 10, the doped region 420 and the doped region 430 can be electrically floating. In addition, since the high-voltage well region 320 and the deep well region 340 are separated from each other, they do not form a conductive junction path, thereby further suppressing the horizontal leakage current.

1 and 2, a doped region 440 and a doped region 450 may be disposed in the well region 344. In some embodiments, the doped region 440 and the doped region 450 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. According to some embodiments of the present invention, the doped region 440 may be of a first conductivity type (P type), and the doped region 450 may be of a second conductivity type (N type). The formation method of the doped region 440 and the doped region 450 may be similar to the formation method of the high-pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated herein.

In some embodiments, the doped region 440 may overlap with the buried layer 200. The doped region 440 may laterally surround the doped region 450. According to some embodiments of the present invention, the doped region 440 may serve as a contact point for a P-type semiconductor structure of a diode. The doping concentration of the doped region 440 may be between 4.0×10 ²⁰ cm ^-3 and 6.0×10 ²⁰ cm ^-3 . The thickness of the doped region 440 may be between 0.09 μm and 0.11 μm.

In some embodiments, the doped region 450 may overlap with the buried layer 200. The doped region 450 may laterally surround the doped region 460. The doped region 440 may be laterally located between the doped region 420 and the doped region 450. According to some embodiments of the present invention, the function of the doped region 450 is the same as that of 440, and the details thereof will not be repeated here. The doping concentration of the doped region 450 may be between 4.0×10 ²⁰ cm ^-3 and 6.0×10 ²⁰ cm ^-3 . The thickness of the doped region 450 may be between 0.09 μm and 0.11 μm.

As mentioned previously, the edge of the buried layer 200 extends laterally beyond the edge of the doped region 450 to a spacing D. According to some embodiments of the present invention, the spacing D may be between 10 μm and 15 μm, for example 13 μm. Although the buried layer 200 can effectively limit the leakage current in the vertical direction, excessive lateral dimensions of the buried layer 200 will affect the performance of the breakdown voltage. Therefore, a trade-off must be made between suppressing the leakage current and maintaining an acceptable breakdown voltage. The inventors have found that through optimization, the gap between the edge of the buried layer 200 and the edge of the doped region 450 can be maintained at 13 μm.

Continuing with reference to FIGS. 1 and 2 , a doping region 460 may be disposed in the well region 362. The doping region 460 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doping region 460 may be located at the center circle of the self-lifting diode. The doping region 460 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the doping region 460 may serve as a contact point of the N-type semiconductor structure of the diode. The doping concentration of the doping region 460 may be between 4.0×10 ²⁰ cm ^-3 and 6.0×10 ²⁰ cm ^-3 . The thickness of the doped region 460 may be between 0.09 μm and 0.11 μm. The formation method of the doped region 460 may be similar to the formation method of the high pressure well region 320, the deep well region 340, and the deep well region 360, and the details thereof will not be repeated here.

1 and 2 , an isolation structure 500a, an isolation structure 500b, an isolation structure 500c, an isolation structure 500d, an isolation structure 500e, and an isolation structure 500f may be formed on the epitaxial layer 300. Specifically, since the manufacturing process thereof involves high temperature treatment, the isolation structure 500a, the isolation structure 500b, the isolation structure 500c, the isolation structure 500d, the isolation structure 500e, and the isolation structure 500f are partially embedded in the epitaxial layer 300. According to some embodiments of the present invention, the isolation structure 500a, the isolation structure 500b, the isolation structure 500c, the isolation structure 500d, the isolation structure 500e, and the isolation structure 500f may be drift oxide (DOX) for isolating various conductive components to prevent an electrical short circuit from occurring during operation of the high voltage device 10.

As shown in FIG. 2 , the doped region 410 may be laterally disposed between the isolation structure 500a and the isolation structure 500b. The isolation structure 500b may laterally isolate the doped region 410 from the doped region 420 (and the doped region 430). The doped region 420 (and the doped region 430) may be laterally disposed between the isolation structure 500b and the isolation structure 500c. The isolation structure 500c may laterally isolate the doped region 420 (and the doped region 430) from the doped region 440. The doped region 440 may be laterally located between the isolation structure 500c and the isolation structure 500d. The isolation structure 500d may laterally isolate the doped region 440 from the doped region 450. The doped region 450 may be laterally located between the isolation structure 500d and the isolation structure 500e. The isolation structure 500e may laterally isolate the doped region 450 from the conductive structure 600. The conductive structure 600 may be laterally located between the isolation structure 500e and the isolation structure 500f. The isolation structure 500f can laterally isolate the conductive structure 600 from the doped region 460.

In some embodiments, the isolation structures 500a, 500b, 500c, 500d, 500e, and 500f may be formed by oxidizing silicon oxide (SiO), which may be silicon local oxidation isolation structures formed by thermal oxidation. In other embodiments, the isolation structures 500a, 500b, 500c, 500d, 500e, and 500f may be shallow trench isolation structures formed by etching, oxidation, and deposition processes.

Continuing to refer to FIGS. 1 and 2 , after forming the isolation structures 500a, 500b, 500c, 500d, 500e, and 500f, a conductive structure 600 may be formed on the epitaxial layer 300. In some embodiments, the conductive structure 600 may extend horizontally from the well region 344 toward the deep well region 360, and may extend over a portion of the surface of the isolation structures 500e and 500f. The conductive structure 600 may laterally surround the doped region 460. The conductive structure 600 may be laterally located between the doped region 450 and the doped region 460. During operation of the high voltage device 10, the conductive structure 600 may be electrically grounded. According to some embodiments of the present invention, the conductive structure 600 may reduce the surface electric field between the isolation structure 500e and the isolation structure 500f. The thickness of the conductive structure 600 may be between 300nm and 450nm.

The material of the conductive structure 600 may include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicide (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbide (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxide, and metal. The metal may include cobalt (Co), ruthenium (Ru), aluminum, palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, combinations thereof, or multiple layers thereof. The conductive structure 600 may be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other suitable processes, or combinations thereof.

1 and 2 , an interlayer dielectric layer 700 may be formed on the epitaxial layer 300. In some embodiments, the interlayer dielectric layer 700 may cover the epitaxial layer 300, the isolation structure 500a, the isolation structure 500b, the isolation structure 500c, the isolation structure 500d, the isolation structure 500e, the isolation structure 500f, and the conductive structure 600. In addition to providing mechanical protection and insulation for the components below, the interlayer dielectric layer 700 may also isolate different levels of conductive materials. The material of the interlayer dielectric layer 700 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO _x N _y C _1-xy , where x and y are in the range of 0 to 1), tetraethoxysilane (tetra ethyl ortho silicate, TEOS), undoped silica glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low dielectric constant (low-k) dielectric material, or other suitable dielectric materials.

The thickness of the interlayer dielectric layer 700 may be between 1000 μm and 1200 μm. The interlayer dielectric layer 700 may be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Next, a planarization process (such as chemical mechanical polishing) may be performed on the interlayer dielectric layer 700 to make the interlayer dielectric layer 700 have a flat top surface.

Continuing with reference to FIGS. 1 and 2 , vias 710, 740, 750, 760, and 780 may be formed through the interlayer dielectric layer 700. Vias 710, 740, 750, 760, and 780 may respectively physically contact doped regions 410, 440, 450, 460, and conductive structure 600. In addition, metal layers 820, 840, 860, and 880 may be formed on the interlayer dielectric layer 700. In some embodiments, the metal layer 820 may be electrically coupled to the doped region 410 through the via 710, the metal layer 840 may be electrically coupled to the doped region 440 and the doped region 450 through the via 740 and the via 750, respectively, the metal layer 860 may be electrically coupled to the doped region 460 through the via 760, and the metal layer 880 may be electrically coupled to the conductive structure 600 through the via 780. According to some embodiments of the present invention, the metal layer 820 and the metal layer 880 may serve as an electrical ground of the high voltage device 10, and the metal layer 840 and the metal layer 860 may serve as an anode terminal and a cathode terminal of the high voltage device 10, respectively. Vias 710, 740, 750, 760, 780, metal layer 820, 840, 860, and 880 may be integrally formed and thus include the same material, which may be similar to the material of conductive structure 600, the details of which will not be repeated here.

First, a plurality of openings may be formed in the interlayer dielectric layer 700, corresponding to the doped region 410, the doped region 440, the doped region 450, the doped region 460, and the conductive structure 600. Then, the above-mentioned materials may be blanket deposited on the interlayer dielectric layer 700 through a suitable deposition process. In addition to being formed on the surface of the interlayer dielectric layer 700, the above-mentioned materials are also filled into all the openings to form vias 710, 740, 750, 760, and 780. The deposited film layer may be patterned by a lithography process followed by an etching process to form metal layer 820, metal layer 840, metal layer 860, and metal layer 880. The lithography process may include applying photoresist, soft baking, exposure, post-exposure baking, developing, other similar methods, or a combination thereof. The etching process may include dry etching, wet etching, other similar methods, or a combination thereof. Based on the integrated process, metal layer 820, metal layer 840, metal layer 860, and metal layer 880 may have substantially the same thickness, which may be between 4000Å and 5000Å.

FIG. 3 is a current-voltage curve diagram 20 of a high voltage device according to some embodiments of the present invention. According to some embodiments of the present invention, the current-voltage curve diagram 20 compares the currents of the anode end, the cathode end, and the substrate end during the operation of the high voltage device. Ideally, only the anode end and the cathode end can be measured for current, and the substrate end should not be measured for current. The high voltage device 10 disclosed in the present invention can suppress the current of the substrate end (that is, the unwanted leakage current) to less than 10%, which is the ratio of the substrate current to the anode end current or the cathode end current. For example, at a voltage of 5.5V, the ratio of the substrate current to the anode end current can be about 7%. Since the high voltage device 10 incorporates an additional buried layer and a doping structure, the on-state current can be significantly increased to 1A and the leakage current can be suppressed to less than 10% to meet the standards required by customers.

The high voltage device of the present invention includes a self-lifting diode, which can be a separate configuration or a buried configuration. When the self-lifting diode conducts the desired current through the diode (PN) junction path, the unwanted parasitic bipolar (PNP) junction path may also be turned on to generate leakage current. Through the parasitic bipolar (PNP) junction path, the leakage current can flow from the well region of the anode end to the well region of the substrate end in the horizontal direction, and can also flow from the well region of the anode end to the substrate below in the vertical direction. An additional doping structure can be configured between the anode end and the substrate end to limit the leakage current in the horizontal direction, and a buried layer can be configured directly below the anode end to limit the leakage current in the vertical direction. This allows the self-lifting diode to achieve a 1A conduction current and suppress the leakage current to less than 10%.

The above summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the perspectives of the embodiments of the present invention. Those with ordinary knowledge in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

10: High voltage device 20: Current-voltage curve 100: Substrate 200: Buried layer 300: Epitaxial layer 320: High voltage well area 322: Well area 340: Deep well area 342: Well area 344: Well area 360: Deep well area 362: Well area 410: Doped area 420: Doped area 430: Doped area 440: Doped area 450: Doped area 460: Doped area 500a: Isolation structure 500b: Isolation structure 500c: Isolation structure 500d: Isolation structure 500e: Isolation structure 500f: Isolation structure 600: Conductive structure 700: Interlayer dielectric layer 710: Via 740: Via 750: Via 760: Via 780: Via 820: Metal layer 840: Metal layer 860: Metal layer 880: Metal layer A-A’: Line segment D: Spacing

The following will be described in detail with the accompanying drawings of various aspects of the embodiments of the present invention. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. Figure 1 is a top view of a high-voltage device according to some embodiments of the present invention. Figure 2 is a cross-sectional schematic diagram of a high-voltage device according to some embodiments of the present invention. Figure 3 is a current-voltage curve diagram of a high-voltage device according to some embodiments of the present invention.

10: High voltage device

100: Base

200: buried layer

300: Epitaxial layer

320: High-pressure well area

322: Well area

340: Sham Tseng District

342: Well area

344: Well area

360: Sham Tseng District

362: Well area

410: Mixed area

420: Mixed area

430: Mixed area

440: Mixed area

450: Mixed area

460: Mixed area

500a: Isolation structure

500b: Isolation structure

500c: Isolation structure

500d: Isolation structure

500e: Isolation structure

500f: Isolation structure

600:Conductive structure

700: Interlayer dielectric layer

710: Guide hole

740: Guide hole

750: Guide hole

760: Guide hole

780: Guide hole

820:Metal layer

840:Metal layer

860:Metal layer

880:Metal layer

A-A’: line segment

D: Spacing

Claims (19)

A high voltage device comprises: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer disposed in the substrate; a first deep well region disposed in the epitaxial layer and having the second conductivity type, wherein the first deep well region directly contacts the buried layer; a high voltage well region disposed in the epitaxial layer and having the first conductivity type, wherein the high voltage well region and the first deep well region are laterally separated from each other; a second deep well region disposed in the epitaxial layer and having the second conductivity type, wherein the second deep well region and the first deep well region are laterally separated from each other; A first well region, disposed in the first deep well region and having the second conductivity type; and A first doped region and a second doped region, disposed in the first well region and both having the second conductivity type, wherein the first doped region and the second doped region are in direct contact in a vertical direction. A high voltage device as claimed in claim 1, wherein the bottom surface of the first doped region is adjacent to the top surface of the second doped region, and the doping concentration of the first doped region is greater than the doping concentration of the second doped region. The high voltage device of claim 1 further comprises a second well region disposed in the first deep well region and having the first conductivity type, wherein the first well region and the second well region are laterally separated from each other. A high voltage device as claimed in claim 3, wherein the first well region and the second well region overlap with the buried layer. The high voltage device of claim 3 further comprises: a third doped region disposed in the second well region and having the first conductivity type; and a fourth doped region disposed in the second well region and having the second conductivity type, wherein the third doped region is laterally disposed between the first doped region and the fourth doped region. A high voltage device as claimed in claim 5, wherein an edge of the buried layer laterally extends beyond an edge of the fourth doped region by a distance. A high voltage device as claimed in claim 6, wherein the spacing is between 10 μm and 15 μm. A high-pressure device as claimed in claim 1, wherein the first deep well region is laterally located between the high-pressure well region and the second deep well region. The high voltage device of claim 5 further comprises: a fifth doped region disposed in the high voltage well region and having the first conductivity type; and a sixth doped region disposed in the second deep well region and having the second conductivity type. The high voltage device of claim 9 further comprises a conductive structure disposed on the epitaxial layer and laterally disposed between the fourth doped region and the sixth doped region. A method for forming a high-voltage device, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a first deep well region in the epitaxial layer; forming a high-voltage well region in the epitaxial layer, wherein the high-voltage well region and the first deep well region are laterally separated from each other; forming a second deep well region in the epitaxial layer, wherein the second deep well region and the first deep well region are laterally separated from each other; forming a first well region in the first deep well region; forming a first doped region in the first well region; and forming a second doped region in the first well region, wherein the second doped region extends from the top surface of the first doped region to the top surface of the first well region. A method for forming a high voltage device as claimed in claim 11, wherein the doping concentration of the second doping region is greater than the doping concentration of the first doping region. The method for forming a high voltage device as claimed in claim 11 further includes forming a buried layer in the substrate before forming the epitaxial layer. A method for forming a high voltage device as claimed in claim 13, wherein the first deep well region overlaps with the buried layer. A method for forming a high voltage device as claimed in claim 13, wherein the substrate has a first conductivity type, and the buried layer, the epitaxial layer, the first deep well region, the first well region, the first doped region, and the second doped region have a second conductivity type different from the first conductivity type. The method for forming a high voltage device as claimed in claim 15 further includes forming a second well region in the first deep well region, the second well region having the first conductivity type, wherein the first well region and the second well region are laterally separated from each other. The method for forming a high voltage device as claimed in claim 16 further includes: forming a third doped region in the second well region, the third doped region having the first conductivity type; and forming a fourth doped region in the second well region, the fourth doped region having the second conductivity type, wherein the third doped region is laterally located between the second doped region and the fourth doped region. A method for forming a high voltage device as claimed in claim 17, wherein the edge of the buried layer is laterally extended beyond the edge of the fourth doped region by a distance, wherein the distance is between 10 μm and 15 μm. A method for forming a high voltage device as claimed in claim 15, wherein the high voltage well region has the first conductivity type, wherein the second deep well region has the second conductivity type, and wherein the first deep well region is located between the high voltage well region and the second deep well region.

Images