TWI894845B - Semiconductor device and methods for forming the same - Google Patents

Abstract

A semiconductor device includes a substrate of the first conductivity type, an epitaxial layer on the substrate and having the first conductivity type, several doping portions of the second conductivity type, a trench structure, a well region of the second conductivity type and a gate structure that is formed on the epitaxial layer and over the well region. The epitaxial layer includes the first epitaxial portion on the substrate and the second epitaxial portion on the first epitaxial portion. The doping portions are formed in the first epitaxial portion, and the trench structure is formed in the second epitaxial portion. The trench structure extends from the top surface of the second epitaxial portion into the the second epitaxial portion. The trench structure is in contact with one of the doping portions. The well region extends from the top surface of the second epitaxial portion into the the second epitaxial portion. The first sidewall of the well region is in contact with the trench structure. The second sidewall and the bottome surface of the well region are in contact with the second epitaxial portion.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method for forming the same, and in particular to a semiconductor device and a method for forming the same that can reduce on-resistance and improve device reliability.

The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing minimum device dimensions, allowing more components to be integrated into a given area. For example, vertical-diffused metal oxide semiconductor (VDMOS) utilizes a vertical structural design to reduce the cell pitch and increase functional density. It uses the backside of the chip as the drain, while the source and gate electrodes of multiple transistors are fabricated on the front side of the chip. This shifts the drive current flow from a planar direction to a vertical direction, enabling semiconductor devices to withstand high voltages and is widely used in power switching devices.

As the demands for the electrical performance of semiconductor devices continue to increase, the types and functions of integrated components are also increasing to meet application requirements. However, as the functional density of semiconductor devices continues to increase, the complexity of the components integrated into semiconductor devices and their formation methods also increases, and there are certain electronic characteristics that require trade-offs in performance that need to be considered. For example, the vertical semiconductor devices mentioned above use conductive trenches embedded in the epitaxial layer as field plates. However, as device operating voltages increase, the critical dimensions of conductive trenches, such as trench opening width, trench depth, and trench insulation layer thickness, need to increase to accommodate higher voltage device operation. This, in turn, increases the cell pitch between semiconductor cells and reduces the density of semiconductor device placement. Therefore, while existing semiconductor devices and formation methods are generally adequate and sufficient for their intended purposes, they are not entirely satisfactory in all respects.

Some embodiments of the present disclosure provide a semiconductor device comprising a substrate having a first conductivity type and an epitaxial layer formed on the substrate and having the first conductivity type. The epitaxial layer comprises a first epitaxial portion formed on the substrate and a second epitaxial portion formed on the first epitaxial portion. The semiconductor device further comprises a plurality of doping portions having a second conductivity type disposed in the first epitaxial portion, and a trench structure disposed in the second epitaxial portion, wherein the trench structure extends downward from the top surface of the second epitaxial portion. The trench structure comprises a conductive portion and an insulating layer covering the sidewalls and bottom of the conductive portion, and the insulating layer contacts one of the doping portions. The semiconductor device further comprises a well region having the second conductivity type, which extends downward from the top surface of the second epitaxial portion into the second epitaxial portion. A first sidewall of the well region contacts the trench structure, and a second sidewall of the well region, opposite the first sidewall and located on the bottom surface of the well region, contacts the second epitaxial portion. The semiconductor device further includes a gate structure formed on the top surface of the second epitaxial portion and corresponding to the well region.

Some embodiments disclosed herein provide a method for forming a semiconductor device, comprising providing a substrate having a first conductivity type; forming a first epitaxial portion having the first conductivity type on the substrate; forming a plurality of doped portions in the first epitaxial portion, wherein the doped portions have a second conductivity type and extend downward from a top surface of the first epitaxial portion into the first epitaxial portion; forming a second epitaxial portion having the first conductivity type on the first epitaxial portion, wherein the first epitaxial portion and the second epitaxial portion form an epitaxial layer; and forming a trench structure extending downward from a top surface of the second epitaxial portion into the first epitaxial portion. A trench structure is formed extending from the top surface of the second epitaxial portion, and the trench structure contacts a corresponding one of the doped portions. The trench structure includes a conductive portion and an insulating layer covering the sidewalls and bottom of the conductive portion, and the insulating layer directly contacts the corresponding doped portion. A well region of the second conductivity type is formed extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, wherein a first sidewall of the well region contacts the trench structure, and a second sidewall of the well region opposite the first sidewall contacts the second epitaxial portion. A gate structure is formed on the top surface of the second epitaxial portion, and the gate structure corresponds to the well region below.

10,20:Semiconductor devices

100,200: Base

102,202: Epitaxial layer

1021: First epitaxial section

1022: Second epitaxial section

102t: Groove

104,304,404A,404B,404C,504: Mixed

104h: Hole

105,205: Groove structure

1051,2051:Insulating layer

1052,2052: Conductive Department

100a, 1021a, 1022a, 104a, 106a: Top surface

106b, 1052b: Bottom surface

106,206: Well Area

106s1: First side wall

106s2: Second side wall

_RD : Drifting Zone

108,208: First mixed section

110,210: Gate structure

111: Gate dielectric layer

112: Gate electrode

114: Interlayer dielectric layer

115,215: Second mixed section

116,216: Contact plug

1161: Contact barrier

1162: Contact with conductive layer

T1: First thickness

T2: Second thickness

dp1: First depth

dp2: Second depth

D1: First Direction

D2: Second Direction

D3: Third direction

Figures 1A-1G are schematic cross-sectional views of a semiconductor device at various intermediate fabrication stages according to some embodiments of the present disclosure.

Figure 2 is a schematic cross-sectional view of a conventional semiconductor device.

Figure 3 is a schematic top view of a doping and trench structure of a semiconductor device according to some embodiments of the present disclosure.

Figures 4A-4C are schematic top views of doping and trench structures of a semiconductor device according to some embodiments of the present disclosure.

Figure 5 is a schematic top view of a doping and trench structure of a semiconductor device according to some embodiments of the present disclosure.

The following disclosure provides numerous embodiments or examples for implementing various components of the provided semiconductor devices. Specific examples of various components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, a description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, as well as embodiments in which additional components are formed between the first and second components so that they are not in direct contact. Furthermore, the embodiments of the present invention may repeat reference numbers and/or letters in different examples. This repetition is for the sake of brevity and clarity and is not intended to indicate a relationship between the different embodiments discussed.

Furthermore, spatially relative terms such as "under," "beneath," "below," "below," "above," "upper," and similar terms may be used in the following description to simplify the description of the relationship between an element or component and other elements or components as shown in the figures. Such spatially relative terms encompass not only the orientation depicted in the figures but also different orientations of the semiconductor device during use or operation. The semiconductor device may be positioned in other orientations, and the spatially relative descriptions used herein should be interpreted accordingly.

The following describes some variations of the embodiments. Similar reference numerals are used to designate similar elements throughout the various figures and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, or after the method, and that some described steps may be replaced or eliminated for other embodiments of the method.

Embodiments of the present disclosure provide semiconductor devices and methods for forming the same. These devices can be fabricated using low-voltage device designs to produce semiconductor devices suitable for high-voltage operation. Furthermore, the semiconductor devices of these embodiments can effectively reduce on-resistance and improve device reliability. These embodiments are applicable to metal-oxide-semiconductor (MOS) devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In some of the following embodiments, MOS field-effect transistors (MOSFETs) with planar gates and conductive trench structures are used as examples of semiconductor devices.

Figures 1A-1G are schematic cross-sectional views of a semiconductor device at various intermediate fabrication stages according to some embodiments of the present disclosure.

Referring to FIG. 1A , according to some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, substrate 100 may be a bulk semiconductor substrate, such as a semiconductor wafer. For example, substrate 100 is a silicon wafer. In some embodiments, substrate 100 may be made of silicon or other semiconductor materials, or may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, substrate 100 may include a compound semiconductor, such as silicon carbide or gallium nitride. In some embodiments, substrate 100 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, or other suitable substrates. In some embodiments, substrate 100 may be composed of multiple layers of material, such as silicon/silicon germanium or silicon/silicon carbide.

In this example, substrate 100 is, for example, a silicon wafer doped with a dopant of a first conductivity type. In a vertical conductive trench MOSFET application, substrate 100 of the first conductivity type can serve as the drain region of the semiconductor device. Furthermore, in this example, the first conductivity type is n-type, but the present disclosure is not limited thereto. In other examples, the first conductivity type can also be p-type.

In some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on a substrate 100. During the epitaxial growth process, for example, epitaxial layer 102 grows in a first direction D1 (e.g., the Z direction). According to embodiments of the present disclosure, epitaxial layer 102 is grown in a two-stage process. After forming a first epitaxial portion 1021 below, a plurality of spaced-apart doping portions 104 are formed in the first epitaxial portion 1021. A second epitaxial portion 1022 is then formed above the first epitaxial portion 1021. According to embodiments of the present disclosure, these doping portions 104 have a different conductivity type than the epitaxial layer 102.

Referring to FIG. 1A , an epitaxial growth process is performed on the top surface 100a of the substrate 100 to form a first epitaxial portion 1021 having a first conductivity type. Furthermore, a plurality of doping portions 104 having a second conductivity type are formed in the first epitaxial portion 1021. These doping portions 104 extend downward from the top surface 1021a of the first epitaxial portion 1021 into the first epitaxial portion 1021. In some embodiments, these doping portions 104 are spaced apart in a second direction D2 (e.g., the X direction). Furthermore, in some embodiments, these doping portions 104 have substantially the same depth within the first epitaxial portion 1021.

Furthermore, the substrate 100 and the first epitaxial portion 1021 have the same conductivity type (e.g., the first conductivity type). In this example, the substrate 100 and the first epitaxial portion 1021 are n-type, while the doping portion 104 has an opposite conductivity type to the first epitaxial portion 1021, e.g., p-type. In some embodiments, the doping concentration of the first epitaxial portion 1021 is less than the doping concentration of the substrate 100. The doping concentration of the substrate 100 is, for example, but not limited to, in the range of approximately 1E18 atoms/ ^cm³ to approximately 1E21 atoms/ ^cm³ . The doping concentration of the first epitaxial portion 1021 is, for example, but not limited to, in the range of approximately 1E14 atoms/ ^cm³ to approximately 1E16 atoms/ ^cm³ .

In some embodiments, the doped portion 104 includes a dopant having a second conductivity type (e.g., p-type), and the doping concentration of the doped portion 104 is lower than the doping concentration of the substrate 100. In some embodiments, the doping concentration of the doped portion 104 is substantially equal to the doping concentration of the first epitaxial portion 1021. The doping concentration of the doped portion 104 is, for example, but not limited to, in a range of approximately 1E14 atoms/cm ³ to approximately 1E16 atoms/cm ³ .

Furthermore, in some embodiments, the doped portion 104 and the first epitaxial portion 1021 comprise the same semiconductor material. For example, the doped portion 104 and the first epitaxial portion 1021 are both made of a silicon-containing material. In some embodiments, the doped portion 104 is epitaxial silicon having a second conductivity type (e.g., p-type).

The doped portion 104 of the above-described embodiment can be formed using various fabrication methods. For example, the doped portion 104 can be formed by an implantation process to form a corresponding doped block, or by etching a hole 104h in the first epitaxial portion 1021 and filling the hole 104h with a material having the second conductivity type. Two applicable methods for forming the doped portion 104 are briefly described below, but this disclosure is not particularly limited to these methods.

In some embodiments, the doping portion 104 described above can be formed through a deposition process, a lithographic patterning process, an etching process, and an implantation process. In one embodiment, a hard mask material layer (not shown) (e.g., an oxide hard mask material layer) can be first deposited above the top surface 1021a of the first epitaxial portion 1021. A patterned photoresist (not shown) can then be formed on the hard mask material layer. The hard mask material layer is then etched based on the patterned photoresist to form a patterned hard mask (e.g., an oxide hard mask). The patterned hard mask has multiple openings corresponding to the locations of the doping portion 104 to be formed. The patterned photoresist is then removed, leaving the patterned hard mask. An ion implantation process is then performed on the first epitaxial portion 1021 according to the pattern of the patterned hard mask (e.g., the aforementioned openings) to form a plurality of doped regions within the first epitaxial portion 1021. These doped regions extend downward from the top surface 1021a of the first epitaxial portion 1021 into the first epitaxial portion 1021 and contain dopants of the second conductivity type. The patterned hard mask is then removed. A thermal drive-in process, such as a high-temperature annealing process, is then selectively performed to diffuse and shape these doped regions, thereby forming the doped portion 104.

In some other embodiments, the location of the doping portion 104 can be defined by a suitable lithographic patterning process, and the doping portion 104 can be formed by suitable deposition and planarization processes. For example, a mask (not shown) is formed above the first epitaxial portion 1021, and the mask has multiple openings to expose the top surface 1021a of the first epitaxial portion 1021. In some embodiments, the mask is a patterned photoresist formed of a photoresist material. In some other embodiments, the mask material can be a hard mask (HM) composed of an oxide layer and a nitride layer. Subsequently, portions of the first epitaxial portion 1021 can be removed through the mask openings, for example by performing one or more etching processes to form a plurality of holes 104h in the first epitaxial portion 1021. The positions of these holes 104h correspond to the positions of the doping portions 104 shown in FIG. 1A . The depth of these holes 104h in the first epitaxial portion 1021 (e.g., along the first direction D1) is equal to the depth of the subsequently formed doping portions 104 in the first epitaxial portion 1021. The etching processes described above can be, for example, dry etching, wet etching, plasma etching, reactive ion etching, other suitable processes, or a combination thereof. After forming the holes, the mask can be removed through an ashing process, a wet etching process (such as acid etching), or other acceptable processes. Subsequently, the holes 104h are filled with a material having a second conductivity type (such as p-type) to form the doped portion 104.

In some examples, a p-type material can be deposited over the first epitaxial portion 1021 through a deposition process, with the p-type material filling the hole 104h. A planarization process is then performed to remove excess p-type material above the top surface 1021a of the first epitaxial portion 1021, exposing the top surface 1021a of the first epitaxial portion 1021. The p-type material in the hole 104h forms the doped portion 104. The deposition process can be, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof. The planarization process may be, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the aforementioned processes.

Furthermore, according to some embodiments, after forming the doped portion 104, the top surface 104a of the doped portion 104 is substantially coplanar with the top surface 1021a of the first epitaxial portion 1021, as shown in FIG. 1A.

Next, referring to FIG. 1B , according to some embodiments, epitaxial growth continues on the top surface 1021a of the first epitaxial portion 1021 in the first direction D1 (e.g., the Z direction) to form a second epitaxial portion 1022. The second epitaxial portion 1022 covers the doped portion 104. The second epitaxial portion 1022 also has the first conductivity type, such as n-type. In this example, the first epitaxial portion 1021 and the second epitaxial portion 1022 together constitute an epitaxial layer 102. After the second epitaxial portion 1022 is formed, the doped portion 104 is embedded in the epitaxial layer 102. As shown in FIG. 1B , the doped portion 104 is embedded in the lower portion of the epitaxial layer 102.

The epitaxial growth process described above can be performed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable processes, or a combination thereof, to form the first epitaxial portion 1021 and the second epitaxial portion 1022, respectively. In applications such as vertical trench-gate metal oxide semiconductor field-effect transistors (MOSFETs), after transistor fabrication, the epitaxial layer 102 having the first conductivity type (e.g., n-type) can serve as the drift region of the semiconductor device.

Figure 1B also shows the thicknesses of the deposited first epitaxial portion 1021 and second epitaxial portion 1022, as well as the depth of the doping portion 104 within the first epitaxial portion 1021. As shown in the figure, the first epitaxial portion 1021 is deposited to a first thickness T1 along a first direction D1, the second epitaxial portion 1022 is deposited to a second thickness T2 along the first direction D1, and the doping portion 104 has a depth dp1 (hereinafter referred to as the first depth dp1) within the second epitaxial portion 1022 along the first direction D1. The first depth dp1 of the doping portion 104 is less than the first thickness T1 of the first epitaxial portion 1021. The first thickness T1 of the first epitaxial portion 1021 can be greater than, equal to, or less than the second thickness T2 of the second epitaxial portion 1022, depending on the electrical requirements of the semiconductor cell in the actual application.

Then, according to some embodiments, a trench structure 105 is formed in the second epitaxial portion 1022, as shown in Figures 1C and 1D.

Referring to FIG. 1C , a portion of the second epitaxial portion 1022 is removed to form a plurality of trenches 102t. These trenches 102t are, for example, spaced apart in the second direction D2 and may extend along the third direction D3. Furthermore, in some embodiments, these trenches 102t correspond to the underlying doping portion 104 and may expose at least a portion of the top surface 104a of the doping portion 104. Furthermore, in some embodiments, the depth of these trenches 102t in the second epitaxial portion 1022 (e.g., along the first direction D1) is equal to the depth of the subsequently formed trench structure 105 in the second epitaxial portion 1022 (e.g., along the first direction D1).

According to some embodiments, the trench 102t described above can be formed through a deposition process, a lithography patterning process, and an etching process. For example, a hard mask material layer (not shown) is formed above the second epitaxial portion 1022, and a patterned photoresist layer (not shown) is formed on this hard mask material layer. This hard mask material layer can be a single layer or a multi-layer material layer. This patterned photoresist layer has an opening pattern corresponding to the position of the trench 102t. Then, an etching process is sequentially performed on the hard mask material layer and the second epitaxial portion 1022 through this patterned photoresist layer to remove a portion of the second epitaxial portion 1022, thereby forming the trench 102t described above. The etching process may be, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof. After forming the trench 102t, the patterned photoresist layer is removed. A cleaning process is then performed on the structure to remove any residue. The hard mask material layer may be removed or retained. To simplify the diagram, the hard mask material layer is shown as removed.

Next, referring to FIG. 1D , according to some embodiments, a plurality of trench structures 105 are formed in the trench 102t . Each trench structure 105 contacts a doped portion 104 below. Each trench structure 105 , for example, includes an insulating layer 1051 and a conductive portion 1052 . The insulating layer 1051 covers the sidewalls and bottom of the conductive portion 1052 .

Furthermore, as shown in FIG1D , the trench structures 105 in the second epitaxial portion 1022 may be spaced apart from each other in the second direction D2 and extend along the third direction D3. The insulating layer 1051 of each trench structure 105 is in direct contact (e.g., physically in contact with the doping portion 104 ). Therefore, according to this embodiment, the conductive portion 1052 of the trench structure 105 is electrically isolated from the corresponding doping portion 104 by the insulating layer 1051 of the trench structure 105 .

In some embodiments, the insulating layer 1051 may be silicon oxide, or other suitable semiconductor oxide materials, or a combination of the foregoing materials. In some examples, an oxidation process may be used to conformably form an insulating material on the sidewalls and bottom surface of the trench 102t and on the top surface 1022a of the second epitaxial portion 1022. This insulating material may also be referred to as a shield insulating material. The above-mentioned oxidation process is, for example, thermal oxidation, radical oxidation, or other suitable processes. Furthermore, in some embodiments, a thermal process may be selectively performed on the insulating material to increase the density of the insulating material. In some embodiments, the aforementioned thermal process may be a rapid thermal annealing (RTA) process.

In some other embodiments, an insulating material may be deposited on the sidewalls and bottom surface of the trench 102t and on the top surface 1022a of the second epitaxial portion 1022 by a deposition process. The deposition process may be, for example, a conformal deposition process, and may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable deposition processes, or a combination thereof.

Then, according to some embodiments, a conductive material (not shown) may be deposited over the insulating material through a deposition process, filling the space in the trench 102t outside the insulating material. The conductive material may optionally be subjected to a thermal process, such as an annealing process. In some embodiments, the conductive material may be a single layer or a multi-layer structure, and may include, for example, polysilicon, other suitable materials, or a combination thereof. In some examples, the conductive material deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof.

Next, a portion of the insulating material and a portion of the conductive material are removed to form the trench structure 105 shown in FIG. 1D . In some examples, the step of removing a portion of the insulating material and a portion of the conductive material may (but is not limited to) include removing excess conductive material and excess insulating material above the top surface 1022a of the second epitaxial portion 1022 using a planarization process to expose the top surface 1022a of the second epitaxial portion 1022. The planarization process may be, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination thereof.

After the aforementioned removal step, the remaining portion of the insulating material becomes the insulating layer 1051, and the remaining portion of the conductive material becomes the conductive portion 1052. The conductive portion 1052 is separated from the second epitaxial portion 1022 by the insulating layer 1051. In some examples, after the planarization process, the conductive portion 1052 is located on the insulating layer 1051, and the top surface of the conductive portion 1052 and the top surface of the insulating layer 1051 are substantially coplanar with the top surface 1022a of the second epitaxial portion 1022.

Furthermore, in some embodiments, the trench structure 105 formed in the second epitaxial portion 1022 has a depth dp2 along the first direction D1 (hereinafter referred to as the second depth dp2 to distinguish it from the first depth dp1 of the doped portion 104). The second depth dp2 of the trench structure 105 is adjusted and determined accordingly with the first depth dp1 of the underlying doped portion 104 to meet the electrical requirements of the semiconductor cell being used.

Furthermore, according to some embodiments, the critical width (maximum width) of the bottom of the trench structure 105 is smaller than the critical width (maximum width) of the top surface 104a of the doping portion 104 that contacts the trench structure 105. As shown in FIG. 1D , the width of the bottom surface of the trench structure 105 in the second direction D2 can be smaller than the width of the top surface 104a of the doping portion 104 in the second direction D2, but the present disclosure is not limited to this.

In some embodiments, when the semiconductor device is operated at high voltage, carriers flowing to the lower first epitaxial portion 1021 can be depleted by the superjunctions between the different conductivity doping portions 104 and the first epitaxial portion 1021. Therefore, a device design suitable for lower voltage operation can be provided in the upper second epitaxial portion 1022, including a smaller cell pitch and a narrower trench structure 105. Therefore, according to some embodiments, the upper trench structure 105 and the lower doping portion 104 contact and interact to achieve a semiconductor device design suitable for high voltage operation.

Next, referring to FIG. 1E , according to some embodiments, a well region 106 is formed in the second epitaxial portion 1022 . This well region 106 has a different conductivity type than the second epitaxial portion 1022 , such as a second conductivity type. In this example, the well region 106 is p-type, also referred to as a p-body region. Furthermore, the depth of the trench structure 105 in the second epitaxial portion 1022 (e.g., depth dp2 along the first direction D1) is greater than the depth of the well region 106 in the second epitaxial portion 1022 (e.g., along the first direction D1). More specifically, the bottom surface of the trench structure 105 is closer to the substrate 100 than the bottom surface of the well region 106. In some embodiments, the doping concentration of the well region 106 is in a range from approximately 1E16 atoms/cm ³ to approximately 1E18 atoms/cm ³ . According to some embodiments, the surface of the well region 106 can serve as a channel region of a semiconductor device.

In some embodiments, the bottom surface 1052b of the conductive portion 1052 of the trench structure 105 is lower than the bottom surface 106b of the well region 106, and the bottom surface 1052b of the conductive portion 1052 is higher than the top surface 1021a of the first epitaxial portion.

Note that, although this example illustrates a symmetric configuration of components in each semiconductor cell (e.g., a transistor), where, for example, related components (including the well region 106, the first heavily doped portion 108, the gate structure 100, the contact plug 116, and other components) are symmetrically formed on opposite sides of a trench structure 105, the present disclosure is not limited thereto. According to other embodiments, the design proposed in the above embodiment, including providing a doping portion 104 in the lower first epitaxial portion 1021 to form a superjunction and a trench structure 105 in the upper second epitaxial portion 1022, can also be applied to semiconductor cells having asymmetric components. The following describes the relevant components formed on one side of the trench structure 105 for simplicity.

According to some embodiments, one side of the formed well region 106 contacts the trench structure 105, while the other side and bottom of the well region 106 are covered by the second epitaxial portion 1022 of the epitaxial layer 102. For example, the first sidewall 106s1 of the well region 106 contacts one side of the trench structure 105. In other words, after the well region 106 is formed, one side of the trench structure 105 extends along the first sidewall 106s1 of the well region 106 into the second epitaxial portion 1022, as shown in FIG. 1E .

According to some embodiments, doping can be performed from the top surface 1022a of the second epitaxial portion 1022 through a deposition process, a lithography patterning process, an etching process, and an implantation process to form well regions 106 in the second epitaxial portion 1022, as shown in FIG. 1E . Note that although the cross-sectional view of FIG. 1E cannot be seen, each well region 106 is a doped region extending in the first direction D1, the second direction D2, and the third direction D3.

Furthermore, according to some embodiments, the epitaxial portion outside and below the well region 106 is a drift region _RD . This drift region _RD has a first conductivity type (e.g., n-type) and contacts the second sidewall 106s2 and bottom surface 106b of the well region 106, as shown in FIG. 1E . In this example, the well region 106 and the drift region _RD directly contact the trench structure 105. The well region 106 and the drift region _RD are separated from the conductive portion 1052 by an insulating layer 1051 of the trench structure 105. In the manufacturing process of some embodiments, when looking down from above the second epitaxial portion 1022, the mask defining the well region 106 (extending in the second direction D2 and the third direction D3, not shown) and the mask defining the trench structure 105 (extending in the second direction D2 and the third direction D3, not shown) partially overlap in the second direction D2, so that the well region 106 subsequently manufactured contacts one side of the trench structure 105.

Next, according to some embodiments, doping is performed in the well region 106, for example, from the top surface 106a of the well region 106 (i.e., the top surface 1022a of the second epitaxial portion 1022), to form first heavily doped portions 108 in the well region 106. In some embodiments, one side of these first heavily doped portions 108 contacts the adjacent trench structure 105. For example, the first heavily doped portions 108 directly contact the insulating layer 1051 of the trench structure 105.

In some embodiments, the first heavily doped portion 108 has the same conductivity type as the epitaxial layer 102, such as the first conductivity type. In this example, the first heavily doped portion 108 is n-type. In some embodiments, the doping concentration of the first heavily doped portion 108 is greater than the doping concentration of the second epitaxial portion 1022. In some embodiments, the doping concentration of the first heavily doped portion 108 is in a range from approximately 1E18 atoms/cm ³ to approximately 1E21 atoms/cm ³ .

According to some embodiments, a deposition process, a lithography patterning process, an etching process, and an implantation process may be performed to form a first heavily doped portion 108 in the well region 106 by doping from the top surface 1022a of the second epitaxial portion 1022. In a non-limiting example, an oxide hard mask material layer (not shown) may be deposited over the top surface 1022a of the second epitaxial portion 1022. Then, a patterned photoresist (not shown) may be formed on the oxide hard mask material layer corresponding to the location of the first heavily doped portion 108. The oxide hard mask material layer may then be etched based on the patterned photoresist to form an oxide hard mask. The patterned photoresist is then removed, and the second epitaxial portion 1022 is doped based on the formed oxide hard mask to form a first heavily doped portion 108 in the well region 106. The oxide hard mask is then removed.

1F , according to some embodiments, a planar gate structure 110 is formed on the top surface 1022a of the second epitaxial portion 1022. Each gate structure 110 corresponds to the underlying well region 106. Specifically, in some embodiments, each gate structure 110 is disposed across the corresponding well region 106, the first heavily doped portion 108 in the well region 106, and a portion of the drift region _RD .

In some embodiments, each gate structure 110 includes a gate dielectric layer 111 and a gate electrode 112 located above the gate dielectric layer 111. The gate dielectric layer 111 may be silicon oxide or other suitable dielectric materials. The gate electrode 112 may be polysilicon or other suitable conductive materials. A dielectric material layer (not shown) may be formed on the second epitaxial portion 1022 by a deposition process (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process) or a thermal oxidation process. Next, a conductive material (not shown) is deposited on the dielectric material layer. This deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable processes. Subsequently, lithography and etching processes can be used to pattern the dielectric material layer and the conductive material to form the gate dielectric layer 111 and gate electrode 112 of the gate structure 110.

According to some embodiments, as shown in FIG. 1F , after forming the gate structure 110, an interlayered dielectric (ILD) layer 114 is formed on the epitaxial layer 102. More specifically, the ILD layer 114 is formed on the top surface 1022a of the second epitaxial portion 1022 and covers the gate structure 110, the first heavily doped portion 108, and the trench structure 105.

In some embodiments, the interlayer dielectric layer 114 can be silicon oxide, or other suitable low-k dielectric materials, or a combination of the foregoing materials. In some embodiments, the material of the interlayer dielectric layer 114 is different from the material of the insulating layer 1051 of the trench structure 105. In some other embodiments, the interlayer dielectric layer 114 and the insulating layer 1051 of the trench structure 105 include the same material. Furthermore, the interlayer dielectric layer 114 can be deposited on top of the epitaxial layer 102 by a deposition process. In some embodiments, the above-mentioned deposition process can be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing.

Next, referring to FIG. 1G , according to some embodiments, a contact plug 116 is formed in the interlayer dielectric layer 114 , and the contact plug 116 is electrically connected to the source region of the semiconductor device. The following is a process for forming the contact plug 116 .

In some embodiments, a portion of the interlayer dielectric layer 114, a portion of the first heavily doped portion 108, and a portion of the well region 106 are removed to form a contact hole (not shown) for subsequently forming a contact plug 116. The contact hole is located between the gate structure 110 and the trench structure 105, and the bottom of the contact hole, for example, exposes the well region 106.

According to some embodiments, the contact holes can be formed by a lithographic patterning process and an etching process. For example, after depositing an interlayer dielectric layer 114 above the second epitaxial portion 1022, one or more etching processes are performed to remove a portion of the interlayer dielectric layer 114, a portion of the first heavily doped portion 108, and a portion of the well region 106 to form the contact holes. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or a combination of the aforementioned processes. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

According to some embodiments of the semiconductor device disclosed herein, after forming the contact hole, the remaining portion of the first heavily doped portion 108 can serve as a source region of the semiconductor device in one embodiment.

According to some embodiments, after forming the contact holes, an ion implantation process may be performed through the bottom of the contact holes to form second heavily doped portions 115 in the well region 106. In some embodiments, these second heavily doped portions 115 have the same conductivity type as the well region 106, such as the second conductivity type. In this example, the second heavily doped portions 115 are p-type.

In some embodiments, the doping concentration of the second heavily doped portion 115 is greater than the doping concentration of the well region 106. Furthermore, in some embodiments, the doping concentration of the doping portion 104 disposed in the first epitaxial portion 1021 is less than the doping concentration of the second heavily doped portion 115. In some embodiments, the doping concentration of the second heavily doped portion 115 is in a range from approximately 1E18 atoms/cm ³ to approximately 1E21 atoms/cm ³ .

Furthermore, in some embodiments, the second heavily doped portions 115 are located around the bottom of the contact hole and are adjacent to the trench structure 105 and the first heavily doped portion 108. For example, the second heavily doped portions 115 are located below the first heavily doped portion 108. In this example, one side of these second heavily doped portions 115 physically contacts the adjacent trench structure 105, for example, the second heavily doped portions 115 directly contact the insulating layer 1051 of the trench structure 105. According to some embodiments of the semiconductor device, the formation of the second heavily doped portion 115 can form a good ohmic contact between the subsequently formed contact plug 116 and the well region 106.

Then, contact plugs 116 are formed in the contact holes. According to some embodiments, each contact plug 116 is located between the gate structure 110 and the trench structure 105 along the second direction D2. According to some embodiments, the contact plugs 116 are electrically connected to the well region 106 and to the first heavily doped portion 108. In this example, the bottom of the contact plug 116 also contacts the second heavily doped portion 115, thereby providing a better electrical connection between the contact plug 116 and the well region 106 via the second heavily doped portion 115. In the embodiment where the first heavily doped portion 108 serves as the source region of the semiconductor device 10, the contact plug 116 may also be referred to as a source contact.

It is noteworthy that the contact plug 116 shown in FIG. 1G directly contacts the adjacent trench structure 105. That is, no epitaxial portion of the drift region _RD exists between the contact plug 116 and the adjacent trench structure 105 (along the second direction D2). However, the present disclosure is not limited to this. In some other embodiments, the contact plug 116 may be separated from the adjacent trench structure 105 by a distance (not shown). That is, a portion of the first heavily doped portion 108 may exist between the contact plug 116 and the trench structure 105 (along the second direction D2).

In some embodiments, contact plug 116 includes a contact barrier layer 1161 and a contact conductive layer 1162. Contact barrier layer 1161 is formed on the sidewalls and bottom of the contact hole, serving as a barrier liner, while contact conductive layer 1162 fills the remaining space in the contact hole outside of contact barrier layer 1161. In this example, as shown in FIG. 1G , the top surface of contact plug 116 (including the top surface of contact barrier layer 1161 and the top surface of contact conductive layer 1162) is substantially coplanar with the top surface of interlayer dielectric layer 114.

In some examples, a barrier material (not shown) can be formed on the interlayer dielectric layer 114 through a deposition process, and the barrier material is isotropically deposited in the contact hole. A conductive material (not shown) is then deposited over the barrier material layer, filling the remaining space in the contact hole. Excess conductive material and barrier material over the interlayer dielectric layer 114 are then removed, for example, by etching or other suitable methods, to form a contact barrier layer 1161 and a contact conductive layer 1162 in the contact hole.

In some embodiments, the material of the contact barrier layer 1161 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), ruthenium (Ru), _aluminum oxide ( _Al2O3 ), magnesium oxide (MgO), aluminum nitride ( _AlN ), tantalum pentoxide ( _Ta2O5 ), silicon dioxide ( _SiO2 ), hexagonal oxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), magnesium fluoride ( _MgF2 ), calcium fluoride ( _CaF2 ), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer 1161 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination thereof.

In some embodiments, the contact conductive layer 1162 may be a single layer or a multi-layer structure, and its conductive material may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), and titanium nitride (TiN). nitride; TiAlN), other suitable metals, or combinations thereof. Furthermore, in some embodiments, the conductive material can be formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or a combination thereof.

After forming the contact plug 116, subsequent fabrication processes for other components are performed. According to some embodiments, a metal layer (not shown) is formed over the interlayer dielectric layer 114 and the contact plug 116. The metal layer covers the contact plug 116 and is physically and electrically connected to the contact plug 116. Thus, the metal layer is electrically connected to the first heavily doped region 108, the second heavily doped region 115, and the well region 106 through the contact plug 116.

In some embodiments, the metal layer may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations thereof. In some embodiments, the metal layer is made of the same material as the contact plug 116. In other embodiments, the metal layer is made of a different material than the contact plug 116. According to some embodiments, the metal layer may be formed on the contact plug 116 by a deposition process. In some embodiments, the deposition process may be a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or combinations thereof. According to some embodiments, this metal layer can serve as the top metal of the semiconductor device 10, electrically connecting to the first heavily doped portion 108, which serves as the source region. Therefore, it can also be referred to as the source metal layer. After forming the metal layer, the manufacturing process of the semiconductor device 10 is complete.

According to embodiments, the doped portion 104 reaches a certain depth within the first epitaxial portion 1021. For example, in some embodiments, the ratio of the first depth dp1 of the doped portion 104 within the first epitaxial portion 1021 to the first thickness T1 of the first epitaxial portion 1021 is in a range of approximately 0.4 to approximately 0.9. In some embodiments, the ratio of the first depth dp1 to the first thickness T1 is in a range of approximately 0.5 to approximately 0.8, or in other suitable ranges.

Furthermore, according to embodiments, the depth of the dopant 104 also reaches a ratio with respect to the depth of the trench structure 105 above it. For example, in some embodiments, the ratio of the first depth dp1 of the dopant 104 in the first epitaxial portion 1021 to the second depth dp2 of the trench structure 105 in the second epitaxial portion 1022 is in the range of approximately 0.4 to 2.0, or in the range of approximately 0.5 to 1.5, or in the range of approximately 0.7 to 1.3, or in the range of approximately 0.8 to 1.2, or in other suitable ranges.

Furthermore, the first depth dp1 of the doped portion 104 of the embodiment can be greater than, equal to, or less than the second depth dp2 of the trench structure 105, depending on the electrical requirements of the semiconductor cell in the actual application. If the first depth dp1 is greater than the second depth dp2, the depth of the depletion region between the first epitaxial portion 1021 below and the doped portion 104 increases. While this makes it less likely that the doped portion 104 will form, it can reduce the dimensions of the trench structure 105 in the second epitaxial portion 1022 above (e.g., the width and depth of the trench structure 105 and the thickness of the insulating layer 1051) and shorten the cell pitch between adjacent semiconductor cells. If the second depth dp2 is greater than the first depth dp1, the depth of the depletion region between the first epitaxial portion 1021 and the doped portion 104 is reduced, but this is beneficial to the formation of the doped portion 104.

The semiconductor devices proposed according to some of the aforementioned embodiments have numerous advantages. In particular, these embodiments enable the use of a device design suitable for low-voltage operation, including a smaller cell pitch and a narrower trench structure 105, in conjunction with the doping portion 104 beneath the trench structure 105, to achieve a semiconductor device suitable for high-voltage operation. Furthermore, the semiconductor devices proposed in these embodiments can effectively reduce on-resistance. Furthermore, according to some embodiments, the dopant 104 located below the trench structure 105 is closer to the substrate 100 (drain region). When a high voltage is applied to the substrate 100, the dopant 104 can reduce the electric field strength at the bottom of the insulating layer 1051 in the trench structure 105, thereby preventing the formation of a leakage path between the bottom of the insulating layer 1051 and the substrate 100, thereby improving the reliability of the semiconductor device.

Furthermore, in semiconductor devices according to some embodiments of the present disclosure, the conductive portion 1052 of the trench structure 105 can be electrically connected to the gate structure 110. For example, the conductive portion 1052 can be coupled to the gate electrode 112 via other interconnects (not shown) within the semiconductor device. Alternatively, pins can be provided on the conductive portion 1052, and then electrically connected to the gate structure 110 via wire bonding during the packaging process. According to some embodiments, if the trench structure 105 is subsequently electrically connected to a gate electrode, the conductive portion 1052 of the trench structure 105 can not only reduce on-resistance, but also further enhance the reduced surface field (RESURF) effect due to the first conductivity type of the conductive portion 1052.

Furthermore, in semiconductor devices according to some embodiments of the present disclosure, the conductive portion 1052 of the trench structure 105 can also be electrically connected to a source terminal. For example, the conductive portion 1052 can be electrically connected to the first heavily doped portion 108 (source region) and the contact plug 116 (source contact) via other interconnects (not shown) within the semiconductor device. Alternatively, leads can be provided on the conductive portion 1052, and then wirebonded during the packaging process to achieve electrical connection to the first heavily doped portion 108 (source region) and the contact plug 116 (source contact).

The trench structure 105 of the embodiment, whether electrically connected to the gate structure 110 or the source terminal, can reduce the on-resistance of the semiconductor device of the embodiment.

Furthermore, the semiconductor devices of the embodiments can be adapted for use in circuit systems requiring low or high frequency operation through appropriate circuit connections, depending on the application requirements. For example, in some embodiments, the conductive portion 1052 of the trench structure 105 is electrically connected to the gate structure 110. Although this results in a higher gate-drain capacitance (Cgd), the on-resistance is relatively low, making it generally suitable for use in circuit systems requiring low frequency operation. In some embodiments, the conductive portion 1052 of the trench structure 105 is electrically connected to the source terminal. Although the on-resistance is high, the gate-drain capacitance (Cgd) is low, and the switching speed of the device is faster. Therefore, it is generally suitable for applications in circuit systems with high-frequency operation requirements.

Furthermore, the semiconductor device proposed in the embodiment can be flexibly configured and designed according to application requirements. For example, a semiconductor structure may include a plurality of semiconductor cells as shown in the embodiment, disposed on a substrate 100. The conductive portions 1052 of the trench structures 105 of these cells may all be electrically connected to the source terminal, or all be electrically connected to the gate structure 110. Alternatively, a portion of the conductive portions 1052 of the trench structures 105 may be electrically connected to the source terminal, while the remaining portion of the conductive portions 1052 of the trench structures 105 may be electrically connected to the gate structure 110. Therefore, the semiconductor device proposed in the embodiment can be flexibly applied.

This disclosure also presents electrical simulations for conventional semiconductor devices and some embodiments of semiconductor devices. The simulation results demonstrate that the embodiments effectively improve various electronic characteristics of the semiconductor devices. The electrical simulations are described below.

Figure 2 is a schematic cross-sectional view of a conventional semiconductor device. Components in Figure 2 that are identical or similar to those in Figure 1G are numbered identical or similarly, and the details regarding these components in the aforementioned embodiments may be referred to and will not be further elaborated upon here.

As shown in FIG. 2 , semiconductor device 20 includes a plurality of trench structures 205 formed in an epitaxial layer 202 grown on substrate 200. Trench structure 205 includes an insulating layer 2051 and a conductive portion 2052. In simulation tests, the depth of trench structure 205 in epitaxial layer 202 is equal to the sum of the depths of trench structure 105 and doping portion 104 in the embodiment ( FIG. 1G ). The semiconductor device 20 shown in Figure 2 also includes components such as a well region 206 having a second conductivity type (e.g., p-type), a first heavily doped region 208 having a first conductivity type (e.g., n-type), a second heavily doped region 215 having a second conductivity type (e.g., p-type), a gate structure 210, and a contact plug 216. Details of the configuration, materials, and manufacturing methods of the components in Figure 2 can be found in the descriptions of Figures 1A-1G above and will not be repeated here.

In this simulation experiment, various electrical simulation tests were performed using the semiconductor device of the embodiment shown in FIG1G and the conventional semiconductor device shown in FIG2 as comparison examples.

Table 1 lists the relevant dimensions and electrical simulation results of the semiconductor devices when the semiconductor device of the embodiment (Figure 1G) and a conventional semiconductor device (Figure 2) achieve the same breakdown voltage, for example, approximately 80V.

According to simulation results, when achieving the same breakdown voltage (e.g., approximately 80V), the critical dimension (e.g., along the second direction D2) of the epitaxial layer mesa in the conventional semiconductor device (Figure 2) is slightly higher than that of the semiconductor device of the embodiment. However, the trench critical dimension (0.6 micron) of the semiconductor device of the embodiment is only half that of the conventional semiconductor device, and the thickness of the insulating layer (e.g., shielding oxide layer) within the trench is also approximately 53% of that of the conventional semiconductor device. According to Table 1, the cell pitch (2.68 microns) of the semiconductor device of the embodiment is approximately 34% smaller than the cell pitch (4.06 microns) of conventional semiconductor devices. In other words, more semiconductor cells of the embodiment can be arranged within the same unit area.

If the trench structure 205 shown in FIG. 2 is fabricated using the trench opening critical dimension (0.6 microns) and trench insulation layer thickness (1900 angstroms) of the embodiment shown in Table 1 to serve as a field plate in a semiconductor device without the doping portion 104 of the embodiment, the breakdown voltage of the semiconductor device decreases and cannot reach 80V, potentially reaching only 52V, for example. Therefore, the trench structure combined with the doping portion design of the disclosed embodiment can achieve a device design with a higher breakdown voltage by using the trench configuration of a device with a lower breakdown voltage.

Furthermore, according to the electrical performance simulation results in Table 1, the trench structure in the semiconductor device of the embodiment, whether electrically connected to the gate structure or the source terminal, can reduce the on-resistance of the semiconductor device of the embodiment. Taking the trench structure electrically connected to the gate structure as an example, the characteristic on-resistance of the semiconductor device of the embodiment (14.83 mΩ-mm ² ) is significantly improved by approximately 40% compared to the characteristic on-resistance of a conventional semiconductor device (24.68 mΩ-mm ² ). Taking the trench structure electrically connected to the source terminal as an example, the characteristic on-resistance (16.09 mΩ-mm ² ) of the semiconductor device of the embodiment is significantly improved by about 44.5% compared to the characteristic on-resistance (29.02 mΩ-mm ² ) of the conventional semiconductor device.

Furthermore, in both the semiconductor device of the embodiment and conventional semiconductor devices, the trench structure electrically connected to the gate structure provides a field effect, resulting in a lower on-resistance than when electrically connected to the source terminal. According to Table 1, the characteristic on-resistance of the semiconductor device of the embodiment with the trench structure electrically connected to the source terminal (16.09 mΩ-mm ² ) is also lower than the characteristic on-resistance of the conventional semiconductor device with the trench structure electrically connected to the gate structure (24.68 mΩ-mm ² ). Therefore, the semiconductor device of the embodiment effectively improves on-resistance.

In addition, the figure of merit (FOM) can be used to evaluate device performance. The FOM is the product of the characteristic charge (Qg,sp, the charge required per unit area during capacitor charging and discharging) and the characteristic on-resistance (Ron,sp). According to the electrical performance simulation results in Table 1, the FOM of the semiconductor device of the embodiment is lower than that of a conventional semiconductor device, regardless of whether the trench structure is electrically connected to the gate structure or the source terminal. Taking the case of the trench structure electrically connected to the gate structure as an example, the FOM of the semiconductor device of the embodiment (278.02mΩ-nC) is significantly improved by approximately 34.1% compared to the FOM of the conventional semiconductor device (421.93mΩ-nC). Taking the trench structure electrically connected to the source terminal as an example, the FOM of the semiconductor device of the embodiment (83.65mΩ-nC) is improved by approximately 10.4% compared to the FOM of a conventional semiconductor device (93.33mΩ-nC).

Furthermore, the magnitude of a semiconductor device's characteristic charge affects its switching speed. A larger characteristic charge value indicates a greater charge per unit area required for capacitor charging and discharging, resulting in slower switching speeds and a device suitable for low-frequency operation. A smaller characteristic charge value indicates a smaller charge per unit area required for capacitor charging and discharging, resulting in faster switching speeds and a device suitable for high-frequency operation. Table 1 shows that the characteristic charge value of the semiconductor device of the embodiment is only slightly higher than that of conventional semiconductor devices, thus maintaining good switching speed. Furthermore, compared to conventional semiconductor devices, the semiconductor device of the embodiment achieves a significant improvement in characteristic on-resistance without sacrificing characteristic charge.

Furthermore, when operating a semiconductor device with vertical current flow (with the substrate as the drain terminal) at high voltage, excessive electric field strength at the bottom of the trench insulation layer can easily damage the layer, causing leakage between the conductive portion within the trench and the substrate, or even a short circuit, thereby impacting the reliability of the semiconductor device. According to the electrical performance simulation results in Table 1, at the same breakdown voltage (approximately 80V), the electric field strength at the bottom of the trench insulation layer of the semiconductor device of the embodiment (2.18MV/cm) is lower than that of the conventional semiconductor device (2.88MV/cm), representing an improvement of approximately 24.3%. In the semiconductor device of the embodiment, the reduced electric field intensity at the bottom of the trench insulation layer can prevent damage to the trench insulation layer, solving the leakage or short circuit problems that may occur in traditional semiconductor devices, thereby improving the reliability of the semiconductor device.

<Some other examples>

Furthermore, although according to the semiconductor device of the above example, as shown in FIG. 1G , the doping portion 104 extends in the same direction (e.g., the third direction D3) in the first epitaxial portion 1021 as the trench structure 105 extending therefrom in the second epitaxial portion 1022 (e.g., the third direction D3), these doping portions 104 may be pillars of the second conductivity type, such as P-type pillars, spaced apart from each other in the first epitaxial portion 1021 and extending in the same direction. However, the doping portion 104 and trench structure 105 of the present disclosure are not limited to the above configuration. The doping portion 104 and trench structure 105 of the embodiment may extend in the same or different directions (e.g., perpendicular to each other), and the shape of the doping portion 104 is not particularly limited.

The following describes configurations of the doping portion 104 and the trench structure 105 that are applicable to some (but not all) embodiments.

FIG3 is a schematic top view of a dopant and trench structure of a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the dopant 304 and trench structure 305 extend in different directions. As shown in FIG3 , the trench structure 305 extends along a third direction D3 in the second epitaxial portion 1022 . In some embodiments, the dopant 304 extends along a second direction D2 in the first epitaxial portion 1021 , where the second direction D2 is perpendicular to the third direction D3 .

In addition, in some other embodiments, the extension direction of the doping portion 104 and the extension direction of the trench structure 105 may have an angle (not shown), and this angle is within the range of greater than 0 degrees to less than 90 degrees.

Furthermore, the doped portion 104 of the present disclosure may have other shapes besides the second conductivity type pillars (e.g., P-type pillars) described in the above embodiment. For example, the doped portion 104 may be island blocks of the second conductivity type. When viewed from above the epitaxial layer 102, the top surfaces of these island blocks may be rectangular, square, circular, elliptical, hexagonal, other polygonal, ring-shaped, or other suitable shapes. This disclosure is not particularly limited in this regard.

Figures 4A-4C are schematic top views of doping and trench structures of a semiconductor device according to some embodiments of the present disclosure. As shown in Figures 4A-4C, doping portions 404A, 404B, and 404C are islands of the second conductivity type. These islands are spaced apart from one another in the first epitaxial portion 1021, and the bottom of each trench structure 305 may contact one or more islands. Furthermore, the islands corresponding to adjacent trench structures 305 may be arranged in multiple rows or staggered.

As shown in FIG. 4A , in some embodiments, the doped portions 404A are islands having rectangular top surfaces and are spaced apart in the first epitaxial portion 1021 , wherein the bottom of the trench structure 305 contacts two or more doped portions 404A.

As shown in FIG. 4B , in some embodiments, the doped portions 404B are islands with rounded top surfaces disposed at intervals in the first epitaxial portion 1021 , wherein the bottom of the trench structure 305 contacts two or more doped portions 404B.

As shown in FIG. 4C , in some embodiments, the doped portions 404C are islands having hexagonal top surfaces and are spaced apart in the first epitaxial portion 1021 , wherein the bottom of the trench structure 305 contacts two or more doped portions 404C.

Figure 5 is a schematic top view of a doping and trench structure of a semiconductor device according to some embodiments of the present disclosure. As shown in Figure 5 , in some embodiments, doping 504 is a hollow pillar of the second conductivity type. These hollow pillars have an annular top surface in the first epitaxial portion 1021. The bottom of the trench structure 305 contacts the doping 504. Furthermore, these dopings 504 are, for example, arranged in a concentric arrangement.

For details on the configuration, materials, and manufacturing methods of the doped portions 304, 404A, 404B, 404C, 504, and trench structure 305, please refer to the description of the doped portion 104 and trench structure 105 in Figures 1A-1D above and will not be repeated here.

In summary, the semiconductor device proposed in the embodiment has many advantages. For example, a component design suitable for low voltage operation (including a smaller cell pitch and a narrower trench structure) can be used in conjunction with the doping portion below to realize a semiconductor device suitable for high voltage operation. Therefore, more semiconductor cells of the embodiment can be formed under the same unit area. Furthermore, the semiconductor device proposed in the above embodiment can effectively reduce the on-resistance and improve the electrical performance of the semiconductor device. Furthermore, the doping portion proposed in the embodiment can reduce the electric field strength at the bottom of the trench insulating layer, thereby avoiding the formation of a leakage path or even a short circuit between the bottom of the insulating layer and the substrate to which a high voltage is applied. Therefore, the semiconductor device proposed in the embodiment can have better reliability. Furthermore, the method for forming the semiconductor device proposed in the embodiment can be fabricated through simple steps. For example, only a single photomask is required to form the doping portion of the embodiment in the lower portion of the epitaxial layer. This method is simple and compatible with existing processes.

10: Semiconductor devices

100: Base

102: Epitaxial layer

1021: First epitaxial section

1022: Second epitaxial section

104: Mixed

105: Groove structure

1051: Insulation layer

1052: Conductive Department

1021a: Top surface

106b, 1052b: Bottom surface

106: Well Area

106s1: First side wall

106s2: Second side wall

_RD : Drifting Zone

108: First Mixture

110: Gate structure

111: Gate dielectric layer

112: Gate electrode

114: Interlayer dielectric layer

115: Second Mixture

116: Contact plug

1161: Contact barrier

1162: Contact with conductive layer

T1: First thickness

T2: Second thickness

dp1: First depth

dp2: Second depth

D1: First Direction

D2: Second Direction

D3: Third direction

Claims (28)

A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer located above the substrate, the epitaxial layer having the first conductivity type, wherein the epitaxial layer includes: a first epitaxial portion located on the substrate; and a second epitaxial portion located on the first epitaxial portion; a plurality of doping portions disposed in the first epitaxial portion, the doping portions having a second conductivity type, wherein the first epitaxial portion includes only the doping portions having the second conductivity type; a trench structure disposed in the second epitaxial portion and extending downward from a top surface of the second epitaxial portion, wherein the trench The trench structure includes a conductive portion and an insulating layer covering the sidewalls and bottom of the conductive portion, wherein the insulating layer of the trench structure contacts one of the doped portions; a well region extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, and the well region has the second conductivity type, wherein a first sidewall of the well region contacts the trench structure, and a second sidewall of the well region, whose bottom surface is opposite to the first sidewall, contacts the second epitaxial portion; a gate structure formed on the top surface of the second epitaxial portion and corresponding to the well region; and a contact plug located between the gate structure and the trench structure. The semiconductor device of claim 1, wherein the conductive portion of the trench structure and the doped portion of the corresponding contact are electrically isolated by the insulating layer of the trench structure. The semiconductor device of claim 1, wherein top surfaces of the doped portions are coplanar with a top surface of the first epitaxial portion. The semiconductor device of claim 1, wherein a bottom surface of the conductive portion of the trench structure is lower than the bottom surface of the well region, and the bottom surface of the conductive portion is higher than a top surface of the first epitaxial portion. The semiconductor device of claim 1, wherein the doping concentrations of the doping portions disposed in the first epitaxial portion are equal to the doping concentration of the first epitaxial portion. The semiconductor device of claim 1 further includes: a first heavily doped portion formed in the well region and extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, and the first heavily doped portion has the first conductivity type, wherein the doping concentration of the doping portions arranged in the first epitaxial portion is less than the doping concentration of the first heavily doped portion. The semiconductor device of claim 6 further includes: a second heavily doped portion formed in the well region and adjacent to the trench structure, and the second heavily doped portion has the second conductivity type, wherein the doping concentration of the doping portions arranged in the first epitaxial portion is less than the doping concentration of the second heavily doped portion. The semiconductor device of claim 1, wherein a ratio of a depth of the doping portions in the first epitaxial portion to a depth of the trench structure in the second epitaxial portion is in a range of 0.5 to 1.5. The semiconductor device of claim 1, wherein a ratio of a depth of the doping portions in the first epitaxial portion to a thickness of the first epitaxial portion is in a range of 0.4 to 0.9. The semiconductor device of claim 1, wherein an extension direction of the doped portions in the first epitaxial portion is the same as an extension direction of the trench structure in the second epitaxial portion. The semiconductor device of claim 1, wherein an extension direction of the doping portions in the first epitaxial portion is different from an extension direction of the trench structure in the second epitaxial portion. The semiconductor device of claim 1, wherein the doped portions are pillars having the second conductivity type, and the pillars are spaced apart from each other in the first epitaxial portion and extend along the same direction. The semiconductor device of claim 12, wherein the width of the bottom surface of the trench structure is smaller than the width of the top surface of the pillar in contact therewith. The semiconductor device of claim 1, wherein the doped portions are islands having the second conductivity type, the islands are arranged apart from each other in the first epitaxial portion, and the bottom of the trench structure contacts two or more of the islands. As in the semiconductor device of claim 14, wherein when looking down at the epitaxial layer, the top surfaces of the islands are rectangular, square, circular, elliptical, hexagonal, or other polygonal shapes. The semiconductor device of claim 1, wherein the doped portions are hollow tubes having the second conductivity type, and the hollow tubes have a ring-shaped top surface in the first epitaxial portion. The semiconductor device of claim 1, wherein the conductive portion of the trench structure is electrically connected to a source terminal of the semiconductor device. The semiconductor device of claim 1, wherein the conductive portion of the trench structure is electrically connected to the gate structure. A method for forming a semiconductor device includes: providing a substrate having a first conductivity type; forming a first epitaxial portion having the first conductivity type on the substrate; forming a plurality of doping portions in the first epitaxial portion, wherein the doping portions have a second conductivity type, wherein the doping portions extend downward from a top surface of the first epitaxial portion into the first epitaxial portion, wherein the first epitaxial portion only includes the doping portions having the second conductivity type; forming a second epitaxial portion having the first conductivity type on the first epitaxial portion, wherein the first epitaxial portion and the second epitaxial portion form an epitaxial layer; forming a trench structure extending downward from a top surface of the second epitaxial portion and contacting a corresponding one of the doped portions, wherein the trench structure includes a conductive portion and an insulating layer covering the sidewalls and bottom of the conductive portion, the insulating layer directly contacting the corresponding doped portion; forming a well region extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, and the well region has the second conductive portion. Type, wherein a first sidewall of the well region contacts the trench structure, and a second sidewall of the well region opposite to the first sidewall contacts the second epitaxial portion; a gate structure is formed on the top surface of the second epitaxial portion, the gate structure corresponding to the well region below; and a contact plug is formed between the gate structure and the trench structure. A method for forming a semiconductor device as claimed in claim 19, wherein the doping portions are formed after forming the first epitaxial portion and before forming the second epitaxial portion. A method for forming a semiconductor device as claimed in claim 19, wherein forming the doped portions comprises: forming a mask above the first epitaxial portion, the mask having a pattern corresponding to the doped portions; performing an ion implantation process on the first epitaxial portion through the pattern of the mask to form a plurality of doped regions in the first epitaxial portion, wherein the doped regions include dopants of the second conductivity type; and performing a thermal drive-in process to diffuse the doped regions to the surrounding areas to form the doped portions. A method for forming a semiconductor device as claimed in claim 19, wherein forming the doping portions comprises: forming a plurality of holes in the first epitaxial portion, wherein the holes extend downward from the top surface of the first epitaxial portion into the first epitaxial portion; and filling the holes with a material having the second conductivity type to form the doping portions. A method for forming a semiconductor device as claimed in claim 19, wherein the doped portions and the first epitaxial portion contain the same semiconductor material. The method for forming a semiconductor device as claimed in claim 19, wherein the conductive portion of the trench structure and the doped portion of the corresponding contact are electrically isolated by the insulating layer of the trench structure. The method for forming a semiconductor device as claimed in claim 19, wherein the doping concentrations of the doping portions formed in the first epitaxial portion are equal to the doping concentration of the first epitaxial portion. The method for forming a semiconductor device as claimed in claim 19, wherein a ratio of a depth of the doping portions formed in the first epitaxial portion to a depth of the trench structure formed in the second epitaxial portion is in a range of 0.5 to 1.5. A method for forming a semiconductor device as claimed in claim 19, which, before forming the gate structure, further includes: doping in the well region from the top surface of the second epitaxial portion to form a first heavily doped portion, and the first heavily doped portion has the first conductivity type, wherein the doping concentration of the first heavily doped portion is greater than the doping concentration of the doping portions, and wherein the gate structure corresponds to the first heavily doped portion below. The method for forming a semiconductor device as claimed in claim 27, wherein after forming the gate structure, the method further comprises: forming an interlayer dielectric layer on the top surface of the second epitaxial portion and covering the gate structure, the first heavily doped region and the trench structure; removing a portion of the interlayer dielectric layer, a portion of the first heavily doped region and a portion of the well region to form a contact A contact hole is formed in the well region, wherein the bottom of the contact hole exposes the well region; doping in the well region through the contact hole to form a second heavily doped portion below the contact hole, wherein the doping concentration of the doped portions formed in the first epitaxial portion is less than the doping concentration of the second heavily doped portion; and forming the contact plug in the contact hole, with the bottom of the contact plug contacting the second heavily doped portion.