TWI812909B - High voltage semiconductor device - Google Patents

Abstract

A high voltage semiconductor device includes a substrate, a first high voltage well region, a second high voltage well region, a third high voltage well region, a drain region, a source region, a gate structure, and a doped region. The substrate has a first conductivity type. The first high voltage well region is disposed over the substrate and has a second conductivity type opposite to the first conductivity type. The second high voltage well region is disposed adjacent to and in contact with the first high voltage well region, and has the first conductivity type. The third high voltage well region is disposed adjacent to and in contact with the first high voltage well region, and has the second conductivity type. The drain region is disposed in the first high voltage well region. The gate structure is disposed between the source region and the drain region. The doped region is disposed in the third high voltage well region and has the second conductivity type.

Description

High voltage semiconductor device

The present disclosure relates to a high-voltage semiconductor device, particularly a high-voltage semiconductor device having a doped region in an external high-voltage well region.

Semiconductor integrated circuit (IC) technology has developed rapidly, among which high-voltage semiconductor device technology has been developed for high voltage and high power applications. High-voltage semiconductor devices include vertically diffused metal oxide semiconductor (VDMOS) transistors and laterally diffused metal oxide semiconductor (LDMOS) transistors, and the advantage of high-voltage semiconductor devices is that they are cost-effective , and easily compatible with other processes, it has been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control and other fields.

Although existing technologies for high voltage semiconductor devices are generally adequate for their intended purposes, they are not satisfactory in every respect. With the development of high-voltage semiconductor device technology, the high-voltage semiconductor device is expected to have a larger operating voltage, and thus requires a larger breakdown voltage. Therefore, there is a need for a high-voltage semiconductor device with a larger breakdown voltage.

The present disclosure provides a high voltage semiconductor device. The high-voltage semiconductor device includes a substrate, a first high-voltage well region, a second high-voltage well region, a third high-voltage well region, a drain region, a source region, a gate structure, and a doping region. The substrate has a first conductivity type. The first high voltage well region is disposed above the substrate and has a second conductivity type opposite to the first conductivity type. The second high-pressure well zone is disposed adjacent to and in contact with the first high-pressure well zone, and has the first conductivity type. The third high-pressure well zone is disposed adjacent to and in contact with the first high-pressure well zone, and has a second conductivity type. The drain region is arranged in the first high-pressure well region. The gate structure is arranged between the source region and the drain region. The doped region is disposed in the third high-voltage well region and has a second conductivity type.

In some embodiments, the high-voltage semiconductor device further includes a buried layer disposed under the second high-voltage well region and the third high-voltage well region and having a second conductivity type.

In some embodiments, the boundary of the buried layer is a predetermined distance away from the boundary between the first high-pressure well zone and the second high-pressure well zone.

In some embodiments, the high-voltage semiconductor device further includes a dielectric layer, a metal contact, and a metal layer. A dielectric layer is disposed above the substrate. Metal contacts are disposed in the dielectric layer and contact the doped regions. The metal layer is disposed above the dielectric layer and contacts the metal contacts.

In some embodiments, the ratio of the depth of the doped region to the depth of the third high pressure well region is in the range of 0.006 to 0.01.

The present disclosure provides a high voltage semiconductor device. The high-voltage semiconductor device includes a substrate, a high-voltage well region, a first annular well region, a second annular well region, a drain region, an annular gate structure, an annular source region, and an annular doping region. The high voltage well region is disposed above the substrate and has a first conductive type dopant. The first annular well region is disposed surrounding and contacting the high voltage well region and has a second conductivity type dopant that is opposite to the first conductivity type dopant. The second annular well region is disposed surrounding the first annular well region and has a first conductive type dopant. The drain zone is arranged in the high-pressure well zone. The annular gate structure is disposed above the high-pressure well region and surrounds the drain region. The annular source region is disposed in the first annular well region and surrounds the annular gate structure. The annular doping region is disposed in the second annular well region and has a first conductive type dopant.

In some embodiments, the high-voltage semiconductor device further includes an annular buried layer disposed under the first annular well region and the second annular well region and having a first conductive type dopant.

In some embodiments, the inner boundary of the annular buried layer is spaced a predetermined distance from the outer boundary of the high-pressure well zone.

In some embodiments, the high-voltage semiconductor device further includes a dielectric layer, a metal contact, and a metal layer. A dielectric layer is disposed above the substrate. The metal contact is disposed in the dielectric layer and contacts the annular doped region. The metal layer is disposed above the dielectric layer and contacts the metal contacts.

In some embodiments, the ratio of the depth of the annular doped region to the depth of the second annular well region is in the range of 0.006 to 0.01.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the explanation. Of course, these specific examples are not limiting. For example, if this disclosure describes that a first feature is formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which the first feature is in direct contact with the second feature. Embodiments in which additional features are formed between the first features and the second features such that the first features and the second features may not be in direct contact. In addition, the same reference symbols and/or marks may be repeatedly used in different examples of the following disclosures. These repetitions are for the purpose of simplicity and clarity and are not intended to limit specific relationships between the various embodiments and/or structures discussed.

For the purposes of this disclosure, unless specifically expressly stated otherwise, the singular includes the plural and vice versa. And the word "includes" means "includes without limitation." In addition, approximation terms such as “approximately”, “almost”, “approximately”, “approximately”, etc. may be used in the embodiments of the present disclosure, with the meanings such as “at, close to, or close to” or “ Within 3 to 5%” or “Within acceptable manufacturing tolerances” or any logical combination.

Furthermore, it is worded in relation to space. For example, words such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of one element or feature in the illustrations in relation to another element or feature. relationship between. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the schematic diagram is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. In this way, the model word "down" will cover both interpretations: upward and downward. In addition, the device may be turned in different orientations (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and does not limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "include," "include," "have," "have," "contains" or variations thereof are used in the detailed description and/or claims, these terms are intended to be used in similar terms. Inclusive by way of "include".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms such as those defined in general dictionaries should be construed to have the same meaning as they do in the context of the relevant field and are not to be construed as idealistic or overly formal unless expressly so stated herein. definition.

The present disclosure relates generally to high voltage semiconductor devices. In a common high-voltage semiconductor device, a high-voltage well region is used as an isolation region on the outer periphery of the high-voltage semiconductor device so that the high-voltage semiconductor device does not affect adjacent components during operation. However, with the development of high-voltage semiconductor device technology, it is expected that the high-voltage semiconductor device can have a larger operating voltage. Therefore, the high-voltage well region as an isolation region needs to be improved to have a larger breakdown voltage to prevent the high-voltage semiconductor device from affecting adjacent components when operating at a larger operating voltage.

FIG. 1A is a top view of the high-voltage semiconductor device 100 according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view of the high-voltage semiconductor device 100 according to an embodiment of the present disclosure. According to some embodiments, high voltage semiconductor device 100 is formed on substrate 102 . Substrate 102 may be composed generally of silicon. In some embodiments, the substrate 102 may include another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide ;Alloy semiconductors, such as silicon germanium (SiGe), silicon carbon phosphide (SiPC), gallium arsenide phosphorus (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs) , gallium indium phosphide (GaInP) and/or gallium indium arsenide phosphide (GaInAsP); or combinations thereof.

Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (germanium-on-insulator). -insulator; GOI) substrate. Semiconductor-on-insulator substrates can be manufactured by separation by implantation of oxygen (SIMOX), wafer bonding and/or other suitable methods.

In some embodiments, the substrate 102 may have a first conductivity type, such as a P-type conductivity type or an N-type conductivity type. Specifically, the substrate 102 may have a first conductivity type dopant, such as a P-type dopant or an N-type dopant. N-type dopants may include phosphorus (P), arsenic (As), other N-type dopants, or combinations thereof. P-type dopants may include boron (B), indium (In), other P-type dopants, or combinations thereof.

Doped regions 104 and 106 are provided in substrate 102 . In some embodiments, the doped region 104 may have a second conductivity type (eg, N-type conductivity type or P-type conductivity type) that is opposite to the first conductivity type (eg, P-type conductivity type or N-type conductivity type) of the substrate, And the doped region 106 may have the same first conductivity type as the substrate. Specifically, the doped region 104 may have a second conductivity type dopant (eg, an N-type dopant or a P-type dopant), and the doping region 106 may have a first conductivity type dopant (eg, a P-type dopant). dopants or N-type dopants). The doped regions 104 and 106 may be formed in the substrate 102 through one or more doping processes, such as a diffusion process or an ion implantation process. In some embodiments, the doping concentration of the doped region 104 may range from 5x10 ¹² atoms/cm ³ to about 1x10 ¹³ atoms/cm ³ , and the doped region The doping concentration of 106 may range from 3x10 ¹² atoms/cm ³ to about 8x10 ¹² atoms/cm ³ . Additionally, in some embodiments, the thickness of doped regions 104 and 106 perpendicular to the top surface of substrate 102 is about 8 microns. In some embodiments, doped regions 104 and 106 may be referred to as buried layers. In addition, as shown in FIG. 1A , the doping regions 104 and 106 are annular or have an annular layout (shown with dotted lines) in plan view, and therefore the doping regions 104 and 106 can also be called annular doping regions.

Referring to FIG. 1B , the epitaxial layer 108 is disposed above the substrate 102 . The epitaxial layer 108 may be an epitaxial semiconductor material having a first conductivity type or a second conductivity type (eg, epitaxially grown silicon (Si) or other suitable materials). In some embodiments, the epitaxial layer 108 can be formed by metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (Plasma-enhanced CVD; PECVD), molecular beam epitaxy ( molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride-vapor phase epitaxy (Cl-VPE) ), other process methods or combinations thereof.

Still referring to FIG. 1B , high pressure well regions 110 , 112 , 114 , 116 are provided in the epitaxial layer 108 . In some embodiments, high voltage well regions 112, 116 may have a first conductivity type (i.e., have first conductivity type dopants) and high pressure well regions 110, 114 may have a second conductivity type (i.e., have a second conductivity type dopant). adulterants). Similar to doped regions 104 and 106, high voltage well regions 110, 112, 114, 116 may be formed in the epitaxial layer 108 through one or more doping processes. It is worth noting that the high-pressure well areas 110 and 112 are adjacent to and in contact with each other, while the high-pressure well areas 112, 114, and 116 are spaced apart from each other. In addition, as shown in Figure 1A, the high-pressure well areas 112, 114, and 116 are annular or have an annular layout in a plan view, and therefore the high-pressure well areas 112, 114, and 116 can also be called annular well areas or annular high-pressure well areas. The high-pressure well zone 112 surrounds the high-pressure well zone 110 , the high-pressure well zone 114 surrounds the high-pressure well zone 112 , and the high-pressure well zone 116 surrounds the high-pressure well zone 114 .

Referring again to Figure 1B, the drift region 118 is disposed in the high pressure well region 110, the well region 120 is disposed in the drift region 118, and the drain region 122 is disposed in the well region 120, wherein the drift region 118, the well region 120, and the drain region The pole regions 122 all have the second conductivity type (ie, have second conductivity type dopants). In some embodiments, the drain region 122 has a doping concentration greater than the well region 120 , the well region 120 has a doping concentration greater than the drift region 118 , and the drift region 118 has a doping concentration greater than the high pressure well. Doping concentration of region 110. In some embodiments, the high-pressure well region 110 may have a doping concentration in the range of 1x10 ¹² atoms/cm ³ to about 5x10 ¹² atoms/cm ³ , and the drift region 118 may have a doping concentration in the range of 6x10 12 atoms/cm 3 to about 5x10 ¹² atoms/cm ³ The doping concentration of the well region 120 may be in the range of 1x10 ¹³ atoms/cm ³ to about 5x10 13 atoms/cm ³ in the range of about 9x10 ¹³ atoms/cm ³ , and the drain region 122 may be in the range of 1x10 ¹⁵ atoms/cm ³ In the range of ³ to about 5x10 ¹⁵ atoms/cm ³ .

A body region 124 is formed in the high voltage well region 112 , and a source region 130 is formed in the body region 124 , where the source region 130 includes doping regions 126 and 128 . Body region 124 and doped region 126 have a first conductivity type (ie, have first conductivity type dopants), and doped region 128 has a second conductivity type (ie, have second conductivity type dopants). In some embodiments, the doping concentration of the doped regions 126 , 128 is greater than the doping concentration of the body region 124 , and the doping concentration of the body region 124 is greater than the doping concentration of the high pressure well region 112 . In some embodiments, the doping concentration of the doped regions 126, 128 may range from 1x10 ¹⁵ atoms/cm ³ to about 5x10 ¹⁵ atoms/cm ³ and the doping concentration of the body region 124 may be in the range of 1x10 ¹³ atoms/cm 3 cm ³ to approximately 5x10 ¹³ atoms/cm ³ . As described above, similar to the high pressure well regions 110, 112, 114, and 116, the drift region 118, the well region 120, the drain region 122, the body region 124, and the doped regions 126 and 128 can each be formed by one or more Formed by doping process.

Complex oxide structures 132-1, 132-2, 132-3, 132-4 are disposed on and partially embedded in the epitaxial layer 108. In some embodiments, oxide structures 132-1, 132-2, 132-3, 132-4 may be composed of silicon oxide, silicon nitride, or silicon oxynitride, and may be silicon partial oxidation formed by thermal oxidation. (local oxidation of silicon; LOCOS). In other embodiments, the oxide structures 132-1, 132-2, 132-3, and 132-4 may be shallow trench isolation (STI) structures formed by etching and deposition processes.

Gate structure 134 is disposed on epitaxial layer 108 and may include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include silicon oxide, silicon oxynitride, aluminum silicon oxide, high-k dielectric materials (such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), and other suitable dielectric materials or a combination thereof, and can be formed by chemical vapor deposition (CVD), spin coating, or other suitable processes. The gate electrode layer may include amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, conductive metal oxides, other suitable materials, or combinations thereof, and may be evaporated by CVD, sputtering, resistance heating, Formed by electron beam evaporation or other suitable deposition processes. It is worth noting that, as shown in Figure 1B, a portion of the gate structure 134 is disposed on the oxide structure 132-1. In this embodiment, the oxide structure 132-1 may be referred to as a field oxide to increase the drain-to-gate punch through voltage.

In some embodiments, the gate structure 134 may further include one or more work function metal layers to adjust the work function of the gate structure 134 . Materials of the work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium disilicide (ZrSi2) , Molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), titanium (Ti), silver (Ag), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride ( TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), other suitable work function materials or combinations thereof, and the work function metal layer can Deposited by atomic layer deposition (ALD), CVD and/or other suitable processes.

As shown in FIG. 1A , the source region 130 is annular or has an annular layout in a plan view, and therefore the source region 130 can also be called an annular source region, and surrounds the high-voltage well region 110 and the drain region 122 . In addition, although not shown in FIG. 1A , in this embodiment, the gate structure 134 may also be annular or have an annular layout, and therefore the gate structure 134 may also be called an annular gate structure and surrounds the drain region 122 . Therefore, the source region 130 also surrounds the gate structure 134, or the gate structure 134 is disposed between the drain region 122 and the source region 130.

The doping regions 136 and 138 may be individually disposed in the high pressure well regions 114 and 116 through one or more doping processes. Doped region 138 has a first conductivity type (ie, has first conductivity type dopants), and doped region 136 has a second conductivity type (ie, has second conductivity type dopants). In some embodiments, the doping concentrations of doped regions 136, 138 are respectively greater than the doping concentrations of high pressure well regions 114 and 116. In some embodiments, the doping concentration of the doped regions 136, 138 may range from 1×10 ¹⁵ atoms/cm ³ to about 5×10 ¹⁵ atoms/cm ³ . In addition, as shown in FIG. 1A , the doping regions 136 and 138 are annular or have annular layout in plan view, and therefore the doping regions 136 and 138 can also be called annular doping regions, wherein the doping regions 136 surround the high-pressure well. region 110, the drain region 122, the gate structure 134, the high voltage well region 112, and the source region 130, and the doping region 138 surrounds the high voltage well region 110, the drain region 122, the gate structure 134, the high pressure well region 112, Source region 130 , high voltage well region 114 , and doping region 136 .

Referring again to FIG. 1B , the interconnect structure is disposed above the epitaxial layer 108 . The interconnect structure may include a plurality of conductive features configured to interconnect the high voltage semiconductor device 100 with additional devices, components, voltage sources, etc. to ensure proper performance of the high voltage semiconductor device 100 . The interconnect structure includes various conductive and dielectric layers. The conductive layers are configured to form vertical interconnect features, such as vertical interconnect structures (eg, vias 142, 148) and/or horizontal interconnect structures (eg, conductors 146, 150). Each horizontal interconnect feature disposed in a dielectric layer may be referred to as a "metal layer," and two different metal layers may be electrically coupled by one or more vertical interconnect structures. Various conductive layers are embedded in the dielectric layers, such as dielectric layers 140 and 144. As shown in FIG. 1B , the source region 130 and the doped region 138 are respectively connected to the via hole 142 and the wire 146 , and the drain region 122 is connected to the via hole 142 , the wire 146 , the via hole 148 , and the wire 150 . Each conductive layer (e.g., vias 142, 148 and wires 146, 150) may include copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), other suitable metals, or the like. In combination, and in some embodiments may further include a barrier layer including titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN). Dielectric layers 140 and 144 may be referred to as interlayer dielectric (ILD) layers. In some embodiments, dielectric layers 140 and 144 may include silicon oxide, tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (borophosphosilicate glass; BPSG), fused silica glass (FSG), phosphosilicate glass (phosphosilicate glass; PSG), boron doped silicon glass (BSG), other suitable dielectric materials or its combination. In some embodiments, dielectric layers 140 and 144 may be formed using CVD, flowable CVD (FCD), or spin-on glass.

As mentioned above, in the embodiment of the present disclosure, the high-voltage well region 114 is used as an isolation region on the outer periphery of the high-voltage semiconductor device 100 so that the high-voltage semiconductor device does not affect adjacent components during operation. In order for the high-voltage semiconductor device 100 to operate at a larger operating voltage without affecting adjacent components, the lateral punch voltage of the high-voltage semiconductor device 100 needs to be increased. In the disclosed embodiment, the doped region 136 is disposed in the high voltage well region 114 to further increase the lateral breakdown voltage. As mentioned above, the doping concentration of the doped region 136 is greater than the doping concentration of the high voltage well region 114 . As a result, because the dopants in the doped region 136 can partially diffuse into the high-voltage well region 114 , the doping concentration of the high-voltage well region 114 will increase, thereby shrinking the depletion region to have a greater lateral collapse voltage. It is worth noting that the doped region 136 is disposed above the high-pressure well region 114 . Specifically, the ratio of the depth H1 of the doped region 136 to the depth H2 of the high-pressure well region 114 ranges from about 0.006 to about 0.01. If the depth H1 of the doped region 136 is too small, the lateral collapse voltage cannot be effectively increased. If the depth H1 of the doped region 136 is too large, the junction breakdown voltage (Junction Breakdown) of this element will decrease (which will lead to the collapse of the high-voltage well region 114 to the high-voltage well region 116 ).

FIG. 2 is a comparison diagram of breakdown voltage between the high-voltage semiconductor device 100 according to the embodiment of the present disclosure and the conventional high-voltage semiconductor device. The peripheral high-pressure well region of the conventional high-voltage semiconductor device does not have a doped region, while the peripheral high-pressure well region (eg, the high-pressure well region 114 ) of the high-voltage semiconductor device 100 has a doped region (eg, the doped region 136 ). As shown in FIG. 2 , in the drain current-drain voltage characteristic diagram (Id-Vd characteristic diagram), curves 202 and 204 respectively represent the Id-Vd characteristics of the conventional high-voltage semiconductor device and the high-voltage semiconductor device 100 . When the drain voltage of a conventional high-voltage semiconductor device increases to about 90V, lateral collapse occurs and the drain current rises sharply. In contrast, since the peripheral high-voltage well region of the high-voltage semiconductor device 100 has a doping region, lateral collapse occurs only when the drain voltage increases to about 167V, and the drain current rises sharply. Therefore, setting a doping region in the peripheral high-voltage well region of a high-voltage semiconductor device can effectively increase the lateral collapse voltage.

Referring again to FIGS. 1A and 1B , the doped region 104 is disposed below the high-pressure well regions 112 and 114 . It is worth noting that in the disclosed embodiment, the doped region 104 does not extend below the high-pressure well region 110 . Specifically, the boundary of the doping region 104 (as shown in FIG. 1A , the inner boundary of the doping region 104 ) is separated from the boundary of the high-pressure well region 110 (as shown in FIG. 1A , the outer boundary of the high-pressure well region 110 ). A predetermined distance D1 is provided to prevent leakage current from the drain region 122 to the doped region 104 . In addition, if the distance D1 is too large, the doped region 104 cannot effectively prevent vertical leakage from the high-voltage well region 112 to the substrate 102 .

FIG. 3 is a cross-sectional view of a high-voltage semiconductor device 100 of another embodiment, in which via holes 152 and conductive lines 154 are additionally formed above the doped region 136 . In this case, the doped region 136 , the high voltage well region 114 , the doped region 104 , and the drain region 122 may constitute the circuit 302 . As mentioned above, the boundary of the doped region 104 and the boundary of the high voltage well region 110 are separated by a distance D1, and this portion constitutes the resistor 304 in the circuit 302. In this embodiment, by measuring the resistance value of the resistor 304 in the circuit 302, it can be monitored whether the distance D1 complies with the design. Specifically, the series of processes used to form the high-voltage semiconductor device 100 may affect the profile of the doped region 104 . For example, the manufacturing process of the high-voltage semiconductor device 100 may cause the doped region 104 to extend below the extended high-voltage well region 110 (ie, the distance D1 is reduced), thereby causing the resistance value of the resistor 304 in the circuit 302 to be reduced. As a result, leakage from the drain region 122 to the doped region 104 occurs in the resulting high-voltage semiconductor device 100 during operation. Therefore, by measuring the resistance value of the resistor 304 in the circuit 302, it can be determined whether the high-voltage semiconductor device 100 meets the design requirements or has defects.

Compared with the prior art, embodiments of the present invention provide multiple advantages, and it should be understood that other embodiments may provide different advantages. It is not necessary to discuss all advantages here, and all embodiments have no specific advantages.

The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the present disclosure from various aspects. It should be understood by those with ordinary skill in the art that other processes and structures can be easily designed or modified based on this disclosure to achieve the same purpose and/or achieve the same results as the embodiments introduced here. The advantages. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure. Various changes, substitutions, or modifications may be made to the disclosure without departing from the spirit and scope of the disclosure.

100:High voltage semiconductor device 102:Substrate 104: Doped area 106: Doped area 108: Epitaxial layer 110:High pressure well area 112:High pressure well area 114:High pressure well area 116:High pressure well area 118:Drift area 120:Well area 122: Drainage area 124: Ontology area 126: Doped area 128: Doped area 130: Source area 132-1:Oxide structure 132-2:Oxide structure 132-3:Oxide structure 132-4:Oxide structure 134: Gate structure 136: Doped area 138: Doped area 140: Dielectric layer 142:Through hole 144:Dielectric layer 146:Wire 148:Through hole 150:Wire H1: Depth H2: Depth D1: distance 202:Curve 204:Curve 152:Through hole 154:Wire 302:Circuit 304: Resistor

In order to describe the present disclosure in a manner that covers the above examples, other advantages and features, the principles of the above brief description will be described in more detail through specific examples in the drawings. It should be understood that the drawings shown here are only examples of the disclosure and do not limit the scope of the disclosure. The principles of the present disclosure are described and explained with additional features and details by means of the accompanying drawings, in which: 1A is a top view of a high-voltage semiconductor device having a doped region in an isolated high-voltage well region according to an embodiment of the present disclosure. 1B is a cross-sectional view of a high-voltage semiconductor device having a doped region in an isolated high-voltage well region according to an embodiment of the present disclosure. FIG. 2 is a comparison chart of breakdown voltage of a high-voltage semiconductor device according to an embodiment of the present disclosure and a conventional high-voltage semiconductor device. 3 is a cross-sectional view of a high-voltage semiconductor device having a doped region in an isolated high-voltage well region according to an embodiment of the present disclosure, wherein a via hole and a metal layer are additionally formed above the doped region.

100:High voltage semiconductor device

102:Substrate

104: Doped area

106: Doped area

108: Epitaxial layer

110:High pressure well area

112:High pressure well area

114:High pressure well area

116:High pressure well area

118:Drift area

120:Well area

122: Drainage area

124: Ontology area

126: Doped area

128: Doped area

132-1:Oxide structure

132-2:Oxide structure

132-3:Oxide structure

132-4:Oxide structure

134: Gate structure

136: Doped area

138: Doped area

140: Dielectric layer

142:Through hole

144:Dielectric layer

146:Wire

148:Through hole

150:Wire

H1: Depth

H2: Depth

D1: distance

Claims (10)

A high-voltage semiconductor device includes: a substrate having a first conductivity type; a first high-voltage well region disposed above the substrate and having a second conductivity type opposite to the first conductivity type; a second high-voltage well region A well area is arranged adjacent to and in contact with the above-mentioned first high-pressure well area and has the above-mentioned first conductivity type; a third high-pressure well area is arranged apart from the above-mentioned second high-pressure well area and has the above-mentioned second conductivity type; A drain region is disposed in the first high-voltage well region; a source region is disposed in the second high-voltage well region; a gate structure is disposed between the source region and the drain region; and a The doped region is disposed in the third high-voltage well region and has the second conductivity type. The high-voltage semiconductor device of claim 1 further includes: a buried layer disposed under the second high-pressure well region and the third high-pressure well region and having the second conductivity type. The high-voltage semiconductor device of claim 2, wherein a boundary of the buried layer is separated by a predetermined distance from a boundary between the first high-pressure well region and the second high-pressure well region. The high-voltage semiconductor device of claim 2 further includes: a dielectric layer disposed above the substrate; a metal contact disposed in the dielectric layer and contacting the doped region; and A metal layer is disposed above the dielectric layer and contacts the metal contact. The high-voltage semiconductor device of claim 2, wherein a ratio of a depth of the doping region to a depth of the third high-pressure well region is in the range of 0.006 to 0.01. A high-voltage semiconductor device, including: a substrate; a high-voltage well region disposed above the substrate and having a first conductive type dopant; a first annular high-pressure well region disposed surrounding and contacting the above-mentioned high-pressure well region, And there is a second conductivity type dopant that is opposite to the above-mentioned first conductivity type dopant; a second annular high-voltage well region is arranged around the above-mentioned first annular high-pressure well region and has the above-mentioned first conductivity type dopant object; a drain region, disposed in the above-mentioned high-pressure well region; an annular gate structure, disposed above the above-mentioned high-pressure well region, and surrounding the above-mentioned drain region; an annular source region, disposed in the above-mentioned first annular high-voltage well region in the well region and surrounding the annular gate structure; and an annular doping region disposed in the second annular high-voltage well region and having the first conductive type dopant. The high-voltage semiconductor device of claim 6 further includes: an annular buried layer disposed under the first annular high-pressure well region and the second annular high-pressure well region and having the first conductive type dopant. The high-voltage semiconductor device of claim 7, wherein an inner boundary of the annular buried layer is separated from an outer boundary of the high-pressure well region by a predetermined distance. The high-voltage semiconductor device of claim 7 further includes: a dielectric layer disposed above the substrate; a metal contact disposed in the dielectric layer and contacting the annular doped region; and a metal layer disposed above the dielectric layer and in contact with the metal contacts. The high-voltage semiconductor device of claim 6, wherein a ratio of a depth of the annular doped region to a depth of the second annular high-pressure well region is in the range of 0.006 to 0.01.

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