TWI748729B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a substrate, an epitaxial layer, a buried layer, a source region and a drain region, a drift region, a gate structure, a first isolation structure, and a high-voltage well region. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type and is disposed on the substrate. The buried layer has the second conductivity type and is disposed in the substrate. The source region and the drain region have the first conductivity type and are disposed in the epitaxial layer, respectively. The drift region has the first conductivity type and is disposed in the epitaxial layer, is located between the source region and the drain region, and is electrically connected to the drain region. The gate structure is disposed on the source region and the drift region. The first isolation structure is disposed between the drift region and the drain region. The high-voltage well region has the first conductivity type, is disposed in the epitaxial layer, and is in contact with the buried layer and the first isolation structure.

Description

Semiconductor structure

This disclosure relates to semiconductor structures, and in particular, to semiconductor structures that can reduce substrate leakage current.

Generally speaking, high voltage integrated circuits (HVIC) can be used to drive high current components such as metal oxide half field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT). Because HVIC has the advantages of being cost-effective and easily compatible with other processes, HVIC is often used in power control systems.

The HVIC includes a high side part and a low side part, and a level shifter is used to connect the high side part and the low side part. Among them, the raising type level shifter such as the N-type level shifter is used to level up (level up), that is, from the low end part to the high end part, and the lowering type such as the P-type level shifter The level shifter is used to level down, that is, from the high-end part to the low-end part. However, since the P-type level shifter needs to operate in a high voltage or even an ultra-high voltage (UHV) environment, it is necessary to maintain a high breakdown voltage while avoiding substrate leakage current (substrate leakage). current). In addition, because the P-type level shifter can sense the abnormal signal of the high-end part and transmit the abnormal signal to the signal detection circuit, if there is a substrate leakage current, it will affect the sensing of the P-type level shifter ability.

Therefore, although existing semiconductor structures have gradually met their intended use, they have not yet fully met the requirements in all aspects. Therefore, there are still some problems to be overcome regarding the semiconductor structure that can be used as a level shifter after further processing.

In view of the above problems, the present disclosure forms a PNPNP structure that includes two PNP structures connected in series and is difficult to conduct by arranging a high-voltage well region and a buried layer in the epitaxial layer, and connects the drift region and the drift region by providing a conductive layer. The drain region makes the semiconductor structure conductive to avoid the generation of substrate leakage current in the semiconductor structure, thereby obtaining a semiconductor structure with better electrical characteristics.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, an epitaxial layer, a buried layer, a source region and a drain region, a drift region, a gate structure, a first isolation structure, and a high-voltage well region. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type and is disposed on the substrate. The buried layer has the second conductivity type and is disposed on the substrate. The source region and the drain region respectively have the first conductivity type and are respectively disposed in the epitaxial layer. The drift region has the first conductivity type and is disposed in the epitaxial layer, is located between the source region and the drain region, and is electrically connected to the drain region. The gate structure is arranged on the source region and the drift region. The first isolation structure is disposed between the drift region and the drain region. The high-voltage well region has the first conductivity type, is disposed in the epitaxial layer, and is in contact with the buried layer and the first isolation structure.

The semiconductor structure of the present disclosure can be applied to various types of semiconductor devices. In order to make the features and advantages of the present disclosure more comprehensible, preferred embodiments are listed below in conjunction with the accompanying drawings, which are described in detail as follows.

The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the disclosure. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present disclosure may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, rather than to indicate the relationship between the different embodiments and/or forms discussed.

In the different drawings and illustrated embodiments, similar component symbols are used to designate similar components. It can be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or deleted for other embodiments of the method.

FIGS. 1-11 are schematic cross-sectional diagrams illustrating the formation of the semiconductor structure 1 at various stages according to some embodiments of the present disclosure.

Referring to FIG. 1, a substrate 100 is provided, and a buried layer is disposed in the substrate 100. The substrate 100 may be a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. The substrate 100 may be a wafer, such as a silicon wafer. Generally speaking, an insulating overlying semiconductor substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer or similar materials, which provide an insulating layer on a silicon or glass substrate. Other types of substrates include, for example, multi-layer or gradient substrates.

The substrate 100 may be an element semiconductor, which includes silicon and germanium; the substrate 100 may also be a compound semiconductor, which includes: for example, silicon carbide, gallium arsenide, and phosphorous. Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide, but the present disclosure is not limited thereto; the substrate 100 may also be an alloy semiconductor, which includes : For example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or any combination thereof, but the present disclosure is not limited thereto; or the substrate 100 may be any other suitable material.

In some embodiments, the buried layer 110 may be formed by, for example, an ion implantation process, a diffusion process, a drive in process, or any other suitable process. In the substrate 100, but the present disclosure is not limited to this. In addition, the implanted dopants can be activated by a rapid thermal annealing (RTA) process. In some embodiments, the dopant may be a P-type dopant such as boron (B) or an N-type dopant such as phosphorus (P), and the corresponding dopant may be selected according to the conductivity type.

In some embodiments, the substrate 100 has a first conductivity type, and the buried layer 110 has a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 is P type, the second conductivity type of the buried layer 110 is N type; on the contrary, if the first conductivity type of the substrate 100 is N type, the second conductivity type of the buried layer 110 is P type. In some embodiments, the first conductivity type and the second conductivity type can be adjusted according to requirements, and at the same time, the doping concentration, doping depth, and size of the doped region can also be adjusted according to requirements. In some embodiments, the semiconductor structure of the present disclosure can be subsequently processed into a P-type level shifter. In other words, it can have a P-type MOSFET (P-type MOSFET). ) Structure, therefore, the following description will be given by assuming that the first conductivity type of the substrate 100 is P-type, and the second conductivity type of the buried layer 110 is N-type.

Referring to FIG. 2, an epitaxial layer 200 is provided on the substrate 100. In some embodiments, the epitaxial layer 200 is disposed on the substrate 100 and the buried layer 110. The epitaxial layer 200 may cover the upper surface of the buried layer 110.

The epitaxial layer 200 may include silicon, germanium, silicon and germanium, III-V compounds, or a combination of the foregoing. The epitaxial layer 200 may be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic chemical vapor deposition (MOCVD), and metal-organic chemical vapor deposition (MOCVD). phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RPCVD), molecular beam epitaxy ( molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl -VPE) or similar methods.

In some embodiments, after the step of forming the epitaxial layer 200 on the substrate 100, the aforementioned diffusion process, heat sink process, and/or rapid thermal annealing process may be performed to make the buried layer disposed in the substrate 100 110 is further disposed in the epitaxial layer 200. That is, the doping profile of the buried layer 110 is changed so that a part of the buried layer 110 is disposed in the substrate 100, and another part of the buried layer 110 is disposed in the epitaxial layer 200, that is, the buried layer 110 It can expand along both sides of the interface between the substrate 100 and the epitaxial layer 200. In some embodiments, the epitaxial layer 200 may have a second conductivity type different from the first conductivity type. In some embodiments, the epitaxial layer 200 may be an N-type epitaxial layer; or the epitaxial layer 200 may be used as a high-voltage N-type well region for carrier transmission. In some embodiments, since the substrate 100 is P-type; the buried layer 110 is N-type; and the epitaxial layer 200 is N-type, the buried layer 110 can recombine electrons and holes, and It is used to block the movement of holes of the substrate 100 located under the buried layer 110.

Referring to FIG. 3, a high-pressure well region 350 is provided in the epitaxial layer 200 so that the high-pressure well region 350 is in contact with the buried layer 110. In some embodiments, since the high-pressure well region 350 is disposed in the epitaxial layer 200, the high-pressure well region 350 allows the epitaxial layer 200 to include the first epitaxial region 210 and the second epitaxial region 220 that are separated from each other. In some embodiments, the high-pressure well region 350 can be formed by performing the aforementioned ion implantation, diffusion process, thermal trapping process, and/or rapid thermal annealing process. In some embodiments, the high-voltage well region 350 has the first conductivity type. In some embodiments, the high-pressure well region 350 is a P-type high-pressure well region.

Referring to FIG. 4, the active area of the semiconductor structure is defined on the substrate 100, and the isolation structure is arranged according to the active area. In some embodiments, the isolation structure may be disposed on the epitaxial layer 200. In some embodiments, the isolation structure may be an oxide, nitride, oxynitride, a combination thereof, or any other suitable isolation material. For example, the isolation structure may be field oxide. In some embodiments, the isolation structure may include silicon oxide. In some embodiments, the isolation structure may be formed by local oxidation of silicon (LOCOS) formed by thermal oxidation. In some embodiments, the isolation structure may include a first isolation structure 410, a second isolation structure 420, a third isolation structure 430, a fourth isolation structure 440, and a fifth isolation structure 450.

In some embodiments, the first isolation structure 410 may be disposed between the drift region formed subsequently and the drain region formed subsequently. In some embodiments, the first isolation structure 410 is disposed on the high-pressure well region 350, and the first isolation structure 410 is in contact with the high-pressure well region 350. That is, the high-pressure well region 350 is in contact with the buried layer 110 and the first isolation structure 410 at the same time, so the high-pressure well region 350 separates the epitaxial layer 200 into the first epitaxial region 210 and the second epitaxial region 220. In some embodiments, the first isolation structure 410 covers the upper surface of the high pressure well region 350. In some embodiments, a portion of the buried layer 110 overlaps the high pressure well region 350.

In some embodiments, the second isolation structure 420 may be disposed between the gate structure formed subsequently and the drift region formed subsequently. In some embodiments, the third isolation structure 430 may be disposed between the gate structure formed subsequently and the source region formed subsequently. In some embodiments, the fourth isolation structure 440 may be disposed between the subsequently formed base region and the subsequently formed source region. In some embodiments, the fifth isolation structure 450 may be disposed between the subsequently formed base region and the boundary of the semiconductor structure. In other words, since the isolation structure can provide an insulating effect, the isolation structure can be formed at any other suitable position.

Referring to FIG. 5, the gate structure 500 is disposed on the epitaxial layer 200, and the gate structure 500 is disposed between the second isolation structure 420 and the third isolation structure 430. The gate structure 500 includes a gate conductive layer 510 and a gate dielectric layer 520 on which the gate conductive layer 510 is disposed. In some embodiments, the gate dielectric layer 520 is in contact with the epitaxial layer 200, and the gate dielectric layer 520 covers the upper surface of the epitaxial layer 200 between the second isolation structure 420 and the third isolation structure 430 . In some embodiments, a part of the gate structure 500 overlaps with the second isolation structure 420, and a part of the gate structure 500 overlaps with the third isolation structure 430.

In some embodiments, a gate dielectric material layer for forming the gate dielectric layer 520 may be deposited first, and then a conductive material layer for forming the gate conductive layer 510 may be deposited on the aforementioned gate dielectric material layer. In some embodiments, the material of the gate dielectric material layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, combinations thereof, or other suitable dielectric materials. Material. In some embodiments, the aforementioned gate dielectric material layer may be formed by a chemical vapor deposition (CVD) process or a spin coating process. In some embodiments, the aforementioned CVD may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), or rapid temperature chemical vapor deposition (LPCVD). Rapid thermal chemical vapor deposition (RTCVD), PECVD, atomic layer deposition (ALD) or other suitable CVD processes. In some embodiments, the material of the aforementioned conductive material layer may be amorphous silicon, polysilicon, one or more metals, metal nitrides, conductive metal oxides, combinations thereof, or other suitable conductive materials. In some embodiments, the aforementioned conductive material layer can be formed by CVD, sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods.

Then, the gate dielectric material layer and the conductive material layer are respectively patterned by a lithography process and an etching process to form a gate structure 500 including a gate dielectric layer 520 and a gate conductive layer 510. In some embodiments, the aforementioned etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a part of the structure to be removed. In addition, the etching process can also be pure chemical etching, pure physical etching, or any combination thereof.

In some embodiments, a lightly doped drain (LDD) structure such as a lightly doped drain (LDD) structure may be further provided where the drain region and the source region formed subsequently are close to the gate structure 500, thereby Reducing the hot-carrier effect causes unnecessary conduction problems in the semiconductor structure. In some embodiments, the gate structure 500 may further include insulating spacers (spacers) disposed on both sidewalls of the gate structure 500.

Referring to FIG. 6, an insulating layer 600 is provided on the epitaxial layer 200. In some embodiments, an insulating layer 600 is provided on the epitaxial layer 200, the gate structure 500, and the isolation structure. In some embodiments, the insulating layer 600 includes oxide, nitride, a combination thereof, or any other suitable insulating material. In some embodiments, the insulating layer 600 may include silicon oxide, silicon nitride, silicon oxynitride, an oxide formed using tetraethoxysilane (TEOS) as a precursor, and silane (SiH4) as a precursor. An oxide formed from a precursor. In some embodiments, the insulating layer 600 may be formed by the aforementioned deposition process. In some embodiments, the insulating layer 600 may be silicon oxide formed by a thermal oxidation process using TEOS as a precursor, so the insulating layer 600 may be a dense silicon oxide layer.

Referring to FIG. 7, the conductive layer 700 is disposed on the insulating layer 600, and the conductive layer 700 is disposed on the first isolation structure 410. In some embodiments, the conductive layer 700 may be electrically connected to the drift region and the drain region formed subsequently. In some embodiments, an insulating layer 600 is provided between the conductive layer 700 and the gate structure 500 to electrically isolate the conductive layer 700 from the gate structure 500. In some embodiments, the conductive layer 700 may include the aforementioned conductive materials. In some embodiments, the conductive layer 700 may include a second polysilicon. In some embodiments, the second polysilicon may be P-type polysilicon.

It should be particularly noted that, in some embodiments, when the gate conductive layer 510 in the gate structure 500 includes a first polysilicon; the insulating layer 600 includes an oxide such as silicon oxide; and the conductive layer 700 includes a second polysilicon In the case of crystalline silicon, a polysilicon-oxide-polysilicon (POP) structure can be formed. In some embodiments, the resistance of the second polysilicon included in the conductive layer 700 is greater than the resistance of the first polysilicon included in the gate structure 500. For example, in some embodiments, the resistance of the second polysilicon is 5 to 250 times the resistance of the first polysilicon. Since the first polysilicon is used to form the gate conductive layer 510, the resistance of the first polysilicon needs to be low to reduce the on-resistance. At the same time, since the second polysilicon is used to form the conductive layer 700, the second polysilicon with a higher resistance value can enable the overall semiconductor structure to operate under a high voltage state. The detailed arrangement of the conductive layer 700 will be described later.

Referring to FIG. 8, a source region 310, a drift region 320, a drain region 330 and a base region 340 are disposed in the epitaxial layer 200. In some embodiments, the source region 310 may be formed by, for example, an ion implantation process, a diffusion process, a drive in process, or any other suitable process. The drift region 320, the drain region 330 and/or the base region 340 are in the epitaxial layer 200.

In some embodiments, the source region 310 and the drain region 330 respectively have the first conductivity type. In some embodiments, the source region 310 and the drain region 330 may be P-type doped regions, for example, P-type heavily doped (P ⁺ ) regions. In some embodiments, the source region 310 may have a stepwise increase in doping concentration from the outside to the inside, that is, compared to the source region 310 farther from the contact plug formed later, it is closer to the contact plug formed later. The source region 310 has a larger doping concentration.

In some embodiments, the aforementioned buried layer 110 extends from the source region 310 toward the drain region 330. In some embodiments, the aforementioned buried layer 110 partially overlaps with the first isolation structure 410 between the drift region 320 and the drain region 330.

Following the above, in some embodiments, the drift region 320 may have the first conductivity type. In some embodiments, the drift region 320 may be a P-type doped region. In some embodiments, the drift region 320 may be disposed between the source region 310 and the drain region 330. For example, the distance between the drift region 320 and the source region 310 may be the same as or different from the distance between the drift region 320 and the drain region 330. For example, the distance between the drift region 320 and the source region 310 may be smaller than the distance between the drift region 320 and the drain region 330. In some embodiments, the drift region 320 is electrically connected to the drain region 330, so that the semiconductor structure of some embodiments of the disclosure can be turned on. In some embodiments, the source region 310 and the drift region 320 are disposed under the aforementioned gate structure 500, and the source region 310 and the drift region 320 are respectively disposed on both sides of the gate structure 500. In some embodiments, the doping concentration of the drift region 320 may be lower than the doping concentration of the source region 310 and the drain region 330.

In some embodiments, the base region 340 has the second conductivity type. In some embodiments, the base region 340 may be an N-type doped region, for example, an N-type heavily doped (N ⁺ ) region. In some embodiments, the source region 310 is disposed between the drift region 320 and the base region 340.

Referring to FIG. 9, an interlayer dielectric (interlayer dielectric) layer 800 is provided on the insulating layer 600 and the conductive layer 700. In some embodiments, the interlayer dielectric layer 800 may include, or may be, silicon oxide, silicon nitride, silicon oxynitride, TEOS derivatives, SiH ₄ derivatives, phosphosilicate glass (PSG), borophosphosilicate Borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon (fluorinated silica) carbon), parylene, bis-benzocyclobutenes (BCB), polyimide, low-k materials, combinations thereof, or any other suitable , But this disclosure is not limited to this. In some embodiments, the interlayer dielectric layer 800 and the gate dielectric layer 520 can be formed by the same or different processes.

Referring to Fig. 10, a plurality of via holes CT are formed. In some embodiments, some of the plurality of vias CT may penetrate through the interlayer dielectric layer 800 and the insulating layer 600, and expose the source region 310, the drift region 320, the drain region 330, and the base region 340, respectively. And a part of the upper surface of the gate structure 500. Other via holes CT of the plurality of via holes CT may penetrate the interlayer dielectric layer 800 and expose a part of the upper surface of the conductive layer 700.

Referring to FIG. 11, a conductive material is filled in the via hole CT to form a contact plug, and a metal layer 900 is formed on the interlayer dielectric layer 800 and the contact plug, so that the metal layer 900 and the contact plug are in contact with each other. In some embodiments, the via material may include a metal material, a conductive material, a combination thereof, or any other suitable materials. In some embodiments, the method of filling the via material includes: CVD, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process, but the disclosure is not limited thereto. In addition, after filling the via material, a chemical mechanical polishing (CMP) process can be further performed.

In some embodiments, the contact plug includes a first contact plug 810, a second contact plug 820, a third contact plug 830, a fourth contact plug 840, and a fifth contact plug 850. In some embodiments, the first contact plug 810 may penetrate the interlayer dielectric layer 800 and the insulating layer 600, and may electrically connect the metal layer 900 and the drift region 320. In some embodiments, the second contact plug 820 may penetrate the interlayer dielectric layer 800 and electrically connect the metal layer 900 and the conductive layer 700. In some embodiments, the second contact plug 820 may be provided as two. In some embodiments, the third contact plug 830 penetrates the interlayer dielectric layer 800 and the insulating layer 600, and electrically connects the metal layer 900 and the drain region 330, so the third contact plug 830 and the third contact plug The metal layer 900 connected to 830 can collectively serve as a drain electrode. In some embodiments, the first contact plug 810, the second contact plug 820, the third contact plug 830, the conductive layer 700, and the metal layer 900 jointly form a carrier channel, so that the semiconductor structure 1 of the present disclosure is turned on.

In some embodiments, the fourth contact plug 840 can penetrate the interlayer dielectric layer 800 and the insulating layer 600, and electrically connect the metal layer 900 and the gate structure 500, so the gate conductive layer 510 and the fourth contact plug 840 And the metal layer 900 connected to the fourth contact plug 840 can collectively serve as a gate electrode. In some embodiments, the fifth contact plug 850 may penetrate the interlayer dielectric layer 800 and the insulating layer 600, and electrically connect the metal layer 900 and the source region 310, so the fifth contact plug 850 and the fifth contact plug The metal layer 900 connected to the plug 850 can collectively serve as a source electrode. In addition, the fifth contact plug 850 can also electrically connect the metal layer 900 and the base region 340, so that the fifth contact plug 850 and the metal layer 900 connected to the fifth contact plug 850 can collectively serve as a base electrode.

In some embodiments, the aforementioned semiconductor structure 1 of the present disclosure can be used as a P-type level shifter in a high voltage integrated circuit (HVIC), that is, used as a PMOS.

It should be particularly noted that, according to some embodiments of the present disclosure, in the aforementioned semiconductor structure 1, since the high-voltage well region 350 is in contact with the first isolation structure 410 and the buried layer 110, the epitaxial layer 200 includes the high-voltage well region 350. The first epitaxial region 210 on one side of the high-pressure well region 350 and the second epitaxial region 220 on the other side of the high-pressure well region 350. In some embodiments, the area of the epitaxial layer 200 with the drift region 320 is the first epitaxial region 210, and the area of the epitaxial layer 200 with the drain region 330 is the second epitaxial region.区220. That is, the epitaxial layer 200 located between the high-pressure well region 350 and the drift region 320 is the first epitaxial layer 210, and the epitaxial layer 200 located between the high-pressure well region 350 and the drain region 330 is the second epitaxial layer Layer 200. Among them, the conductivity type is selected according to some of the foregoing embodiments. Under operating conditions such as applying voltage and/or bias, the drift region 320 has a P-type conductivity type, and the first epitaxial region 210 has an N-type conductivity type. The high-voltage well region 350 with P-type conductivity, the second epitaxial region 220 with N-type conductivity, and the substrate 100 with P-type conductivity are all in a depleted state. Since the drift region 320, the first epitaxial region 210, the high-voltage well region 350, the second epitaxial region 220, and the substrate 100 have a PNPNP structure, they form a structure similar to two PNP bipolar junction transistors (BJT). ) Series structure. Therefore, the two PNP-type BJTs in the aforementioned PNPNP structure are not easily turned on at the same time. Therefore, when the entire PNPNP structure is in a depleted state, it can effectively prevent and/or reduce the generation of substrate leakage current of the semiconductor structure of some embodiments of the disclosure. At the same time, the charge balance can be further improved, and a semiconductor structure with better electrical characteristics can be obtained.

Refer to FIG. 12, which is a schematic cross-sectional view of the semiconductor structure 2 according to some embodiments of the disclosure. For ease of description, the same or similar elements will not be repeated. As shown in FIG. 12, the high-pressure well region 350 may extend to a part of the substrate 100. The source region 310 may have a first sub-source region 311, a second sub-source region 312, and a third sub-source region 313. The doping concentration of the first sub-source region 311 is higher than the doping concentration of the second sub-source region 312, and the doping concentration of the second sub-source region 312 is higher than that of the third sub-source region 313. Miscellaneous concentration.

Refer to FIG. 13, which is a block diagram of the high-voltage integrated circuit 3 of some embodiments of the disclosure. The high-voltage integrated circuit 3 includes a high-end part and a low-end part, and the interface between the high-end part and the low-end part relies on a level shifter. As shown in Figure 13, between the high-voltage terminal VH and the ground terminal, there is a transistor T1 that controls a high side gate driver 34, a load 36 such as a motor, a fan, etc., and a low-side gate driver ( Low side gate driver) 35 transistor T2. The raising-type level shifter 31 raises the level from the low-end part to the high-end part, and the lowering-type level shifter 32 lowers the level from the high-end part to the low-end part. At the same time, the reduced level shifter 32 is also connected to the logic control circuit 33 to use the logic control circuit 33 to detect signals. In some embodiments, the semiconductor structures 1 and 2 of the present disclosure are used as the reduced level shifter 32.

Refer to FIG. 14, which is a schematic top view of the semiconductor structure 1 shown in FIG. 11 disposed in the high-voltage integrated circuit shown in FIG. 13. In some embodiments, the schematic cross-sectional view of the semiconductor structure 1 shown in FIG. 11 is a schematic cross-sectional view taken along the line AA' in the circuit layout 4 shown in FIG. 14. Similarly, in some embodiments, the semiconductor structure 2 shown in FIG. 12 may also be disposed in the high-voltage integrated circuit shown in FIG. 13. In some embodiments, the circuit layout 4 includes a high-end part 37, a low-end part 39, and an isolation part 38 that electrically isolates the high-end part 37 and the low-end part 39. In some embodiments, the semiconductor structure 1 or 2 of the present disclosure can be disposed on the isolation portion 38 to save the size of the overall circuit layout 4.

It should be particularly noted that, as shown in FIG. 14, the conductive layer 700 of the semiconductor structure 1 of the present disclosure can be arranged along the shape of the isolation portion 38. For example, if the isolation portion 38 has a ring shape or a racetrack shape, the conductive layer 700 can be arranged around the isolation portion 38. For example, the conductive layer 700 may have a spiral shape. In some embodiments, when viewed in a top view as shown in FIG. 14, the conductive layer 700 may extend between the drift region 320 and the drain region 330 in a direction parallel to the drift region 320 and/or the drain region 330 . In some embodiments, the conductive layer 700 may even extend beyond the boundary of the semiconductor structure 1 and is disposed on the isolation portion 38. With Figures 11 and 14, according to the shape of the conductive layer 700, carriers can travel from the drift region 320 to the first contact plug 810, the metal layer 900, the second contact plug 820 near the drift region 320, and the conductive layer 700 , The second contact plug 820, the metal layer 900, the third contact plug 830 and the drain region 330 far away from the drift region 320 are transmitted sequentially, thereby turning on the semiconductor structure 1.

It should be particularly noted that in some of the foregoing embodiments, since the conductive layer 700 includes the second polysilicon with a higher resistance value, the effect of withstanding high voltage operation can be achieved. Further, because the conductive layer 700 It can be arranged along the shape of the isolation portion 38, so the length of the conductive layer 700 can be controlled by controlling the number of turns of the conductive layer 700 to adjust the overall resistance of the conductive layer 700. For example, as the number of turns around the isolation portion 38 increases, the semiconductor structure 1 of some embodiments of the present disclosure can withstand operation under a higher voltage state. For example, the conductive layer 700 can go around 1 turn, 2 turns, 3 turns, 4 turns, 5 turns, or any number of turns that can make the conductive layer 700 reach the desired resistance value. In addition, according to some embodiments of the present disclosure, the conductive layer 700 is disposed on the insulating layer 600. Therefore, the insulating layer 600, the first isolation structure 410, and the epitaxial layer 200 are provided between the conductive layer 700 and the substrate 100, so that the conductive layer can be reduced. 700 affects the electric field of the substrate 100 under the conductive layer 700.

Referring to FIG. 15, it is a schematic top view of the semiconductor structure 1 shown in FIG. 11 disposed in the high-voltage integrated circuit shown in FIG. 13. Following the above, if the semiconductor structure 1 in some embodiments of the present disclosure does not need to be operated under a very high voltage state, the conductive layer 700 can be disposed in the drift region 320 and the drain region within the boundary of the semiconductor structure 1 Between 330. For example, when viewed from a top view, the conductive layer 700 may have a saw-tooth shape.

In summary, according to some embodiments of the present disclosure, the semiconductor structure separates the epitaxial layer into the first epitaxial region and the second epitaxial layer by arranging high-voltage well regions with different conductivity types and buried layers in the epitaxial layer. Two epitaxial regions are formed to form a PNPNP structure to avoid reducing substrate leakage current. In addition, the semiconductor structure is provided with a conductive layer and a contact plug matched with the conductive layer to provide a path for carrier conduction, so that the semiconductor structure can operate effectively. Therefore, according to some embodiments of the present disclosure, it is possible to provide low-cost, high-process margin, high-reliability, low-cost, high-process margin, and high-reliability, without using a thicker epitaxial layer, and without accurately controlling the doping concentration of the drift region. Semiconductor structure with high breakdown voltage and high span voltage amplitude.

Although the embodiments of the present disclosure and their advantages have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the manufacturing process, machinery, manufacturing, material composition, device, method, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can implement some implementations from this disclosure. The disclosed contents of the examples understand the current or future developed processes, machines, manufacturing, material composition, devices, methods, and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. The present disclosure uses some embodiments. Therefore, the protection scope of the present disclosure includes the above-mentioned manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps. In addition, the scope of each patent application constitutes an individual embodiment, and the protection scope of this disclosure also includes the scope of each patent application and the combination of the embodiments.

The above summarizes several embodiments so that those with ordinary knowledge in the technical field of the present disclosure can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field of the present disclosure should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present disclosure to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of this disclosure, and they can, without violating the spirit and scope of this disclosure, Make all kinds of changes, substitutions and replacements.

1,2: Semiconductor structure 3: High voltage integrated circuit 4,5: Circuit layout 31: Lifting type level shifter 32: Reduced level shifter 33: Logic control circuit 34: High-end gate driver 35: Low-end gate driver 36: Load 37: High-end part 38: Isolation part 39: Low-end part 100: substrate 110: Buried layer 200: epitaxial layer 210: The first epitaxial zone 220: second epitaxial zone 310: source region 311: The first sub-source region 312: second sub source region 313: Third sub-source region 320: drift zone 330: Drain Area 340: Base Area 350: high pressure well area 410: The first isolation structure 420: second isolation structure 430: third isolation structure 440: Fourth isolation structure 450: Fifth isolation structure 500: Gate structure 510: gate conductive layer 520: gate dielectric layer 600: insulating layer 700: conductive layer 800: Interlayer dielectric layer 810: first contact plug 820: second contact plug 830: third contact plug 840: fourth contact plug 850: Fifth contact plug 900: Metal layer CT: Via hole T1, T2: Transistor VH: High voltage side

With the following detailed description and accompanying drawings, we can better understand the viewpoints of the embodiments of the present disclosure. It is worth noting that, according to industry standard conventions, some features may not be drawn to scale. In fact, in order to be able to discuss clearly, the size of different components may be increased or decreased. 1 to 11 are schematic cross-sectional views of semiconductor structures formed at various stages according to some embodiments of the present disclosure; FIG. 12 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the disclosure; FIG. 13 is a block diagram of a high voltage integrated circuit (HVIC) according to some embodiments of the present disclosure; and FIG. 14 and FIG. 15 are schematic top views respectively showing the semiconductor structure disposed in the high-voltage integrated circuit according to some embodiments of the present disclosure.

1: Semiconductor structure

100: substrate

110: Buried layer

200: epitaxial layer

210: The first epitaxial zone

220: second epitaxial zone

310: source region

320: drift zone

330: Drain Area

340: Base Area

350: high pressure well area

410: The first isolation structure

420: second isolation structure

430: third isolation structure

440: Fourth isolation structure

450: Fifth isolation structure

500: Gate structure

510: gate conductive layer

520: gate dielectric layer

600: insulating layer

700: conductive layer

800: Interlayer dielectric layer

810: first contact plug

820: second contact plug

830: third contact plug

840: fourth contact plug

850: Fifth contact plug

900: Metal layer

Claims (12)

A semiconductor structure comprising: A substrate having a first conductivity type; An epitaxial layer having a second conductivity type different from the first conductivity type and disposed on the substrate; A buried layer having the second conductivity type and disposed in the substrate; A source region and a drain region respectively have the first conductivity type and are respectively disposed in the epitaxial layer; A drift region having the first conductivity type and disposed in the epitaxial layer, located between the source region and the drain region, and the drift region and the drain region are electrically connected; A gate structure arranged on the source region and the drift region; A first isolation structure disposed between the drift region and the drain region; and A high-voltage well region has the first conductivity type, is disposed in the epitaxial layer, and is in contact with the buried layer and the first isolation structure. The semiconductor structure of claim 1, wherein the buried layer extends from the source region toward the drain region, and the buried layer overlaps the first isolation structure. The semiconductor structure of claim 1, wherein the first isolation structure covers the upper surface of the high-voltage well region. Such as the semiconductor structure of claim 1, which further includes: An insulating layer disposed on the epitaxial layer; and A conductive layer is disposed on the insulating layer and on the first isolation structure, and the conductive layer is electrically connected to the drift region and the drain region. The semiconductor structure of claim 4, wherein the gate structure includes a gate conductive layer and a gate dielectric layer, the gate conductive layer includes a first polysilicon, and the conductive layer includes a second polysilicon Silicon, the resistance of the second polysilicon is greater than the resistance of the first polysilicon. Such as the semiconductor structure of claim 4, which further includes: An interlayer dielectric layer is arranged on the conductive layer; A metal layer disposed on the interlayer dielectric layer; A first contact plug penetrating the interlayer dielectric layer and the insulating layer, and electrically connecting the metal layer and the drift region; A second contact plug penetrates the interlayer dielectric layer and electrically connects the metal layer and the conductive layer; and A third contact plug penetrates the interlayer dielectric layer and the insulating layer, and electrically connects the metal layer and the drain region. Such as the semiconductor structure of claim 6, which further includes: A fourth contact plug penetrating the interlayer dielectric layer and the insulating layer, and electrically connecting the metal layer and the gate structure; and A fifth contact plug penetrates the interlayer dielectric layer and the insulating layer, and electrically connects the metal layer and the source region. The semiconductor structure of claim 1, wherein the epitaxial layer includes a first epitaxial region and a second epitaxial region, the drift region and the high-voltage well region are separated from each other by the first epitaxial region, and the high-voltage The well region and the drain region are separated from each other by the second epitaxial region, and the drift region, the first epitaxial region, the high-voltage well region, the second epitaxial region, and the substrate are subject to voltage and/ Or the whole is in a depleted state during bias operation. The semiconductor structure of claim 8, wherein the first conductivity type of the drift region, the high-voltage well region, and the substrate is P-type, and the first epitaxial region and the second epitaxial region have the second The conductivity type is N-type, and the drift region, the first epitaxial region, the high-voltage well region, the second epitaxial region, and the substrate have a PNPNP structure. Such as the semiconductor structure of claim 1, which further includes: A second isolation structure disposed between the gate structure and the drift region; and A third isolation structure is arranged between the gate structure and the source region. Such as the semiconductor structure of claim 1, which further includes: A base region having the second conductivity type, disposed on the epitaxial layer, and the source region is disposed between the base region and the drift region; and A fourth isolation structure is arranged on the epitaxial layer and between the base region and the source region. The semiconductor structure of claim 1, wherein a part of the buried layer is disposed in the substrate, and another part of the buried layer is disposed in the epitaxial layer.

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