TWI871159B - Semiconductore device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first source/drain electrode, a first isolation structure, a second source/drain electrode, a first buffer layer, a semiconductor structure, a gate dielectric layer and a gate electrode. The first isolation structure is located on the first source/drain electrode and has a first through hole overlapping with the first source/drain electrode. The second source/drain electrode is located on the top surface of the first isolation structure. The first buffer layer covers a sidewall of the first through hole and continuously extends from the second source/drain electrode to the first source/drain electrode. The semiconductor structure is filled in the first through hole and extending from the second source/drain electrode along the first buffer layer to the first source/drain electrode. The gate dielectric layer is located on the semiconductor structure. The gate electrode is located on the gate dielectric layer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

At present, general thin film transistors usually use amorphous silicon semiconductors as channel materials. Due to the simple process and low cost of amorphous silicon semiconductors, they are widely used in various thin film transistors. However, with the continuous advancement of thin film transistor process technology, the size of thin film transistors has also been shrinking. In order to reduce the size of thin film transistors, many manufacturers are committed to developing semiconductor materials with higher carrier mobility, including metal oxide semiconductor materials. Metal oxide semiconductor materials have excellent electron mobility and can be used in small-sized thin film transistors.

The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device has a stable operating current.

At least one embodiment of the present invention provides a semiconductor device, which includes a first source/drain, a first isolation structure, a second source/drain, a first buffer layer, a semiconductor structure, a gate dielectric layer, and a gate. The first isolation structure is located on the first source/drain and has a first through hole overlapping the first source/drain. The second source/drain is located on the top surface of the first isolation structure. The first buffer layer covers the sidewall of the first through hole and extends continuously from the second source/drain to the first source/drain. The semiconductor structure is filled in the first through hole and extends from the second source/drain along the first buffer layer to the first source/drain. The gate dielectric layer is located on the semiconductor structure. The gate is located on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a first isolation structure above a first source/drain, wherein the first isolation structure has a first through hole overlapping the first source/drain; forming a second source/drain above the first source/drain; and forming a buffer material layer to cover a top surface of the second source/drain, a sidewall of the first through hole, and a top surface of the first source/drain. Patterning the buffer material layer to form a first buffer layer exposing the top surface of the first source/drain and the top surface of the second source/drain, wherein the first buffer layer covers the sidewall of the first through hole and extends continuously from the second source/drain to the first source/drain. Forming a semiconductor structure in the first through hole, and the semiconductor structure extends from the second source/drain along the first buffer layer to the first source/drain. Forming a gate dielectric layer in the first through hole. Forming a gate on the gate dielectric layer.

10,10A,10B,10C:Semiconductor devices

100: Substrate

210: First source/drain

210t, 220t, 230t: Top surface

220: Second source/drain

220s,S1,S2: side wall

220’, 230’: conductive material layer

230: Third source/drain

310,310A: First isolation structure

310’, 310A’, 330’: Isolation material layer

320: Gate dielectric layer

400,410,400C: First buffer layer

400’, 400C’: Buffer material layer

402: Part 1

404: Part 2

420: Second buffer layer

500,500A,500C:Semiconductor structure

500A’,500C’: semiconductor interposer structure

510: The first heavily doped area

520: Second mixed area

530: First channel area

540: First lightly mixed area

550: Second channel area

560: Second lightly mixed area

570: The third mixed area

600: Gate

DE: Dry etching process

H1: First through hole

H2: Second through hole

HP: Hydrogen doping process

ND: Normal direction

PR1,PR2: Patterned photoresist layer

t1,t2: thickness

FIG1A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG1B is a schematic cross-sectional view along line A-A’ of FIG1A .

Figures 2A to 2H are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of Figures 1A and 1B.

FIG3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 4A to 4F are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of Figure 3.

FIG5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG6A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG6B is a schematic cross-sectional view along line A-A’ of FIG6A .

Figures 7A to 7G are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of Figures 6A and 6B.

FIG1A is a schematic top view of a semiconductor device 10 according to an embodiment of the present invention. FIG1B is a schematic cross-sectional view along line A-A' of FIG1A. Referring to FIG1A and FIG1B, the semiconductor device 10 includes a first source/drain 210, a first isolation structure 310, a second source/drain 220, a first buffer layer 400, a semiconductor structure 500, a gate dielectric layer 320, and a gate 600.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The first source/drain 210, the first isolation structure 310 and the second source/drain 220 are stacked in sequence above the substrate 100 along the normal direction ND of the top surface of the substrate 100. In this embodiment, by stacking the first source/drain 210, the first isolation structure 310 and the second source/drain 220 on the substrate 100, the area required for setting up the semiconductor device 10 can be effectively reduced.

The first source/drain 210 is located on the substrate 100. In this embodiment, the first source/drain 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, other buffer layers (not shown) may be additionally included between the first source/drain 210 and the substrate 100, and the aforementioned other buffer layers are used, for example, as hydrogen barrier layers and/or metal ion barrier layers.

The first isolation structure 310 is located on the top surface 210t of the first source/drain 210 and has a first through hole H1 overlapping the first source/drain 210. In this embodiment, the vertical projection of the first through hole H1 on the substrate 100 is circular, but the present invention is not limited thereto. In other embodiments, the vertical projection of the first through hole H1 on the substrate 100 is rectangular, elliptical, triangular, pentagonal, hexagonal or other geometric shapes.

In this embodiment, the first isolation structure 310 has a single-layer or multi-layer structure, and its material includes oxide (such as silicon oxide or silicon oxynitride), nitride (such as silicon nitride) or other suitable materials. In some embodiments, the thickness t1 of the first isolation structure 310 is 3000 angstroms to 6000 angstroms. In some embodiments, the first isolation structure 310 includes oxide and can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration of the semiconductor structure 500 during the manufacturing process.

The second source/drain 220 is located on the top surface of the first isolation structure 310. In this embodiment, the first source/drain 210 and the second source/drain 220 are separated from each other by the first isolation structure 310.

In some embodiments, the materials of the first source/drain 210 and the second source/drain 220 may include metals, such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or alloys of any combination of the above metals or stacked layers of the above metals and/or alloys, but the present invention is not limited thereto. The first source/drain 210 and the second source/drain 220 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties. The first source/drain 210 and the second source/drain 220 each have a single-layer structure or a multi-layer structure.

The first buffer layer 400 covers the sidewall S1 of the first through hole H1 and extends continuously from the second source/drain 220 to the first source/drain 210. In the present embodiment, the first buffer layer 400 contacts the sidewall 220s of the second source/drain 220 and extends continuously from the sidewall 220s of the second source/drain 220 to the top surface 210t of the first source/drain 210.

In some embodiments, the first buffer layer 400 covers not only the sidewall S1 of the first through hole H1, but also the outer sidewall of the first isolation structure 310. Therefore, the first isolation structure 310 is laterally surrounded by the first buffer layer 400. In some embodiments, the thickness t2 of the first buffer layer 400 on the sidewall S1 is 200 angstroms to 850 angstroms.

In some embodiments, the material of the first buffer layer 400 includes oxide (such as silicon oxide or silicon oxynitride) or other suitable materials. By providing the first buffer layer 400, the first isolation structure 310 can be prevented from being damaged during the manufacturing process, thereby making the semiconductor structure 500 formed thereon have a higher yield. For example, the first buffer layer 400 can prevent moisture from invading the first isolation structure 310 during the manufacturing process, thereby preventing the semiconductor structure 500 from being contaminated by moisture.

In some embodiments, the first buffer layer 400 includes oxide and can be used as an oxygen storage/replenishing layer, thereby adjusting the oxygen concentration in the semiconductor structure 500 during the manufacturing process. In this embodiment, the semiconductor device 10 is a thin film transistor, and the thickness t2 of the first buffer layer 400 affects the oxygen concentration of the semiconductor structure 500, thereby affecting the critical voltage of the thin film transistor.

In some embodiments, when both the first buffer layer 400 and the first isolation structure 310 include silicon oxide, the first buffer layer 400 and the first isolation structure 310 with different characteristics can be obtained by adjusting the process parameters of the first buffer layer 400 and the first isolation structure 310. For example, both the first buffer layer 400 and the first isolation structure 310 are formed by a chemical vapor deposition process, and the raw materials both include silane ( _SiH4 ) and nitric oxide ( _N2O ). The first buffer layer 400 and the first isolation structure 310 are formed by different deposition powers, thereby obtaining the first buffer layer 400 and the first isolation structure 310 with different water barrier properties, different etching rates or other different characteristics. In some embodiments, the power used when depositing the first buffer layer 400 (or the power divided by the silane flow rate) is greater than the power used when depositing the first isolation structure 310 (or the power divided by the silane flow rate). In some embodiments, the water barrier properties of the first buffer layer 400 and the first isolation structure 310 are detected by measuring the molecular weight of water (M/z=18) released by the sample at 50° C. to 500° C. by thermal desorption spectroscopy (TDS), wherein the water desorption amount (molecules/cm ² ) of the sample of the stacked layer of the first buffer layer 400 and the first isolation structure 310 is less than the water desorption amount (molecules/cm ² ) of the sample of the first isolation structure 310 alone. In other words, the water barrier property of the stacked layer of the first buffer layer 400 and the first isolation structure 310 is better than the water barrier property of the first isolation structure 310 alone. In some embodiments, during the dry etching process, the etching rate of the first buffer layer 400 is greater than the etching rate of the first isolation structure 310. When both the first buffer layer 400 and the first isolation structure 310 include silicon oxide formed by a chemical vapor deposition process, the etching rate decreases as the deposition power of the chemical vapor deposition process increases.

The semiconductor structure 500 is filled in the first through hole H1 and extends from the second source/drain 220 along the first buffer layer 400 to the first source/drain 210. The semiconductor structure 500 contacts the second source/drain 220 and the first source/drain 210. In this embodiment, the first buffer layer 400 is located between the semiconductor structure 500 and the sidewall S1 of the first through hole H1, and the first buffer layer 400 contacts the semiconductor structure 500 and the sidewall S1 of the first through hole H1, but the present invention is not limited thereto. In other embodiments, other buffer layers are included between the first buffer layer 400 and the semiconductor structure 500.

In some embodiments, the material of the semiconductor structure 500 includes an oxide containing two or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), indium gallium oxide (InGO), and indium tungsten oxide (InWO)) or a rare earth doped metal oxide (e.g., Ln-IZO) or other suitable metal oxides or a combination of the above materials. The semiconductor structure 500 has a single-layer structure or a multi-layer structure.

In this embodiment, the semiconductor structure 500 is rectangular in the top view, but the present invention is not limited thereto. In other embodiments, the semiconductor structure 500 is circular, elliptical, triangular or other suitable shapes in the top view.

The gate dielectric layer 320 is located on the semiconductor structure 500. In some embodiments, the material of the gate dielectric layer 320 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials.

The gate 600 is located on the gate dielectric layer 320 and partially fills the first through hole H1. In some embodiments, the material of the gate 600 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The gate 600 may have a single-layer structure or a multi-layer structure.

FIG. 2A to FIG. 2G are cross-sectional schematic diagrams of a manufacturing method of the semiconductor device 10 of FIG. 1A and FIG. 1B. Referring to FIG. 2A, a first source/drain 210 is formed on the substrate 100. In some embodiments, a conductive material layer is first deposited on the entire surface of the substrate 100, and then the conductive material layer is patterned by a lithography process and an etching process to form the first source/drain 210.

Referring to FIG. 2B to FIG. 2D , a first isolation structure 310 and a second source/drain 220 are formed on the first source/drain. In this embodiment, an isolation material layer 310' and a conductive material layer 220' are sequentially formed on the first source/drain 210. Then, a patterned photoresist layer PR1 is formed on the conductive material layer 220', as shown in FIG. 2B . The conductive material layer 220' is etched using the patterned photoresist layer PR1 as a mask to form the second source/drain 220, as shown in FIG. 2C . Finally, the isolation material layer 310' is etched using the patterned photoresist layer PR1 and/or the second source/drain 220 as a mask to form the first isolation structure 310.

In some embodiments, the method of etching the conductive material layer 220' and the isolation material layer 310' includes dry etching, wet etching or a combination thereof. In some embodiments, the first isolation structure 310 has inclined sidewalls, but the present invention is not limited thereto. In other embodiments, the first isolation structure 310 has vertical sidewalls.

In some embodiments, the patterned photoresist layer PR1 is removed using an ashing process or other suitable process.

Referring to FIG. 2E , a buffer material layer 400 'is formed to cover the top surface 220t and sidewall 220s of the second source/drain 220, the sidewall S1 of the first through hole H1 of the first isolation structure 310, and the top surface 210t of the first source/drain 210.

In some embodiments, the sidewall S1 of the first through hole H1 of the first isolation structure 310 may have an uneven surface due to undercut. The buffer material layer 400' can cover the surface unevenness caused by the undercut, thereby improving the yield of the subsequent formation of the semiconductor structure.

In some embodiments, the materials forming the isolation material layer 310' (see FIG. 2B) and the buffer material layer 400' both include silicon oxide, and the forming methods both include chemical vapor deposition, wherein the raw materials used in the chemical vapor deposition include silane ( _SiH4 ) and nitric oxide ( _N2O ). In some embodiments, the power used when depositing the buffer material layer 400' (or the power divided by the silane flow rate) is greater than the power used when depositing the isolation material layer 310' (or the power divided by the silane flow rate).

2F , the buffer material layer 400′ is patterned to form the first buffer layer 400 exposing the top surface 210t of the first source/drain 210 and the top surface 220t of the second source/drain 220. In the present embodiment, the buffer material layer 400′ is patterned by a dry etching process DE. In some embodiments, a dry etching process is performed from the front side of the structure. Since the dry etching process is an anisotropic etching process, the buffer material layer 400' located on the sidewall of the first isolation structure 310 can be retained while removing the buffer material layer 400' located on the top surface 220t of the second source/drain 220 and the bottom of the first through hole H1, and there is no need to use other patterned photoresist layers as etching masks.

Please refer to FIG. 2G , a semiconductor structure 500 is formed in the first through hole H1. In some embodiments, a semiconductor material layer is first formed on the entire surface, and then the semiconductor material layer is patterned using a lithography process and an etching process to form the semiconductor structure 500.

In some embodiments, after forming the semiconductor structure 500, a first annealing process is performed to diffuse oxygen in the semiconductor structure 500 or the environment and store it in the first isolation structure 310 and/or the first buffer layer 400.

Referring to FIG. 2H , a gate dielectric layer 320 is formed on the semiconductor structure 500. In some embodiments, after the gate dielectric layer 320 is formed, a hydrogen doping process is optionally performed on the semiconductor structure 500. In some embodiments, after the gate dielectric layer 320 is formed, a second annealing process is performed to diffuse oxygen stored in the first isolation structure 310 and/or the first buffer layer 400 into the semiconductor structure 500, thereby reducing oxygen vacancies in the portion of the semiconductor structure 500 that contacts the first buffer layer 400 (i.e., the portion that serves as the semiconductor channel region) and increasing its resistivity, thereby reducing the problem of leakage current.

Finally, please return to FIG. 1A and FIG. 1B to form a gate 600 on the gate dielectric layer 320.

FIG3 is a cross-sectional schematic diagram of a semiconductor device 10A according to an embodiment of the present invention. It must be noted that the embodiment of FIG3 uses the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10A of FIG. 3 and the semiconductor device 10 of FIG. 1B is that the semiconductor structure 500A of the semiconductor device 10A includes a first heavily doped region 510, a first lightly doped region 540 and a second heavily doped region 520 through a hydrogen doping process, and the first through hole H1 of the first isolation structure 310A has a steeper sidewall S1.

In the embodiment of FIG3 , the first isolation structure 310A of the semiconductor device 10A includes nitride (e.g., silicon nitride) and the first buffer layer 400 includes oxide (e.g., silicon oxide). Generally speaking, since silicon nitride has a higher etching rate than silicon oxide in a dry etching process, using silicon nitride as the first isolation structure 310A can obtain a steeper sidewall S1. The etching gas used in the dry etching process includes, for example, SF ₆ and O ₂ .

In some embodiments, silicon nitride is selected as the material of the first isolation structure 310A to improve the water barrier property of the first isolation structure 310A. In some embodiments, silicon oxide is selected as the material of the first buffer layer 400, so the first buffer layer 400 can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration in the semiconductor structure 500A during the manufacturing process.

In this embodiment, the semiconductor structure 500A includes a first heavily doped region 510, a first channel region 530, a first lightly doped region 540, and a second heavily doped region 520. The first heavily doped region 510 is located at the bottom of the first through hole H1 and contacts the first source/drain 210. The first channel region 530 is located between the sidewall S1 of the first through hole H1 and the gate dielectric layer 320. The second heavily doped region 520 contacts the second source/drain 220. The first lightly doped region 540 is located between the first channel region 530 and the second heavily doped region 520 and is close to the top of the first through hole H1. In this embodiment, the first channel region 530 and the first lightly doped region 540 contact the first buffer layer 400.

The resistivity of the first channel region 530 is higher than the resistivity of the first lightly doped region 540. The resistivity of the first lightly doped region 540 is higher than the resistivity of the first heavily doped region 510 and the second heavily doped region 520.

4A to 4F are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device 10A of FIG3. Referring to FIG4A, a first source/drain 210 is formed above the substrate 100. Then, an isolation material layer 310A', a conductive material layer 220' and a patterned photoresist layer PR1 are sequentially formed.

Please refer to FIG. 4B , the conductive material layer 220' is etched using the patterned photoresist layer PR1 as a mask to form the second source/drain 220. The isolation material layer 310A' is etched using the patterned photoresist layer PR1 and/or the second source/drain 220 as a mask to form the first isolation structure 310A.

In some embodiments, the material forming the isolation material layer 310A′ includes silicon nitride, and the forming method includes chemical vapor deposition, wherein the raw materials used in the chemical vapor deposition include silane (SiH ₄ ), nitrogen (N ₂ ) and ammonia (NH ₃ ).

In some embodiments, the method of etching the conductive material layer 220' and the isolation material layer 310A' includes dry etching, wet etching or a combination thereof. In some embodiments, the first isolation structure 310A has a vertical sidewall. For example, the inclination of the sidewall of the first isolation structure 310A is related to its etching rate under the dry etching process. When the etching rate is faster, the sidewall of the first isolation structure 310A is closer to vertical.

Referring to FIG. 4C , a buffer material layer 400' is formed to cover the top surface 220t and the side wall 220s of the second source/drain 220, the side wall S1 of the first through hole H1 of the first isolation structure 310A, and the top surface 210t of the first source/drain 210.

In some embodiments, the sidewall S1 of the first through hole H1 of the first isolation structure 310A may have an uneven surface due to undercut. The buffer material layer 400' can cover the surface unevenness caused by the undercut, thereby improving the yield of the subsequent formation of the semiconductor structure.

4D , the buffer material layer 400′ is patterned to form the first buffer layer 400 exposing the top surface 210t of the first source/drain 210 and the top surface 220t of the second source/drain 220. In the present embodiment, the buffer material layer 400′ is patterned by a dry etching process DE. In some embodiments, the dry etching process DE is performed from the front side of the structure. Since the dry etching process DE is an anisotropic etching process, the buffer material layer 400' located on the top surface 220t of the second source/drain 220 and the bottom of the first through hole H1 can be removed while retaining the buffer material layer 400' located on the side wall of the first isolation structure 310A, and there is no need to use other patterned photoresist layers as etching masks.

Please refer to FIG. 4E to form a semiconductor interposer 500A' in the first through hole H1. The semiconductor interposer 500A' is located on the second source/drain 220, the first buffer layer 400, and the first source/drain 210. In some embodiments, a semiconductor material layer is first formed on the entire surface, and then the semiconductor material layer is patterned by a lithography process and an etching process to form the semiconductor interposer 500A'.

In some embodiments, after forming the semiconductor interposer 500A', a first annealing process is performed to diffuse oxygen in the semiconductor interposer 500A' or the environment and store it in the first isolation structure 310A and/or the first buffer layer 400.

A gate dielectric layer 320 is formed on the semiconductor interposer structure 500A’.

Referring to FIG. 4F , a hydrogen doping process HP is performed on the semiconductor interposer 500A’ to form a semiconductor structure 500A. The semiconductor structure 500A includes a first heavily doped region 510, a second heavily doped region 520, a first lightly doped region 540, and a first channel region 530. The first heavily doped region 510 contacts the first source/drain 210, the first channel region 530 and the first lightly doped region 540 contact the first buffer layer 400, and the second heavily doped region 520 contacts the second source/drain 220. The first lightly doped region 540 is located between the first channel region 530 and the second heavily doped region 520.

In this embodiment, the first lightly doped region 540 is located at the turning position between the first channel region 530 and the second heavily doped region 520. Therefore, the first lightly doped region 540 receives a lower degree of hydrogen doping process HP than the first heavily doped region 510 and the second heavily doped region 520 which directly receive the hydrogen doping process HP. Therefore, the resistivity of the first lightly doped region 540 is lower than the resistivity of the first heavily doped region 510 and the second heavily doped region 520. In addition, the first channel region 530 receives a lower degree of hydrogen doping process HP or is completely shielded by the first lightly doped region 540 and does not receive the hydrogen doping process HP. Therefore, the resistivity of the first channel region 530 is lower than the resistivity of the first lightly doped region 540. In some embodiments, the more vertical the sidewall of the first through hole is, the lower the impact of the hydrogen doping process HP on the first channel region 530.

In some embodiments, a gate dielectric layer 320 is formed on the semiconductor interposer 500A' before performing the hydrogen doping process HP, thereby preventing the surface of the semiconductor interposer 500A' from being damaged during the hydrogen doping process HP.

In some embodiments, after forming the gate dielectric layer 320, a second annealing process is performed to diffuse the oxygen stored in the first isolation structure 310A and/or the first buffer layer 400 into the semiconductor structure 500A, thereby reducing the oxygen vacancies in the portion of the semiconductor structure 500A that contacts the first buffer layer 400 (i.e., the portion that serves as the semiconductor channel region) and increasing its resistivity, thereby reducing the leakage current problem. In some embodiments, the second annealing process can be performed before or after the hydrogen doping process HP.

Finally, please return to FIG. 3 to form a gate 600 on the gate dielectric layer 320.

FIG5 is a cross-sectional schematic diagram of a semiconductor device 10B according to an embodiment of the present invention. It must be noted that the embodiment of FIG5 uses the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10B of FIG. 5 and the semiconductor device 10 of FIG. 1B is that the semiconductor device 10B includes a first buffer layer 410 and a second buffer layer 420.

The first buffer layer 410 and the second buffer layer 420 are located in the first through hole H1. The first buffer layer 410 is located between the second buffer layer 420 and the sidewall S1 of the first through hole H1. The first buffer layer 410 contacts the sidewall S1 of the first through hole H1. The second buffer layer 420 contacts the semiconductor structure 500.

In this embodiment, the first buffer layer 410 contacts the sidewall 220s of the second source/drain 220 and continuously extends from the sidewall 220s of the second source/drain 220 to the top surface 210t of the first source/drain 210.

In some embodiments, the first buffer layer 410 and the second buffer layer 420 not only cover the sidewall S1 of the first through hole H1, but also cover the outer sidewall of the first isolation structure 310. Therefore, the first isolation structure 310 is laterally surrounded by the first buffer layer 410 and the second buffer layer 420.

In some embodiments, the materials of the first buffer layer 410 and the second buffer layer 420 include oxides (such as silicon oxide or silicon oxynitride) or other suitable materials. By providing the first buffer layer 410 and the second buffer layer 420, the first isolation structure 310 can be prevented from being damaged during the manufacturing process, thereby making the semiconductor structure 500 have a higher yield. For example, the first buffer layer 410 and the second buffer layer 420 can prevent moisture from invading the first isolation structure 310 during the manufacturing process, thereby preventing the semiconductor structure 500 from being contaminated by moisture.

In some embodiments, the first buffer layer 410 and the second buffer layer 420 include oxides and can be used as oxygen storage/replenishing layers, thereby adjusting the oxygen concentration in the semiconductor structure 500 during the manufacturing process.

FIG6A is a schematic top view of a semiconductor device 10C according to an embodiment of the present invention. FIG6B is a schematic cross-sectional view along line A-A' of FIG6A. It must be noted that the embodiments of FIG6A and FIG6B use the component numbers and partial contents of the embodiment of FIG3, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10C of FIG. 6A and FIG. 6B and the semiconductor device 10A of FIG. 3 is that the semiconductor device 10C includes a second isolation structure 330 and a third source/drain 230.

The second isolation structure 330 is located on the second source/drain 220 and has a second through hole H2 overlapping the first through hole H1. The third source/drain 230 is located on the top surface of the second isolation structure 330.

The first buffer layer 400C covers the sidewall S1 of the first through hole H1 and the sidewall S2 of the second through hole H2. For example, the first portion 402 of the first buffer layer 400C covers the sidewall S1 of the first through hole H1, and the second portion 404 of the first buffer layer 400C covers the sidewall S2 of the second through hole H2. The first portion 402 extends continuously from the second source/drain 220 to the first source/drain 210, and the second portion 404 extends continuously from the third source/drain 230 to the second source/drain 220. There is a gap between the first portion 402 and the second portion 404, and the gap prevents a portion of the top surface 220t of the second source/drain 220 from being covered by the first buffer layer 400C.

The semiconductor structure 500C includes a first heavily doped region 510, a first lightly doped region 540, a second heavily doped region 520, a third heavily doped region 570, and a second lightly doped region 560 through a hydrogen doping process.

The first heavily doped region 510 is located at the bottom of the first through hole H1 and contacts the first source/drain 210. The first channel region 530 is located between the sidewall S1 of the first through hole H1 and the gate dielectric layer 320. The second heavily doped region 520 contacts the second source/drain 220 and is located at the bottom of the second through hole H2. The first lightly doped region 540 is located between the first channel region 530 and the second heavily doped region 520 and is close to the top of the first through hole H1 and the bottom of the second through hole H2. In this embodiment, the first channel region 530 and the first lightly doped region 540 contact the first portion 402 of the first buffer layer 400C. The second channel region 550 is located between the sidewall S2 of the second through hole H2 and the gate dielectric layer 320. The third heavily doped region 570 contacts the third source/drain 230. The second lightly doped region 560 is located between the second channel region 550 and the third heavily doped region 570 and is close to the top of the second through hole H2. In this embodiment, the second channel region 550 and the second lightly doped region 560 contact the second portion 404 of the first buffer layer 400C.

The resistivity of the first channel region 530 and the second channel region 550 is higher than the resistivity of the first lightly doped region 540 and the second lightly doped region 560. The resistivity of the first lightly doped region 540 and the second lightly doped region 560 is higher than the resistivity of the first heavily doped region 510, the second heavily doped region 520 and the third heavily doped region 570.

FIG. 7A to FIG. 7G are cross-sectional schematic diagrams of a manufacturing method of the semiconductor device 10C of FIG. 6A and FIG. 6B. Referring to FIG. 7A, after forming the first source/drain 210, the first isolation structure 310A, and the second source/drain 220 in a manner similar to FIG. 4A to FIG. 4D, the patterned photoresist layer PR1 is removed. Then, an isolation material layer 330', a conductive material layer 230', and a patterned photoresist layer PR2 are sequentially formed on the second source/drain 220.

Please refer to FIG7B , the conductive material layer 230' is etched with the patterned photoresist layer PR2 as a mask to form the third source/drain 230. Please refer to FIG7C , the isolation material layer 330' is etched with the patterned photoresist layer PR2, the second source/drain 220 and the third source/drain 230 as a mask to form the second isolation structure 330.

In some embodiments, the method of etching the conductive material layer 230' and the isolation material layer 330' includes dry etching, wet etching or a combination thereof. In some embodiments, the second isolation structure 330 has vertical sidewalls, but the present invention is not limited thereto. In other embodiments, the second isolation structure 330 has inclined sidewalls.

Referring to FIG. 7D , a buffer material layer 400C’ is formed to cover the top surface 230t of the third source/drain 230, the sidewall S2 of the second through hole H2 of the second isolation structure 330, the top surface 220t of the second source/drain 220, the sidewall S1 of the first through hole H1 of the first isolation structure 310A, and the top surface 210t of the first source/drain 210.

In some embodiments, the sidewall S1 of the first through hole H1 of the first isolation structure 310A and the sidewall S2 of the second through hole H2 of the second isolation structure 330 may have a surface unevenness problem due to undercutting. The buffer material layer 400C' can cover the surface unevenness caused by the aforementioned undercutting, thereby improving the yield of the subsequent formation of the semiconductor structure.

7E , the buffer material layer 400C’ is patterned to form a first buffer layer 400C exposing the top surface 210t of the first source/drain 210, the top surface 220t of the second source/drain 220, and the top surface 230t of the third source/drain 230. In the present embodiment, the buffer material layer 400C’ is patterned by a dry etching process DE. In some embodiments, the dry etching process DE is performed from the front side of the structure. Since the dry etching process DE is an anisotropic etching process, the buffer material layer 400C' located on the top surface 230t of the third source/drain 230, the bottom of the second through hole H2, and the bottom of the first through hole H1 can be removed while retaining the buffer material layer 400' located on the sidewall of the first isolation structure 310A and the sidewall of the second isolation structure 330, and there is no need to use other patterned photoresist layers as etching masks.

Please refer to FIG. 7F to form a semiconductor interposer 500C' in the first through hole H1 and the second through hole H2. The semiconductor interposer 500C' is located on the third source/drain 230, the second source/drain 220, the first source/drain 210 and the first buffer layer 400C. In some embodiments, a semiconductor material layer is first formed on the entire surface, and then the semiconductor material layer is patterned by a lithography process and an etching process to form the semiconductor interposer 500C'.

In some embodiments, after forming the semiconductor interposer 500C', a first annealing process is performed to diffuse oxygen in the semiconductor interposer 500C' or the environment and store it in the first isolation structure 310A, the second isolation structure 330 and/or the first buffer layer 400C.

A gate dielectric layer 320 is formed on the semiconductor interposer structure 500C’.

Referring to FIG. 7G , a hydrogen doping process HP is performed on the semiconductor interposer 500C’ to form a semiconductor structure 500C. The semiconductor structure 500C includes a first heavily doped region 510, a second heavily doped region 520, a third heavily doped region 570, a first lightly doped region 540, a second lightly doped region 560, a first channel region 530, and a second channel region 550.

In this embodiment, the first lightly-doped region 540 is located at the turning position between the first channel region 530 and the second heavily-doped region 520, and the second lightly-doped region 560 is located at the turning position between the second channel region 550 and the third heavily-doped region 570. Therefore, compared with the first heavily-doped region 510, the second heavily-doped region 520 and the third heavily-doped region 570 directly receiving the hydrogen-doping process HP, the first lightly-doped region 540 and the second lightly-doped region 560 receive a lower degree of the hydrogen-doping process HP. Therefore, the resistivity of the first lightly doped region 540 and the second lightly doped region 560 is lower than the resistivity of the first heavily doped region 510, the second heavily doped region 520, and the third heavily doped region 570. In addition, the first channel region 530 and the second channel region 550 receive a lower degree of hydrogen doping process HP or are completely shielded and do not receive the hydrogen doping process HP. Therefore, the resistivity of the first channel region 530 and the second channel region 550 is lower than the resistivity of the first lightly doped region 540 and the second lightly doped region 560. In some embodiments, a gate dielectric layer 320 is formed on the semiconductor interposer 500C' before performing the hydrogen doping process HP, thereby preventing the surface of the semiconductor interposer 500C' from being damaged during the hydrogen doping process HP.

In some embodiments, after forming the gate dielectric layer 320, a second annealing process is performed to diffuse the oxygen stored in the first isolation structure 310A, the second isolation structure 330 and/or the first buffer layer 400C into the semiconductor structure 500C, thereby reducing the oxygen vacancies in the portion of the semiconductor structure 500C that contacts the first buffer layer 400C (i.e., the portion that serves as the semiconductor channel region) and increasing its resistivity, thereby reducing the leakage current problem. In some embodiments, the second annealing process can be performed before or after the hydrogen doping process HP.

Finally, please return to FIG. 6A and FIG. 6B to form a gate 600 on the gate dielectric layer 320.

In summary, by setting up the first buffer layer, the yield of the first isolation structure and the semiconductor structure can be improved, thereby enabling the semiconductor device to have a stable operating current.

10: Semiconductor devices

100: Substrate

210: First source/drain

210t,220t: Top surface

220: Second source/drain

220s, S1: side wall

310: First isolation structure

320: Gate dielectric layer

400: First buffer layer

500:Semiconductor structure

600: Gate

H1: First through hole

ND: Normal direction

t1,t2: thickness

Claims (10)

A semiconductor device comprises: a first source/drain; a first isolation structure located on the first source/drain and having a first through hole overlapping the first source/drain; a second source/drain located on the top surface of the first isolation structure; a first buffer layer covering the sidewalls of the first through hole and extending continuously from the second source/drain to the first source/drain; a semiconductor structure filled in the first through hole and extending from the second source/drain along the first buffer layer to the first source/drain; a gate dielectric layer located on the semiconductor structure; and A gate is located on the gate dielectric layer. A semiconductor device as described in claim 1, wherein the semiconductor structure comprises: a first heavily doped region contacting the first source/drain; a first channel region located between the sidewall of the first through hole and the gate dielectric layer; and a second heavily doped region contacting the second source/drain, wherein the resistivity of the first channel region is higher than the resistivity of the first heavily doped region and the resistivity of the second heavily doped region. A semiconductor device as described in claim 2, wherein the semiconductor structure comprises: A first lightly doped region located between the first channel region and the second heavily doped region, and the resistivity of the first lightly doped region is higher than the resistivity of the second heavily doped region and lower than the resistivity of the first channel region. A semiconductor device as described in claim 1, wherein the first buffer layer contacts the side wall of the second source/drain and extends continuously from the side wall of the second source/drain to the top surface of the first source/drain. The semiconductor device as described in claim 1 further includes: a second isolation structure located on the second source/drain and having a second through hole overlapping the first through hole, wherein the first buffer layer covers the side wall of the first through hole and the side wall of the second through hole; a third source/drain located on the top surface of the second isolation structure, wherein the first buffer layer extends continuously from the third source/drain to the second source/drain. A semiconductor device as described in claim 5, wherein the semiconductor structure further comprises: a third heavily doped region contacting the third source/drain; a second channel region located between the sidewall of the second through hole and the gate dielectric layer; and a second lightly doped region located between the second channel region and the third heavily doped region, wherein the resistivity of the second lightly doped region is higher than the resistivity of the third heavily doped region and lower than the resistivity of the second channel region. The semiconductor device as described in claim 1 further comprises: a second buffer layer, wherein the first buffer layer is located between the second buffer layer and the side wall of the first through hole, wherein the first buffer layer contacts the side wall of the first through hole, and the second buffer layer contacts the semiconductor structure. A method for manufacturing a semiconductor device, comprising: Forming a first isolation structure above a first source/drain, wherein the first isolation structure has a first through hole overlapping the first source/drain; Forming a second source/drain above the first source/drain; Forming a buffer material layer to cover the top surface of the second source/drain, the sidewalls of the first through hole, and the top surface of the first source/drain; Patterning the buffer material layer to form a first buffer layer exposing the top surface of the first source/drain and the top surface of the second source/drain, wherein the first buffer layer covers the sidewall of the first through hole and extends continuously from the second source/drain to the first source/drain; Forming a semiconductor structure in the first through hole, and the semiconductor structure extends from the second source/drain along the first buffer layer to the first source/drain; Forming a gate dielectric layer in the first through hole; and Forming a gate on the gate dielectric layer. The manufacturing method as described in claim 8, wherein the method of forming the semiconductor structure includes: forming a semiconductor interposer structure on the second source/drain, the first buffer layer and the first source/drain; and A hydrogen doping process is performed on the semiconductor interposer to form the semiconductor structure, wherein the semiconductor structure includes a first heavily doped region, a second heavily doped region, a first lightly doped region, and a first channel region, wherein the first heavily doped region contacts the first source/drain, the first channel region contacts the first buffer layer, the second heavily doped region contacts the second source/drain, the first lightly doped region is located between the first channel region and the second heavily doped region, and the resistivity of the first lightly doped region is higher than the resistivity of the second heavily doped region and lower than the resistivity of the first channel region. The manufacturing method as described in claim 9, wherein the gate dielectric layer is formed on the semiconductor interposer before performing the hydrogen doping process.