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TW201818386A - 電致發光顯示器中的電壓補償電路 - Google Patents

電致發光顯示器中的電壓補償電路 Download PDF

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Publication number
TW201818386A
TW201818386A TW106131488A TW106131488A TW201818386A TW 201818386 A TW201818386 A TW 201818386A TW 106131488 A TW106131488 A TW 106131488A TW 106131488 A TW106131488 A TW 106131488A TW 201818386 A TW201818386 A TW 201818386A
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TW
Taiwan
Prior art keywords
transistor
capacitor
pixel unit
voltage
sub
Prior art date
Application number
TW106131488A
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English (en)
Other versions
TWI627620B (zh
Inventor
鄭士嵩
Original Assignee
創王光電股份有限公司
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Publication of TW201818386A publication Critical patent/TW201818386A/zh
Application granted granted Critical
Publication of TWI627620B publication Critical patent/TWI627620B/zh

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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • H—ELECTRICITY
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Abstract

揭示於一電致發光(EL)裝置中進行電壓補償的電路。所述電路包含EL裝置的一像素單元、一與像素單元相關聯的一阻抗負載及一開關。所述像素單元包含一電致發光(EL)裝置、一第一電容器，用以儲存與EL裝置相關的資料、以及一電晶體，包含與第一電容器第一端耦接的一閘極以及與所述電容器第二端耦接的第一終端。所述阻抗負載包含一第二電容器，其電容量遠高於第一電容器的電容量。所述開關透過阻抗負載將像素單元選擇性地連接至一電流槽。

Description

電致發光顯示器中的電壓補償電路
本發明是關於一種電壓補償電路，特別是用於電致發光顯示器中的電壓補償電路。
電致發光(EL)顯示器，譬如主動矩陣有機發光二極體(active matrix organic light emitting diode，AMOLED)顯示器，可包含一像素陣列。該些像素中的每一像素可包含一EL裝置、用以傳輸含有與亮度相關之資訊的一開關電晶體、以及用以驅動該EL裝置使其根據該資料而發光的一驅動電晶體。雖然此種EL顯示器具備電力消耗較低的優點，但半導體製備過程中的製程因素卻可能使多個像素間的顯示不均勻。因此，相關領域需要一種能夠解決上述問題的電路。
本發明實施例提出一種電致發光(EL)顯示器的電壓補償電路，包含一子像素單元、一阻抗負載及一開關。該子像素單元包含一電致發光(EL)裝置、一第一電容器，耦接於該EL裝置，用以儲存與該EL裝置相關的資料、以及一電晶體，包含一閘極，耦接至該第一電容器的一第一端，以及一終端，耦接至該電容器的一第二端。該阻抗負載耦接於該子像素單元，包含一第二電容器，其電容值高於該第一電容器的電容值。該開關選擇性地耦接於該阻抗負載或斷開，將該子像素單元耦接至相應的一電流槽或與該電流槽斷開。 於一實施例中，該子像素單元還包含另一電晶體，用以在第一階段中重置位於電晶體閘極的電壓位準。 於另一實施例中，該另一電晶體還用以於第二階段中接收與該EL裝置相關的資料。 於又一實施例中，該第二電容器用以在該第二階段中，保持該電晶體之該終端的電壓位準，該電壓位準等於該終端在該第一階段中的電壓位準。 於又另一實施例中，該子像素單元還包含又一電晶體，分別耦接於該電晶體與一供應電壓，該又一電晶體用以於第三階段中使一電流流經EL裝置。 於又一實施例中，該第二電容器用以在該第三階段中，保持該電晶體之該閘極與該終端之間的電壓差異，該電壓差異等於其於該第二階段中的電壓差異。 於一實施例中，該電流的強度與與電晶體的閾值電壓無關。 於另一實施例中，該子像素單元還包含又一電晶體，分別耦接於該電晶體與該阻抗負載，用以在第一階段中於該電晶體的該終端建立和該電晶體之閾值電壓相關聯的一補償電壓。 本發明某些實施例提出一種電致發光(EL)裝置，其包含多個像素單元，以及一電壓補償電路。該等像素單元呈矩陣排列，且每一該像素單元包含多個子像素單元。該電路包含該等子像素單元、一阻抗負載及一開關。每一該子像素單元包含一電致發光(EL)裝置、一第一電容器，耦接於該EL裝置，用以儲存與該EL裝置相關的資料、以及一電晶體，包含一閘極，耦接至該第一電容器的一第一端，以及一終端，耦接至該電容器的一第二端耦接。該阻抗負載，耦接於該子像素單元，包含一第二電容器，其電容值高於該第一電容器的電容值。該開關，選擇性地耦接於該阻抗負載或斷開，將該子像素單元耦接至相應的一電流槽或與該電流槽斷開。 本發明的實施例亦提供一種在電致發光(EL)顯示器中進行電壓補償的方法，該EL顯示器包含一像素單元陣列，每一像素單元包含一電晶體與一第一電容器。該方法包含：提供一開關，以透過與一像素單元相關聯的一阻抗負載將該像素單元其中之一選擇性地連接至一電流槽；將該電晶體閘極的電壓位準重置為參考電壓；建立與在該電晶體的一終端之電晶體的閾值電壓相關聯的補償電壓；將與該EL裝置相關的資料儲存於該第一電容器中並利用該阻抗負載中的一第二電容器保持位於一終端的電壓位準；以及使一電流透過該電晶體流經一EL裝置，該電流的強度與該電晶體的閾值電壓無關。
以下揭示內容提供了多種實施方式或例示，其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，這些敘述僅為例示，其本意並非用於限制本揭示內容。舉例來說，在下文的描述中，將一第一特徵形成於一第二特徵上或之上，可能包含某些實施例其中所述的第一與第二特徵彼此直接接觸；且也可能包含某些實施例其中還有而外的元件形成於上述第一與第二特徵之間，而使得第一與第二特徵可能沒有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚的目的，且其本身不代表所討論的不同實施例和/或組態之間的關係。 此外，當可理解，若將一部件描述為與另一部件「連接(connected to)」或「耦接(coupled to)」，則兩者可直接連接或耦接，或兩者間可能出現其他中間(intervening)部件。 在下文說明中，當一裝置屬於正緣觸發(active high)，係使一信號生效(asserted)而具有高邏輯值，以啟動該相應裝置。反之，使該信號失效(deasserted)而具有低邏輯值，以停用該相應裝置。然而當該裝置屬於負緣觸發(active low)時，係使該信號生效而具有低邏輯值，以啟動該裝置，且使該信號失效而具有高邏輯值，以停用該裝置。 圖1為根據一實施例的顯示器10之區塊圖。顯示器10可包含一電致發光(EL)顯示器，譬如主動矩陣有機發光二極體(AMOLED)顯示器。 參照圖1，顯示器10包含主動區域12、閘極驅動器14及源極驅動器15。主動區域12包含一像素單元陣列，舉例來說，可將多個像素單元P排列成N×M的矩陣，其中N、M分別為正整數。閘極驅動器14經由N條掃描線將多個控制信號提供給N列像素單元，例如第一控制信號SN及第二控制信號EM。源極驅動器15透過資料線DATA[1]至DATA[M]，將資料提供給M行像素單元中的一所選像素。此外，資料線DATA[1]至DATA[M]中的每一條線透過一開關SW而選擇性地與一對應電流槽I0 耦接。再者，電源驅動器16在供應電壓VDD及VSS的電軌中提供一供應電壓至上述主動區域12。在一實施例中，供應電壓VDD(即工作電壓)約為5伏特(5V)，而供應電壓VSS)(即接地電壓)約為-5V。 主動區域12中像素單元P的每一者包含三個子像素單元20，其可用以顯示紅色(R)、綠色(G)及藍色(B)等顏色，且三者所顯示顏色互異。在其他實施例中，例如，在子像素渲染(sub-pixel rendering，SPR)感應器中，子像素單元20的數目不限於三。在本實施例中，三種子像素20係沿著列的方向排列。因此，源極驅動器15的資料線數目為3×M。 圖2是根據一實施例，用於在圖1所示EL顯示器10的電壓補償電路200之電路圖。參照圖2，電壓補償電路200 包含一例示性的子像素單元20、一阻抗負載25、一開關SW以及一電流槽I0 。其中，雖然在本實施例中將子像素單元20配置為包含四個電晶體T1至T4與一個電容器Cst的4T1C電路結構。然而，在本發明的其他實施例中，子像素單元不限於4T1C電路結構或任何特定結構，包含任何數目的電晶體或電容器之子像素單元皆屬於本揭示內容之範圍。 在本實施例中，子像素單元20包含一EL裝置28、四個電晶體T1至T4及一個電容器Cst。舉例來說，EL裝置28包含一電流驅動部件，其可包含一有機發光二極體(organic light emitting diode，OLED)、微LED或量子點LED(quantum dot LED，QLED)。電容器Cst作為儲存電容器。電晶體T3作為驅動電晶體，其可根據儲存於電容器Cst中的資料來驅動EL裝置28。此外，電晶體T1至T4中每一個電晶體可以是n型薄膜電晶體(thin film transistor， TFT)或n型金氧半(metal-oxide-semiconductor，MOS)電晶體。 在例示性的4T1C電路結構中，電晶體T1的閘極耦接於閘極驅動器14，用以從閘極驅動器14接收一對應閘極線上的第一控制信號SN。電晶體T1的汲極耦接於源極驅動器15，用以回應上述第一控制信號SN，以及從源極驅動器15接收一對應資料線上的資料(標記為"DATA")。此外，電晶體T3的閘極耦接至電晶體T1的源極以及電容器Cst的一第一端。電晶體T3的源極耦接至電容器Cst的一第二端以及耦接至EL裝置28的陰極。本發明所屬技術領域中具有通常知識者當可理解，MOS電晶體的汲極與源極可互換，端視施加至該處的電壓位準而定。 此外，電晶體T4的閘極耦接於閘極驅動器14，用以接收一第二控制信號EM。電晶體T4的汲極耦接於電源驅動器16，用以接收一供應電壓VDD。電晶體T4的源極耦接至電晶體T3的汲極。再者，電晶體T2的閘極亦耦接於閘極驅動器14，用以接收第一控制信號SN。電晶體T2的源極耦接至電晶體T3的源極，且因此亦連接至電容器Cst的第二端以及EL裝置28的陰極。EL裝置28的陽極接收另一供應電壓VSS。此外，子像素單元20透過電晶體T2的汲極耦接至阻抗負載25。 與例示性子像素單元20相關的阻抗負載25是由寄生電阻器與寄生電容器組成的網路所形成。這些寄生電阻器與電容器可存在於進行子像素單元20佈線(routing)時可能涉及之傳導層與介電層之中或之間。舉例來說，成對的寄生電阻器Ry與寄生電容器Cy(以下簡稱寄生對)和在N×M的像素單元陣列中的第y個子像素單元相關，其中y是1到N之間的正整數。因此，從電晶體T2的汲極來看，與子像素單元20相關的R1、C1寄生對至RN、CN寄生對彼此併聯，而在每一寄生對中，譬如在R1、C1寄生對中，寄生電阻器R1與寄生電容器C1互相串聯。可將阻抗負載25簡化為一等效電路250(如圖3B、4B及5B所示)，其是由等效電阻器Rcol與等效電容器Ccol所形成。當已有EL顯示器10的佈局時，可在設計階段模擬出等效電阻器Rcol的阻抗值以及等效電容器Ccol的電容值。其中，在本發明的某些實施例中，也可以將寄生電容器Cy視為第一電容器，以及將等效電容器Ccol視為第二電容器，以示區隔。 開關SW係用以選擇性地將對應子像素單元20電性連接至對應電流槽(current sink)I0 ，或斷開對應子像素單元20與對應電流槽I0 的電性連接。如此一來，當開關SW關閉時，可建立對應子像素單元20與對應電流槽I0 之間的電流槽路徑(current sink path)。相反地，當開關SW釋放時，會切斷對應子像素單元20與對應電流槽I0 之間的電流槽路徑。於一實施例中，由顯示面板上的多個TFT形成這些開關SW，且開關SW位於像素單元陣列外部。於另一實施例中，由和像素單元陣列整合於一IC中的MOS電晶體形成開關SW。 每一電流槽I0 提供一恆定電流，亦標記為I0 。在某些實施例中，可調整電流I0 的強度，以基於製程因素來強化電流槽的效能。 子像素單元20的4T1C電路結構相對簡單。此外，位於EL顯示器10之像素單元陣列以外的電路可包含多個開關SW及電流槽I0 ，這些也是相對簡單的電路，且有助於主動區域12的設計。事實上，基於上述結構的EL顯示器10有助於實現高像素密度(pixel-per-inch，ppi)應用之優點。更有甚者，可在設計階段預先決定阻抗負載25，並可輕易地實作開關SW與電流槽I0 。因此，可以減輕驅動器IC的負擔。 圖3A、3B及3C繪示根據某些實施例，在第一階段中，操作圖2所示電壓補償電路200的方法。 參照圖3A，對於電晶體T1至T4而言，第一至第三控制信號EM、SN及ISW經設定為正緣觸發。開關SW可以是一n-型電晶體，其受到第三控制信號ISW所控制。在操作上，於時間點t1，將第一控制信號SN拉至正緣(rising edge)，而第二控制信號EM及第三控制信號ISW保持在高邏輯位準。因此，參照圖3B，電晶體T1至T4都被開啟，且與之相應的開關SW被關閉。由於電晶體T1是開啟的，使作為驅動電晶體的電晶體T3之閘極的電壓位準（標記為VG）拉至一資料電壓Vdata，此資料電壓Vdata在時間點t1可作為參考電壓Vref。於一實施例中，參考電壓Vref約為0V。更進一步，由於開關SW是關閉的，在第一階段中，所述電路用以透過阻抗負載250來儲存電流。電流Ids由供應電壓VDD流經電晶體T4、T3、T2、阻抗負載250及開關SW而到達電流槽I0 。可將流經電晶體T3的電流Ids表達為下列方程式(1)。 2 方程式(1) 其中k為常數，VGS代表電晶體T3之閘極至源極電壓，而Vth3代表電晶體T3的閾值電壓。 由於Ids等於I0 ，可將方程式(1)改寫為下列方程式(2)。 2 = 2 方程式(2) 其中VG代表電晶體T3之閘極電壓，VS代表電晶體T3之源極電壓，而Vov（被定義為VGS-Vth3）代表電晶體T3的過激電壓。圖3C繪示在此階段中，電晶體T3之VG及VS間相對於VDD及VSS之關係。 承上，由於Vov=VG-VS-Vth3且VG=Vref，可將VS 改寫如下。 VS=VG-Vov-Vth3=Vref-Vov-Vth3 方程式(3) 因此，在第一階段中，重置VG的電壓位準，例如將VG重置為Vref，而VS為Vth3的函數。在電晶體T3的源極建立一補償電壓，即電晶體T3的閾值電壓Vth3。 圖4A、4B及4C繪示根據某些實施例，在第二階段中，操作圖2所示電壓補償電路200的方法。 參照圖4A，在時間點t2，將第二控制信號EM拉至負緣(falling edge)失效，而第一控制信號SN保持在高邏輯位準及第三控制信號ISW亦失效。因此，參照圖4B，將電晶體T4關閉(圖中以"×"符號標記)，而電晶體T1及T2則保持在開啟狀態，且斷開相應的開關SW。由於電晶體T1保持開啟，將資料D[y]寫入VG，使VG由Vref改變為Vdata，因此，以電容器Cst及等效電容器Ccol的電容值為函數，可將VS表示為以下方程式(4)。 VS=Vref-Vov-Vth3+×(Vdata-Vref)] 方程式(4) 在此方程式中，Cst及Ccol分別代表儲存電容器Cst及等效電容器Ccol的電容值。其中，電容值Ccol明顯高於Cst，且可能是Cst的數百倍。因此，)的數值趨近於0且可忽略不計。此外，VS實質上等於在第一階段之VS=Vref-Vov-Vth3(如方程式(3)所示)。在第二階段中，將包含EL裝置28之灰階值的資訊，即資料D[y]，寫入VG。圖4C繪示在第二階段中，驅動電晶體T3之VG及VS間相對於VDD及VSS之關係。應注意到在第二階段中 VGS=Vdata-(Vref-Vov-Vth3)=Vov+Vth3+Vdata-Vref，其大於EL裝置28的閾值電壓。然而，由於電晶體T4是關閉的，沒有電流會流過EL裝置28。 因此，在第二階段中，將與所述EL裝置28相關的資料儲存於電容器Cst中。此外，VS的值可以利用阻抗負載250中的等效電容器Ccol來維持，使其實質上等於在第一階段的值。 圖5A、5B及5C繪示根據某些實施例，在第三階段中，操作圖2所示電壓補償電路200的方法。 參照圖5A，在時間點t3，將第二控制信號EM拉至正緣，並使第一控制信號SN失效。因此，參照圖5B，電晶體T1及T2被關閉，電晶體T4被打開而產生一正值的電壓偏移Vshift。透過電容器Cst的耦接功能，此正值的電壓偏移Vshift使VG與VS偏移而到達一電性平衡。分別以下列方程式(5)及方程式(6)來表示VG及VS。 VG=Vdata+Vshift 方程式(5) VS=Vref-Vov-Vth3+Vshift 方程式(6) 因此，由於VG及VS都被Vshift拉高，VGS保持不變，且如上文針對第二階段之操作時所述，VGS大於。圖5C繪示在第三階段中電晶體T3之VG及VS間相對於VDD及VSS之關係。隨著第二控制信號EM生效，電流Iel由VDD透過電晶體T4、T3及EL裝置28而流向VSS，使得EL裝置28根據所述資料DATA發出光線。電流Iel可表示為以下方程式(7)。 2 = 2 方程式(7) 由於方程式(7)中的電流Iel不含任何Vth參數，可提升EL顯示器10的顯示品質。 因此，在第三階段中，等效電容器Ccol協助VG及VS達到電性平衡，且可維持VGS使其和在第二階段的數值相同。 圖6A是根據另一實施例，用於在圖1所示之顯示器10中進行電壓補償的電壓補償電路600之電路圖。 參照圖6A，電壓補償電路600與上文參照圖2所述之電壓補償電路200相似，不同之處在於例如例示性子像素單元60中的電晶體T1至T4以p型TFT或P型金氧半電晶體(PMOS)取代圖2之子像素單元20的n型TFT或NMOS。此外，相似地，可將阻抗負載25簡化為圖6B所示的等效負載250。 在例示性的4T1C電路結構中，子像素單元60的電晶體T1的閘極耦接至閘極驅動器14，用以接收來自閘極驅動器14位於對應閘極線上的第一控制信號SN。電晶體T1的源極耦接於源極驅動器15，用以回應第一控制信號SN，以及接收來自源極驅動器15位於對應資料線上的資料DATA。此外，電晶體T3的閘極耦接至電晶體T1的汲極並耦接至電容器Cst的第一端。電晶體T3的源極耦接至電容器Cst的第二端並耦接至EL裝置28的陽極。 此外，電晶體閘極T4的閘極耦接於閘極驅動器14，用以接收第二控制信號EM。電晶體T4的汲極耦接於電源驅動器16，用以接收供應電壓VSS。電晶體T4的源極耦接至電晶體T3的汲極。更進一步，電晶體T2的閘極亦耦接於閘極驅動器14，用以接收第一控制信號SN。電晶體T2的汲極耦接至電晶體T3的源極，並因而耦接至電容器Cst的第二端以及EL裝置28的陽極。EL裝置28的陰極接收另一供應電壓VDD。此外，子像素單元20透過電晶體T2的源極耦接至阻抗負載25。 圖6C為根據某些實施例，用以操作圖6A所示電路之第一至第三控制信號EM、SN及ISW的時序圖。 參照圖6C，第一至第三控制信號EM、SN及ISW與上文參照圖3A、4A或5A所述者相似，不同之處例如在於，圖6C的第一至第三控制信號EM、SN及ISW基於子像素單元60中的電晶體T1至T4為負緣觸發，或在負緣生效。如圖6B所示，電流Iel'由VDD流經EL裝置28及電晶體T3、T4而到達VSS，使得EL裝置28可根據所述資料DATA而發出光線。可將電流Iel'表示為以下方程式(8)。 2 = 2 方程式(8) 由於方程式(8)中的電流Iel’不含任何Vth參數，可提升EL顯示器10的顯示品質。 圖7為一流程圖，繪示在電致發光顯示器中進行電壓補償的方法。 參照圖7，在操作71，提供一電致發光(EL)顯示器。所述EL顯示器包含一像素單元陣列，其中每一像素單元包含多個子像素單元，且每一子像素單元分別包含EL裝置、電晶體及第一電容器。 接著，在操作73，透過與子像素單元相對應的阻抗負載，將子像素單元選擇性地連接至電流槽。 在操作75，於第一階段中，將電晶體閘極之電壓位準重置為參考電壓。 在操作76，於第一階段中，在電晶體的一終端建立與電晶體之閾值電壓相關聯的補償電壓。 在操作77，於第二階段中，將與所述EL裝置相關的資料儲存於第一電容器中。此外，利用阻抗負載中的第二電容器保持電晶體之終端的電壓位準，使其實質上與第一階段中的值相同。同時，利用等效電容器協助電晶體的閘極之電壓位準與終端之電壓位準達到電性平衡，並保持電晶體之源極電壓使其與第二階段中的值相同。 其後，在操作78，使電流透過電晶體而流經所述EL裝置。上述電流的強度與所述電晶體的閾值電壓無關。 上文的敘述簡要地提出了本發明某些實施例之特徵，而使得本發明所屬技術領域具有通常知識者能夠更全面地理解本揭示內容的多種態樣。本發明所屬技術領域具有通常知識者當可明瞭，其可輕易地利用本揭示內容作為基礎，來設計或更動其他製程與結構，以實現與此處所述之實施方式相同的目的和/或達到相同的優點。本發明所屬技術領域具有通常知識者應當明白，這些均等的實施方式仍屬於本揭示內容之精神與範圍，且其可進行各種變更、替代與更動，而不會悖離本揭示內容之精神與範圍。
10‧‧‧EL顯示器
12‧‧‧主動區域
14‧‧‧閘極驅動器
15‧‧‧源極驅動器
16‧‧‧電源驅動器
20、60‧‧‧子像素單元
P‧‧‧像素單元
25‧‧‧阻抗負載
28‧‧‧EL裝置
200、600‧‧‧電壓補償電路
250‧‧‧等效負載
Ccol‧‧‧等效電容器
Cst‧‧‧電容器
C1至CN‧‧‧寄生電容器
DATA‧‧‧資料
I0‧‧‧電流槽
R1至RN‧‧‧寄生電阻器
SN‧‧‧第一控制信號
EM‧‧‧第二控制信號
ISW‧‧‧第三控制信號
SW‧‧‧開關
T1~T4‧‧‧電晶體
VS、VG、Vov、Vth3‧‧‧電壓
Vref‧‧‧參考電壓
VDD、VSS‧‧‧供應電壓
t1~t3‧‧‧時間點
Ids、Iel、Iel’‧‧‧電流
71~78‧‧‧步驟
在閱讀了下文實施方式以及附隨圖式時，能夠最佳地理解本揭露的多種態樣。應注意到，根據本領域的標準作業習慣，圖中的各種特徵並未依比例繪製。事實上，為了能夠清楚地進行描述，可能會刻意地放大或縮小某些特徵的尺寸。 圖1為根據一實施例之顯示器的區塊圖。 圖2為根據一實施例，於圖1所示EL顯示器中的電壓補償電路的電路圖。 圖3A、3B及3C繪示根據某些實施例，於第一階段中操作圖2所示電路的方法。 圖4A、4B及4C繪示根據某些實施例，於第二階段中操作圖2所示電路的方法。 圖5A、5B及5C繪示根據某些實施例，於第三階段中操作圖2所示電路的方法。 圖6A及6B為根據另一實施例，於圖1所示EL顯示器10中進行電壓補償之電路的電路圖。 圖6C為根據某些實施例，用以操作圖6A所示電路之控制信號的時序圖。 圖7為流程圖，其繪示在一電致發光顯示器中進行電壓補償的方法。

Claims (19)

  1. 一種電致發光(EL)顯示器的電壓補償電路，包含： 一子像素單元，該子像素單元包含： 一電致發光(EL)裝置； 一第一電容器，耦接於該EL裝置，用以儲存與該EL裝置相關聯的一資料；以及 一電晶體，包含一閘極，耦接至該第一電容器的一第一端，以及一終端，耦接至該電容器的一第二端； 一阻抗負載，耦接於該子像素單元，該阻抗負載包含一第二電容器，其電容值高於該第一電容器的電容值；以及 一開關，選擇性地耦接於該阻抗負載或斷開，將該子像素單元耦接至相應的一電流槽或與該電流槽斷開。
  2. 如請求項1所述之電路，其中該子像素單元還包含另一電晶體，用以在一第一階段中，重置該電晶體之該閘極的一電壓位準。
  3. 如請求項2所述之電路，其中該另一電晶體還用以在一第二階段中，接收與該EL裝置相關聯的一資料。
  4. 如請求項3所述之電路，其中該第二電容器用以在該第二階段中，保持該電晶體之該終端的一電壓位準，該電壓位準等於該終端在該第一階段中的電壓位準。
  5. 如請求項3所述之電路，其中該子像素單元還包含又一電晶體，分別耦接於該電晶體與一供應電壓，該又一電晶體用以於一第三階段中，使一電流流經該EL裝置。
  6. 如請求項5所述之電路，其中該第二電容器用以在該第三階段中，保持該電晶體之該閘極與該終端間的一電壓差異，該電壓差異等於其於該第二階段中的電壓差異。
  7. 如請求項5所述之電路，其中該電流的強度與該電晶體的閾值電壓無關。
  8. 如請求項2所述之電路，其中該子像素單元還包含 又一電晶體，分別耦接於該電晶體與該阻抗負載，用以在該第一階段中，於該電晶體之該終端建立與該電晶體的閾值電壓相關的補償電壓。
  9. 一種電致發光(EL)顯示器，包含： 多個像素單元，呈矩陣排列，且每一該像素單元包含多個子像素單元；以及 一電壓補償電路，包含： 該等子像素單元，每一該子像素單元包含： 一電致發光(EL)裝置； 一第一電容器，耦接於該EL裝置，用以儲存與該EL裝置相關聯的一資料；以及 一電晶體，包含一閘極，耦接至該第一電容器的一第一端，以及一終端，耦接至該電容器的一第二端； 一阻抗負載，耦接於該子像素單元，該阻抗負載包含一第二電容器，其電容值高於該第一電容器的電容值；以及 一開關，選擇性地耦接於該阻抗負載或斷開，將該子像素單元耦接至相應的一電流槽或與該電流槽斷開。
  10. 如請求項9所述之EL顯示器，其中該子像素單元還包含一電晶體，用以在一第一階段中，重置該電晶體之該閘極的一電壓位準。
  11. 如請求項10所述之EL顯示器，其中該電晶體用以在一第二階段中，接收與該EL裝置相關聯的一資料。
  12. 如請求項11所述之EL顯示器，其中該第二電容器用以在該第二階段中，保持該電晶體之該第一終端的一電壓位準，使其實質上等於其在該第一階段中的電壓位準。
  13. 如請求項11所述之EL顯示器，其中該子像素單元還包含另一電晶體，用以於一第三階段中，使一電流流經該EL裝置。
  14. 如請求項13所述之EL顯示器，，其中該第二電容器用以在該第三階段中，保持該電晶體之該閘極與該第一終端間的一電壓差異，使其實質上等於該第二階段中的電壓差異。
  15. 如請求項13所述之EL顯示器，其中該電流的強度與該電晶體之該閾值電壓無關。
  16. 如請求項10所述之EL顯示器，其中該子像素單元還包含 另一電晶體，用以在該第一階段中，於該電晶體之該第一終端建立與該電晶體之一閾值電壓相關的補償電壓。
  17. 如請求項16所述之EL顯示器，其中該另一電晶體包含一終端，且該開關用以透過該阻抗負載將該終端選擇性地連接至該電流槽。
  18. 如請求項17所述之EL顯示器，還包含又一電晶體，用以回應該第一控制信號以重置該電晶體之該閘極的一電壓位準。
  19. 一種於一電致發光(EL)顯示器中進行電壓補償的方法，該EL顯示器包含一像素單元陣列，每一像素單元包含一EL裝置、電晶體及一第一電容器，該方法包含： 提供一開關，以透過與一像素單元相關聯的一阻抗負載將該一像素單元選擇性地連接至一電流槽; 將該電晶體一閘極之電壓位準重置為一參考電壓； 在該電晶體之一第一終端建立與該電晶體之一閾值電壓相關聯的一補償電壓； 將與該EL裝置相關聯的資料儲存於該第一電容器中，並利用該阻抗負載中的第二電容器保持該第一終端之一電壓位準；以及 使一電流透過該電晶體流經該EL裝置，該電流的強度與該電晶體之該閾值電壓無關。
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