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CN108074534A - 像素电路及包含该像素电路的电致发光显示器 - Google Patents

像素电路及包含该像素电路的电致发光显示器 Download PDF

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Publication number
CN108074534A
CN108074534A CN201710797111.3A CN201710797111A CN108074534A CN 108074534 A CN108074534 A CN 108074534A CN 201710797111 A CN201710797111 A CN 201710797111A CN 108074534 A CN108074534 A CN 108074534A
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CN
China
Prior art keywords
transistor
mrow
control signal
pixel unit
current
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Granted
Application number
CN201710797111.3A
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CN108074534B (zh
Inventor
郑士嵩
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Taizhou Guanyu Technology Co Ltd
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INT Tech Co Ltd
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract

一种像素电路，包含一电致发光EL装置、一晶体管、一第一电容器及一第二电容器。所述晶体管耦接于一供应电压和该EL装置之间，其包含耦接至一第一节点的一栅极以及耦接至一第二节点的一端部。所述第一电容器耦接于该第一节点和第二节点之间，其是用以回应一第一控制信号，而将晶体管的栅极重置为供应电压。所述第二电容器包含耦接至该第二节点的第一端、以及用以接收一第二控制信号的第二端，其是用以回应该第二控制信号，以在晶体管的端部建立与该晶体管的阈值电压相关的一补偿电压。上述晶体管用以使一电流流经该EL装置。所述电流的强度与该晶体管的阈值电压无关。

Description

像素电路及包含该像素电路的电致发光显示器
技术领域
本发明涉及显示器的电路领域，特别是一种像素电路及包含所述像素电路的电致发光显示器。
背景技术
电致发光(EL)显示器，譬如主动矩阵有机发光二极管(active matrix organiclight emitting diode，AMOLED)显示器，可包含一像素阵列。所述像素中的每一像素可包含一EL装置、用以传输含有与亮度相关的信息的一开关晶体管、以及用以驱动该EL装置使其根据该数据而发光的一驱动晶体管。虽然此种EL显示器具备电力消耗较低的优点，但半导体制备过程中的制程因素却可能使多个像素间的显示不均匀。因此，相关领域需要一种能够解决上述问题的电路。
发明内容
本发明实施例提出一种像素电路，其包含一电致发光(EL)装置、一晶体管、一第一电容器及一第二电容器。该晶体管耦接于一供应电压和该EL装置之间，其包含耦接至一第一节点的一栅极以及耦接至一第二节点的一端部。该第一电容器耦接于该第一节点和第二节点之间，其是用以回应一第一控制信号，而将晶体管的栅极重置为供应电压。该第二电容器包含耦接至该第二节点的第一端、以及用以接收一第二控制信号的第二端，其是用以回应该第二控制信号，以在晶体管的端部建立与该晶体管的阈值电压相关的一补偿电压。该晶体管用以使一电流流经该EL装置。该电流的强度与该晶体管的阈值电压无关。
在一实施例中，该电路还包含另一晶体管，用以回应该第一控制信号，以提供该供应电压至该晶体管的该栅极。
在另一实施例中，该电路还包含另一晶体管，用以回应一第三控制信号，以接收与该EL装置相关的数据。
在又一实施例中，该电路还包含另一晶体管，用以回应一第四控制信号，以使该电流流经该EL装置。
在另一实施例中，该电流的强度是该第一与第二电容器每一者的电容的函数。
在又另一实施例中，该晶体管包含一p-型晶体管，且该电流可表示为：
其中Isd表示该电流的强度，k为一常数，C1及C2分别表示该第一与第二晶体管的电容，VDD表示供应电压，且Vdata表示与该EL装置相关的数据的电压电平。
在又一实施例中，该晶体管包含一n-型晶体管，且该电流可表示为：
其中Isd表示该电流的强度，k为一常数，C1及C2分别表示该第一与第二晶体管的电容，VSS表示供应电压，且Vdata表示与该EL装置相关的数据的电压电平。
在一实施例中，该第一控制信号的脉冲宽度等于一讯框时间。
本发明的某些实施例提供一电致发光显示器，其包含一像素单元阵列。此像素单元阵列中的每一像素单元包含一电致发光(EL)装置、一晶体管、一第一电容器及一第二电容器。该晶体管耦接于一供应电压和该EL装置之间，其包含耦接至一第一节点的一栅极以及耦接至一第二节点的一端部。该第一电容器耦接于该第一节点和第二节点之间，其是用以回应一第一控制信号，而将晶体管的栅极重置为供应电压。该第二电容器包含耦接至该第二节点的第一端、以及用以接收一第二控制信号的第二端，其是用以回应该第二控制信号，以在晶体管的端部建立与该晶体管的阈值电压相关的一补偿电压。该晶体管用以使一电流流经该EL装置。该电流的强度与该晶体管的阈值电压无关。
本发明的实施例亦提供一种在电致发光(EL)显示器中进行电压补偿的方法，所述的EL显示器包含一像素单元阵列，其中的每一像素单元包含一晶体管、一第一电容器及一第二电容器。所述方法包含：回应一第一控制信号，以将该晶体管栅极的电压电平重置为一供应电压；回应一第二控制信号，以在该晶体管的的一端部建立与该晶体管的阈值电压相关的一补偿电压；回应一第三控制信号，以将与该EL装置相关的数据储存于该第一与第二电容器中；以及回应一第四控制信号，以使一电流通过该晶体管而流经该EL装置。该电流的强度与该晶体管的阈值电压无关。
附图说明
在阅读了下文实施方式以及附随附图时，能够最佳地理解本公开的多种实施方式。应注意到，根据本领域的标准作业习惯，图中的各种特征并未依比例绘制。事实上，为了能够清楚地进行描述，可能会刻意地放大或缩小某些特征的尺寸。
图1为根据一实施例的显示器的区域图。
图2为根据一实施例，图1所示显示器中一子像素单元的电路图。
图3A及3B示出的根据某些实施例，于第一阶段中操作图2所示电路的方法。
图4A及4B示出的根据某些实施例，于第二阶段中操作图2所示电路的方法。
图5A及5B示出的根据某些实施例，于第三阶段中操作图2所示电路的方法。
图6为根据某些实施例，一子像素单元的电路结构附图。
图7A为根据另一实施例，一显示器中一子像素单元的电路图。
图7B为根据某些实施例，用以操作图7A所示电路的控制信号的波形图。
图8为流程图，其示出的在一电致发光显示器中进行电压补偿的方法。
附图标记说明：
10 显示器
12 主动区域
14 栅极驱动器
15 源极驱动器
16 电源驱动器
18 DC偏压源
20、60～62 子像素单元
28 EL装置
81～88 步骤
A、B 节点
C1、C2 电容器
DATA 数据
Isd 电流
M 行
N 列
P 像素单元
pw 脉冲宽度
S1～S3、EM 信号
t1～t5 时间点
T1～T7 晶体管
VDD 工作电压
Vref 参考电压
VSS 接地电压
具体实施方式
以下公开内容提供了多种实施方式或例示，其能用以实现本公开内容的不同特征。下文所述的元件与配置的具体例子是用以简化本公开内容。当可想见，这些叙述仅为例示，其本意并非用于限制本公开内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包含某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包含某些实施例其中还有而外的元件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本公开内容可能会在多个实施例中重复使用元件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
此外，当可理解，若将一部件描述为与另一部件「连接(connected to)」或「耦接(耦接至)」，则两者可直接连接或耦接，或两者间可能出现其他中间(intervening)部件。
在下文说明中，当一装置属于正缘触发(active high)，将一信号拉高(asserted)至高逻辑值，以启动该相应装置。反之，将该信号拉低(deasserted)至低逻辑值，以停用该相应装置。然而当该装置属于负缘触发(active low)时，将该信号拉至低逻辑值，以启动该装置，并将其拉至高逻辑值，以停用该装置。
图1为根据一实施例的显示器10的区域图。显示器10可以是一电致发光(EL)显示器，譬如主动矩阵有机发光二极管(AMOLED)显示器。
参照图1，显示器10包含主动区域12、栅极驱动器14及源极驱动器15。主动区域12包含一像素单元阵列，举例来说，可将多个像素单元P排列成N×M的矩阵。栅极驱动器14经由N条扫描线将控制信号S1、S2、S3及EM提供给N列像素单元P。源极驱动器15将数据提供给M行像素单元P中的一所选像素。此外，一电源驱动器16在VDD及VSS的电源中提供供应电压至该主动区域12，而一DC偏压源18则提供一参考电压Vref，例如接地电压，至该主动区域12。在一实施例中，VDD约为5伏特(5V)，VSS约为-5V，而Vref则约为0V。
主动区域12中的每一像素单元P包含三个子像素单元，其可用以显示红色(R)、绿色(G)及蓝色(B)。在其他实施例中，例如，子像素渲染(sub-pixel rendering，SPR)感应器，子像素单元的数目不限于三。在本实施例中，三种子像素单元是沿着列的方向排列。因此，源极驱动器15的数据线数目为3×M。
图2是根据一实施例，图1所示显示器10中一例示性子像素单元20的电路图。
参照图2，所述电路包含EL装置28、多个晶体管T1至T7、第一电容器C1与第二电容器C2。举例来说，EL装置28包含一电流驱动部件，其可包含一有机发光二极管(organiclight emitting diode，OLED)、微LED或量子点LED(quantum dot LED，QLED)。第一电容器C1与第二电容器C2作为储存电容器。晶体管T4作为驱动晶体管，其可根据储存于电容器C1与C2中的数据来驱动EL装置28。在本实施例中，晶体管T1至T7中每一个晶体管包含一p-型薄膜晶体管(thin film transistor、TFT)或一p-型金氧半(p-型metal-oxide-semiconductor，PMOS)晶体管。
晶体管T1的栅极用以接收控制信号S1。晶体管T1的漏极耦接至节点A。此外，晶体管T3的栅极亦可接收该第一控制信号S1。晶体管T3的源极接收一供应电压VDD。晶体管T3的漏极耦接至晶体管T1的源极。本发明所述技术领域中技术人员当可理解，MOS晶体管的漏极与源极端可互换，其是取决于施加于该处的电压电平。
此外，晶体管T2的栅极亦接收上述第一控制信号S1。晶体管T2的源极耦接至晶体管T1的源极，并因而耦接至晶体管T3的漏极。晶体管T4的栅极耦接至第一节点A，并因而耦接至晶体管T1的漏极。晶体管T4的一端部，例如源极，耦接至第二节点B。晶体管T4的另一端部，例如漏极，耦接至晶体管T2的漏极。
所述的第一电容器C1耦接于第一节点A和第二节点B之间。此外，第二电容器C2的第一端耦接至第二节点B，且第二端用以接收一第二控制信号S2。
再者，晶体管T5的栅极接收一第三控制信号S3。晶体管T5的源极从源极驱动器15接收一相应数据线上的数据(标记为"DATA")。晶体管T5的漏极耦接至第一节点A，并因而耦接至晶体管T4的栅极与晶体管T1的漏极。此外，晶体管T6与T7两者的栅极接收第四控制信号EM。晶体管T6的源极接收VDD。晶体管T6的漏极耦接至第二节点B，并因而耦接至晶体管T4的源极。此外，晶体管T7的源极耦接至晶体管T6与T4两者的漏极。晶体管T7的漏极耦接至EL装置28的阳极。EL装置28的阴极接收另一供应电压VSS。
图3A及3B示出的根据某些实施例，在第一阶段中，操作图2所示电路20的方法。
参照图3A，基于p-型晶体管T1至T7，控制信号S1、S3及EM经设定为负缘触发。在时间点t1，将第一控制信号S1拉至负缘(falling edge)，第二控制信号S2保持在低逻辑电平，而位于高逻辑电平的第三与第四控制信号S3与EM则未经拉动。如此一来，参照图3B，晶体管T1、T2、T3被开启，而晶体管T5至T7则被关闭(图中以"×"符号标记)。由于晶体管T1与T3是开启的，节点A的电压电平(下文标记为VA)被拉高至VDD。此外，在前一阶段(下文参照图5A与5B所述的第三阶段)中，接点B的电压电平(下文标记为VA)为VDD(因为晶体管T6被开启)于第一阶段中一开始保持此一电压电平。由于驱动晶体管的栅极与源极的电压电平(分别标记为Vg与Vs)是VDD，晶体管T4被关闭。
在时间点t2，第二控制信号S2变成逻辑高位，第一控制信号S1保持在低逻辑电平，且第三与第四控制信号S3与EM并未经拉动。随着在时间点t2，第二控制信号S2在第二电容器C2的耦合功能作用下由低电平变换至高电平，原本处于VDD的VB被拉高到高于VDD+|Vth4|的电平，其中|Vth4|为晶体管T4的阈值电压。于是，晶体管T4被开启。如此一来，在第一阶段中，将VA(或晶体管T4的Vg)重置为VDD。此外，在VB(或晶体管T4的Vs)建立了一补偿电压。可通过调整第一控制信号S1的脉冲宽度pw，而使VB或Vs达到理想的数值，即VDD+|Vth4|。第一控制信号S1的脉冲宽度pw是指第一控制信号S1保持触发的时期。举例来说，在图3A所示的实施例中，第一控制信号S1的脉冲宽度pw为时间点t1至t3。在本实施例中，与驱动晶体管T4相关的|Vth4|代表补偿电压。用以建立补偿电压的时间(下称「补偿时间」)和第一控制信号S1的脉冲宽度pw成正比。另，第一控制信号S1的脉冲宽度pw不会受限于显示器10的分辨率。随着补偿时间变长，VB的电压电平会更接近第二电容器C2的饱和电压，如此可提升显示器10的显示品质。所述的补偿时间(或脉冲宽度pw)实际上可与讯框时间一样长。
图4A及4B示出的根据某些实施例，在第二阶段中，操作图2所示电路20的方法。
参照图4A，在时间点t4，第三控制信号S3被拉至负缘，第二控制信号S2保持在高逻辑电平，且第一与第四控制信号S1与EM并未被拉动。如此一来，参照图4B，晶体管T5被开启，晶体管T1至T3被关闭，且晶体管T6与T7则保持在关闭状态。由于晶体管T5被开启，数据被写入至第一节点A。因此，VA(Vg)变成Vdata。此外，当通过第一电容器C1的耦合功能使VA从VDD(第一阶段)变成Vdata(第二阶段)时，VB成为为了便于说明，在本公开内容中，一电容器的元件符号或标记亦用于表示其电容值，且反之亦然。举例来说，虽然上文以元件符号"C1"来表示第一电容器，其亦可用以表示第一电容器的电容值。
图5A及5B示出的根据某些实施例，在第三阶段中，操作图2所示电路20的方法。
参照图5A，在时间点t5，第四控制信号EM被拉至负缘，第二控制信号S2被保持在高逻辑电平，而第一与第三控制信号S1与S3则未经拉动。如此一来，参照图5B，晶体管T6与T7被开启，晶体管T5被关闭，而晶体管T1至T3则被保持在关闭状态。由于晶体管T6被开启，将VB(Vs)由拉至VDD。在第一电容器C1的作用下，VA(Vg)成为
此外，来自供应电源VDD的电流Isd会通过晶体管T6、T4与T7而流经EL装置28到达VSS。可将上述电流Isd表达为下列方程式(1)。
|Isd|＝k×(|Vsg|-|Vth4|)2 方程式(1)
其中k为一常数，Vsg表示晶体管T4的源极至栅极电压。
由于将其带入方程式(1)，可将电流Isd重新表示如下。
上述电流Isd与晶体管T4的阈值电压无关。由于方程式(2)不含Vth参数，可提升显示器10的显示品质。
图6为根据某些实施例，一子像素单元的附图。参照图6，所述电路结构与上文参照图2所述者类似，不同之处例如在于，沿着行的方向排列的子像素单元配置成接收被提供给位于下一列上紧邻的一子像素单元的第四控制信号EM来作为第二控制信号S2。为了便于讨论，此处仅示出的例示性的子像素单元60、61与62。如此一来，原本依图3A、4A或5A所示，会被提供到位于第n列上的子像素单元的第二控制信号S2[n]就会被提供到位于第(n+1)列上的子像素单元的第四控制信号EM[n+1]所取代。具体来说。对子像素单元60而言，提供给子像素单元61的第四控制信号EM[n+1]亦可作为一第二控制信号，所述的第二控制信号是耦接至子像素单元60中第二电容器C2的第二端。除此之外，对于子像素单元61而言，提供给子像素单元62的第四控制信号EM[n+2]亦可作为耦接至子像素单元61中第二电容器C2第二端的一第二控制信号。如此一来，可有效地简化控制机制。
图7A示出的根据另一实施例的显示器的子像素单元70的电路图。
参照图7A，所示电路与上文参照图2所示的电路20相似，不同之处在于譬如可利用n-型TFT或n-型金氧半(NMOS)晶体管来取代图2的p-型TFT或PMOS晶体管T1至T7。
具体来说，晶体管T1的栅极接收第一控制信号S1。晶体管T1的漏极耦接至第一节点A。此外，晶体管T3的栅极亦接收上述第一控制信号S1。晶体管T3的源极接收VSS。晶体管T3的漏极耦接至晶体管T1的源极。再者，晶体管T2的栅极亦接收上述第一控制信号S1。晶体管T2的源极耦接至晶体管T1的源极，并因而耦接至晶体管T3的漏极。晶体管T4的栅极耦接至第一节点A，并因而耦接至晶体管T1的漏极。晶体管T4的源极耦接至第二节点B。晶体管T4的漏极耦接至晶体管T2的漏极。
所述的第一电容器C1耦接于第一节点A和第二节点B之间。此外，第二电容器C2的第一端耦接至第二节点B，且第二端用以接收一第二控制信号S2。
再者，晶体管T5的栅极接收一第三控制信号S3。晶体管T5的漏极从源极驱动器15接收一相应数据线上的数据(标记为"DATA")。晶体管T5的源极耦接至第一节点A，并因而耦接至晶体管T4的栅极与晶体管T1的漏极。此外，晶体管T6与T7两者的栅极接收第四控制信号EM。晶体管T6的源极接收VSS。晶体管T6的漏极耦接至第二节点B，并因而耦接至晶体管T4的源极。此外，晶体管T7的源极耦接至晶体管T2与T4两者的漏极。晶体管T7的漏极耦接至EL装置28的阴极。EL装置28的阳极耦接至耦接至VDD。
图7B为根据某些实施例，用以操作图7A所示电路的控制信号的时序图。
参照图7B，控制信号S1、S3与EM和上文参照图3A、4A或5A所述者相似，不同之处在于，例如，由于采用了n-型晶体管T1至T7，图7B的控制信号S1、S3及EM为正缘触发，或拉高至一正缘(rising edge)，而第二控制信号S2相较于图3A、4A或5A所示者为反相。
可将流经图7A的EL装置28的电流Isd表示为下列方程式(3)。
同理，上述电流Isd与晶体管T4的阈值电压无关。由于方程式(3)不涉及Vth参数，可提升显示器10的显示品质。此外，上文参照图6所述的简化控制机制亦可运用于图7A的子像素单元70。
图8为一流程图，示出的在电致发光显示器中进行电压补偿的方法。
参照图8，在操作81，提供一电致发光(EL)显示器。所述EL显示器包含一像素单元阵列，其中的每一像素单元分别包含EL装置、晶体管、第一电容器以及第二电容器。
接着，在操作83，于第一阶段中，回应一第一控制信号，将晶体管栅极的电压电平重置为供应电压。
在操作85，回应一第二控制信号，在晶体管的一端部(源极)建立与晶体管阈值电压相关的一补偿电压。
在操作87，回应一第三控制信号，将与该EL装置相关的数据储存于第一与第二电容器中。
其后，在操作88，回应一第四控制信号，使电流通过晶体管而流经所述EL装置。上述电流的强度与所述晶体管的阈值电压无关。
上文的叙述简要地提出了本发明某些实施例的特征，而使得本发明所属技术领域技术人员能够更全面地理解本公开内容的多种实施方式。本发明所属技术领域技术人员当可明了，其可轻易地利用本公开内容作为基础，来设计或变动其他制程与结构，以实现与此处所述的实施方式相同的目的和/或达到相同的优点。本发明所属技术领域技术人员应当明白，这些均等的实施方式仍属于本公开内容的构思与范围，且其可进行各种变更、替代与变动，而不会悖离本公开内容的构思与范围。

Claims (20)

1.一种像素电路，包含：
一电致发光EL装置；
一晶体管，耦接于一供应电压和该EL装置之间，该晶体管包含耦接至一第一节点的一栅极，以及耦接至一第二节点的一端部；
一第一电容器，耦接于该第一节点和该第二节点之间，用以回应一第一控制信号，而将该晶体管的该栅极重置为该供应电压；以及
一第二电容器，包含耦接至该第二节点的一第一端，以及用以接收一第二控制信号的一第二端，该第二电容器用以回应该第二控制信号，以在该晶体管的该端部建立与该晶体管的一阈值电压相关的一补偿电压，
其中该晶体管用以使一电流流经该EL装置，该电流的强度与该晶体管的该阈值电压无关。
2.如权利要求1所述的电路，还包含另一晶体管，用以回应该第一控制信号，以提供该供应电压给该晶体管的该栅极。
3.如权利要求1所述的电路，还包含另一晶体管，用以回应一第三控制信号，以接收与该EL装置相关的数据。
4.如权利要求1所述的电路，还包含另一晶体管，用以回应一第四控制信号，以使该电流流经该EL装置。
5.如权利要求1所述的电路，其中该电流的强度为该第一与第二电容器各自的一电容的一函数。
6.如权利要求1所述的电路，其中该晶体管包含一p-型晶体管，且该电流可表示为：
<mrow> <mo>|</mo> <mi>I</mi> <mi>s</mi> <mi>d</mi> <mo>|</mo> <mo>=</mo> <mi>k</mi> <mo>&amp;times;</mo> <msup> <mrow> <mo>&amp;lsqb;</mo> <mfrac> <mrow> <mi>C</mi> <mn>2</mn> </mrow> <mrow> <mi>C</mi> <mn>1</mn> <mo>+</mo> <mi>C</mi> <mn>2</mn> </mrow> </mfrac> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mi>V</mi> <mi>D</mi> <mi>D</mi> <mo>-</mo> <mi>V</mi> <mi>d</mi> <mi>a</mi> <mi>t</mi> <mi>a</mi> <mo>)</mo> </mrow> <mo>&amp;rsqb;</mo> </mrow> <mn>2</mn> </msup> </mrow>
其中Isd表示该电流的强度，k为一常数，C1及C2分别表示该第一与第二晶体管的电容，VDD表示该供应电压，且Vdata表示与该EL装置相关的数据的一电压电平。
7.如权利要求1所述的电路，其中该晶体管包含一n-型晶体管，且该电流可表示为：
<mrow> <mo>|</mo> <mi>I</mi> <mi>s</mi> <mi>d</mi> <mo>|</mo> <mo>=</mo> <mi>k</mi> <mo>&amp;times;</mo> <msup> <mrow> <mo>&amp;lsqb;</mo> <mfrac> <mrow> <mi>C</mi> <mn>1</mn> </mrow> <mrow> <mi>C</mi> <mn>1</mn> <mo>+</mo> <mi>C</mi> <mn>2</mn> </mrow> </mfrac> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mi>V</mi> <mi>d</mi> <mi>a</mi> <mi>t</mi> <mi>a</mi> <mo>-</mo> <mi>V</mi> <mi>S</mi> <mi>S</mi> <mo>)</mo> </mrow> <mo>&amp;rsqb;</mo> </mrow> <mn>2</mn> </msup> </mrow>
其中Isd表示该电流的强度，k为一常数，C1及C2分别表示该第一与第二晶体管的电容，VSS表示该供应电压，且Vdata表示与该EL装置相关的数据的一电压电平。
8.如权利要求1所述的电路，其中该第一控制信号的一脉冲宽度等于一讯框时间。
9.一种电致发光显示器，包含：
一像素单元阵列，该像素单元阵列中的每一像素单元包含：
一电致发光EL装置；
一晶体管，耦接于一供应电压和该EL装置之间，包含耦接至一第一节点的一栅极，以及耦接至一第二节点的一端部；
一第一电容器，耦接于该第一节点和该第二节点之间，用以回应一第一控制信号，以将该晶体管的该栅极重置为该供应电压；以及
一第二电容器，包含耦接至该第二节点的一第一端，以及用以接收一第二控制信号的一第二端，该第二电容器用以回应该第二控制信号，以在该晶体管的该端部建立与该晶体管的一阈值电压相关的一补偿电压，
其中该晶体管用以使一电流流经该EL装置，该电流的强度与该晶体管的该阈值电压无关。
10.如权利要求9所述的电致发光显示器，还包含另一晶体管，用以回应该第一控制信号，以提供该供应电压给该晶体管的该栅极。
11.如权利要求9所述的电致发光显示器，还包含另一晶体管，用以回应一第三控制信号，以接收与该EL装置相关的数据。
12.如权利要求9所述的电致发光显示器，还包含另一晶体管，用以回应一第四控制信号，以使该电流流经该EL装置。
13.如权利要求12所述的电致发光显示器，其中该像素单元阵列包含位于第N列上的一第一像素单元，以及位于第(N+1)-列上且紧邻该第一像素单元的一第二像素单元，N为一自然数，且其中该第四控制信号是提供给该第二像素单元，并作为该第一像素单元的该第二控制信号。
14.如权利要求9所述的电致发光显示器，其中该电流的强度为该第一与第二电容器各自的一电容的一函数。
15.如权利要求9所述的电致发光显示器，其中该晶体管包含一p-型晶体管，且该电流可表示为：
<mrow> <mo>|</mo> <mi>I</mi> <mi>s</mi> <mi>d</mi> <mo>|</mo> <mo>=</mo> <mi>k</mi> <mo>&amp;times;</mo> <msup> <mrow> <mo>&amp;lsqb;</mo> <mfrac> <mrow> <mi>C</mi> <mn>2</mn> </mrow> <mrow> <mi>C</mi> <mn>1</mn> <mo>+</mo> <mi>C</mi> <mn>2</mn> </mrow> </mfrac> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mi>V</mi> <mi>D</mi> <mi>D</mi> <mo>-</mo> <mi>V</mi> <mi>d</mi> <mi>a</mi> <mi>t</mi> <mi>a</mi> <mo>)</mo> </mrow> <mo>&amp;rsqb;</mo> </mrow> <mn>2</mn> </msup> </mrow>
其中Isd表示该电流的强度，k为一常数，C1及C2分别表示该第一与第二晶体管的电容，VDD表示该供应电压，且Vdata表示与该EL装置相关的数据的一电压电平。
16.如权利要求9所述的电致发光显示器，其中该晶体管包含一n-型晶体管，且该电流可表示为：
<mrow> <mo>|</mo> <mi>I</mi> <mi>s</mi> <mi>d</mi> <mo>|</mo> <mo>=</mo> <mi>k</mi> <mo>&amp;times;</mo> <msup> <mrow> <mo>&amp;lsqb;</mo> <mfrac> <mrow> <mi>C</mi> <mn>1</mn> </mrow> <mrow> <mi>C</mi> <mn>1</mn> <mo>+</mo> <mi>C</mi> <mn>2</mn> </mrow> </mfrac> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mi>V</mi> <mi>d</mi> <mi>a</mi> <mi>t</mi> <mi>a</mi> <mo>-</mo> <mi>V</mi> <mi>S</mi> <mi>S</mi> <mo>)</mo> </mrow> <mo>&amp;rsqb;</mo> </mrow> <mn>2</mn> </msup> </mrow>
其中Isd表示该电流的强度，k为一常数，C1及C2分别表示该第一与第二晶体管的电容，VSS表示该供应电压，且Vdata表示与该EL装置相关的数据的一电压电平。
17.如权利要求9所述的电致发光显示器，其中该第一控制信号的一脉冲宽度等于一讯框时间。
18.一种电致发光(EL)显示器的电压补偿方法，其中该EL显示器包含一像素单元阵列，该像素单元阵列的每一像素单元包含一EL装置、一晶体管、一第一电容器及一第二电容器，该方法包含：
将位于该晶体管的一栅极的一电压电平重置为一供应电压，以回应一第一控制信号；
在该晶体管的一端部建立与该晶体管的一阈值电压相关的一补偿电压，以回应一第二控制信号；
将与该EL装置相关的数据储存于该第一与第二电容器，以回应一第三控制信号；以及
使一电流通过该晶体管而流经该EL装置体，以回应一第四控制信号，该电流的强度与该晶体管的该阈值电压无关。
19.如权利要求18所述的方法，其中该像素单元阵列包含位于第N列上的一第一像素单元，以及位于第(N+1)-列上且紧邻该第一像素单元的一第二像素单元，N为一自然数，该方法还包含：
利用提供给该第二像素单元的该第四控制信号作为该第一像素单元的该第二控制信号。
20.如权利要求19所述的方法，还包含：
提供具有实质上等于一讯框时间的一脉冲宽度的该第一控制信号。
CN201710797111.3A 2016-11-14 2017-09-06 像素电路及包含该像素电路的电致发光显示器 Active CN108074534B (zh)

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