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TW201818379A - 像素電路及包含該像素電路之電致發光顯示器 - Google Patents

像素電路及包含該像素電路之電致發光顯示器 Download PDF

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Publication number
TW201818379A
TW201818379A TW106129401A TW106129401A TW201818379A TW 201818379 A TW201818379 A TW 201818379A TW 106129401 A TW106129401 A TW 106129401A TW 106129401 A TW106129401 A TW 106129401A TW 201818379 A TW201818379 A TW 201818379A
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TW
Taiwan
Prior art keywords
transistor
control signal
current
pixel unit
node
Prior art date
Application number
TW106129401A
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English (en)
Other versions
TWI673693B (zh
Inventor
鄭士嵩
Original Assignee
創王光電股份有限公司
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Publication of TW201818379A publication Critical patent/TW201818379A/zh
Application granted granted Critical
Publication of TWI673693B publication Critical patent/TWI673693B/zh

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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract

一種像素電路，包含一電致發光(EL)裝置、一電晶體、一第一電容器及一第二電容器。所述電晶體耦接於一供應電壓和該EL裝置之間，其包含耦接至一第一節點的一閘極以及耦接至一第二節點的一端部。所述第一電容器耦接於該第一節點和第二節點之間，其係用以回應一第一控制信號，而將電晶體之閘極重置為供應電壓。所述第二電容器包含耦接至該第二節點的第一端、以及用以接收一第二控制信號的第二端，其係用以回應該第二控制信號，以在電晶體的端部建立與該電晶體之閾值電壓相關的一補償電壓。上述電晶體用以使一電流流經該EL裝置。所述電流的強度與該電晶體的閾值電壓無關。

Description

像素電路及包含該像素電路之電致發光顯示器
本發明是關於顯示器的電路領域，特別是一種像素電路及包含所述像素電路的電致發光顯示器。
電致發光(EL)顯示器，譬如主動矩陣有機發光二極體(active matrix organic light emitting diode，AMOLED)顯示器，可包含一像素陣列。該些像素中的每一像素可包含一EL裝置、用以傳輸含有與亮度相關之資訊的一開關電晶體、以及用以驅動該EL裝置使其根據該資料而發光的一驅動電晶體。雖然此種EL顯示器具備電力消耗較低的優點，但半導體製備過程中的製程因素卻可能使多個像素間的顯示不均勻。因此，相關領域需要一種能夠解決上述問題的電路。
本發明實施例提出一種像素電路，其包含一電致發光(EL)裝置、一電晶體、一第一電容器及一第二電容器。該電晶體耦接於一供應電壓和該EL裝置之間，其包含耦接至一第一節點的一閘極以及耦接至一第二節點的一端部。該第一電容器耦接於該第一節點和第二節點之間，其係用以回應一第一控制信號，而將電晶體之閘極重置為供應電壓。該第二電容器包含耦接至該第二節點的第一端、以及用以接收一第二控制信號的第二端，其係用以回應該第二控制信號，以在電晶體的端部建立與該電晶體之閾值電壓相關的一補償電壓。該電晶體用以使一電流流經該EL裝置。該電流的強度與該電晶體的閾值電壓無關。 在一實施例中，該電路還包含另一電晶體，用以回應該第一控制信號，以提供該供應電壓至該電晶體之該閘極。 在另一實施例中，該電路還包含另一電晶體，用以回應一第三控制信號，以接收與該EL裝置相關之資料。 在又一實施例中，該電路還包含另一電晶體，用以回應一第四控制信號，以使該電流流經該EL裝置。 在另一實施例中，該電流的強度是該第一與第二電容器每一者之電容的函數。 在又另一實施例中，該電晶體包含一p-型電晶體，且該電流可表示為：×(VDD-Vdata)]2 其中Isd表示該電流之強度，k為一常數，C1及C2分別表示該第一與第二電晶體的電容，VDD表示供應電壓，且Vdata表示與該EL裝置相關之資料的電壓位準。 在又一實施例中，該電晶體包含一n-型電晶體，且該電流可表示為：×(Vdata-VSS)]2 其中Isd表示該電流之強度，k為一常數，C1及C2分別表示該第一與第二電晶體的電容，VSS表示供應電壓，且Vdata表示與該EL裝置相關之資料的電壓位準。 在一實施例中，該第一控制信號的脈衝寬度等於一訊框時間。 本發明的某些實施例提供一電致發光顯示器，其包含一像素單元陣列。 此像素單元陣列中的每一像素單元包含一電致發光(EL)裝置、一電晶體、一第一電容器及一第二電容器。該電晶體耦接於一供應電壓和該EL裝置之間，其包含耦接至一第一節點的一閘極以及耦接至一第二節點的一端部。該第一電容器耦接於該第一節點和第二節點之間，其係用以回應一第一控制信號，而將電晶體之閘極重置為供應電壓。該第二電容器包含耦接至該第二節點的第一端、以及用以接收一第二控制信號的第二端，其係用以回應該第二控制信號，以在電晶體的端部建立與該電晶體之閾值電壓相關的一補償電壓。該電晶體用以使一電流流經該EL裝置。該電流的強度與該電晶體的閾值電壓無關。 本發明的實施例亦提供一種在電致發光(EL)顯示器中進行電壓補償的方法，所述的EL顯示器包含一像素單元陣列，其中的每一像素單元包含一電晶體、一第一電容器及一第二電容器。所述方法包含：回應一第一控制信號，以將該電晶體閘極的電壓位準重置為一供應電壓；回應一第二控制信號，以在該電晶體的的一端部建立與該電晶體之閾值電壓相關的一補償電壓；回應一第三控制信號，以將與該EL裝置相關之資料儲存於該第一與第二電容器中；以及回應一第四控制信號，以使一電流透過該電晶體而流經該EL裝置。該電流的強度與該電晶體的閾值電壓無關。
以下揭示內容提供了多種實施方式或例示，其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，這些敘述僅為例示，其本意並非用於限制本揭示內容。舉例來說，在下文的描述中，將一第一特徵形成於一第二特徵上或之上，可能包含某些實施例其中所述的第一與第二特徵彼此直接接觸；且也可能包含某些實施例其中還有而外的元件形成於上述第一與第二特徵之間，而使得第一與第二特徵可能沒有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚的目的，且其本身不代表所討論的不同實施例和/或組態之間的關係。 此外，當可理解，若將一部件描述為與另一部件「連接(connected to)」或「耦接(耦接至)」，則兩者可直接連接或耦接，或兩者間可能出現其他中間(intervening)部件。 在下文說明中，當一裝置屬於正緣觸發(active high)，將一信號拉高(asserted)至高邏輯值，以啟動該相應裝置。反之，將該信號拉低(deasserted)至低邏輯值，以停用該相應裝置。然而當該裝置屬於負緣觸發(active low)時，將該信號拉至低邏輯值，以啟動該裝置，並將其拉至高邏輯值，以停用該裝置。 圖1為根據一實施例的顯示器10之區塊圖。顯示器10可以是一電致發光(EL)顯示器，譬如主動矩陣有機發光二極體(AMOLED)顯示器。 參照圖1，顯示器10包含主動區域12、閘極驅動器14及源極驅動器15。主動區域12包含一像素單元陣列，舉例來說，可將多個像素單元P排列成N×M的矩陣。閘極驅動器14經由N條掃描線將控制信號S1、S2、S3及EM提供給N列像素單元P。源極驅動器15將資料提供給M行像素單元P中的一所選像素。此外，一電源驅動器16在VDD及VSS的電源中提供供應電壓至該主動區域12，而一DC偏壓源18則提供一參考電壓Vref，例如接地電壓，至該主動區域12。在一實施例中，VDD約為5伏特(5V)，VSS約為-5V，而Vref則約為0V。 主動區域12中的每一像素單元P包含三個子像素單元，其可用以顯示紅色(R)、綠色(G)及藍色(B)。在其他實施例中，例如，子像素渲染(sub-pixel rendering，SPR)感應器，子像素單元的數目不限於三。在本實施例中，三種子像素單元係沿著列的方向排列。因此，源極驅動器15的資料線數目為3×M。 圖2是根據一實施例，圖1所示顯示器10中一例示性子像素單元20的電路圖。 參照圖2，所述電路包含EL裝置28、多個電晶體T1至T7、第一電容器C1與第二電容器C2。舉例來說，EL裝置28包含一電流驅動部件，其可包含一有機發光二極體(organic light emitting diode，OLED)、微LED或量子點LED(quantum dot LED，QLED)。第一電容器C1與第二電容器C2作為儲存電容器。電晶體T4作為驅動電晶體，其可根據儲存於電容器C1與C2中的資料來驅動EL裝置28。在本實施例中，電晶體T1至T7中每一個電晶體包含一p-型薄膜電晶體(thin film transistor、TFT)或一p-型金氧半(p-型metal-oxide-semiconductor，PMOS)電晶體。 電晶體T1的閘極用以接收控制信號S1。電晶體T1的汲極耦接至節點A。此外，電晶體T3的閘極亦可接收該第一控制信號S1。電晶體T3的源極接收一供應電壓VDD。電晶體T3的汲極耦接至電晶體T1的源極。本發明所述技術領域中具有通常知識者當可理解，MOS電晶體的汲極與源極端可互換，其係取決於施加於該處的電壓位準。 此外，電晶體T2的閘極亦接收上述第一控制信號S1。電晶體T2的源極耦接至電晶體T1的源極，並因而耦接至電晶體T3的汲極。電晶體T4的閘極耦接至第一節點A，並因而耦接至電晶體T1的汲極。電晶體T4的一端部，例如源極，耦接至第二節點B。電晶體T4的另一端部，例如汲極，耦接至電晶體T2的汲極。 所述的第一電容器C1耦接於第一節點A和第二節點B之間。此外，第二電容器C2的第一端耦接至第二節點B，且第二端用以接收一第二控制信號S2。 再者，電晶體T5的閘極接收一第三控制信號S3。電晶體T5的源極從源極驅動器15接收一相應資料線上的資料(標記為"DATA")。電晶體T5的汲極耦接至第一節點A，並因而耦接至電晶體T4之閘極與電晶體T1的汲極。此外，電晶體T6與T7兩者的閘極接收第四控制信號EM。電晶體T6的源極接收VDD。電晶體T6的汲極耦接至第二節點B，並因而耦接至電晶體T4的源極。此外，電晶體T7的源極耦接至電晶體T6與T4兩者的汲極。電晶體T7的汲極耦接至EL裝置28的陽極。EL裝置28的陰極接收另一供應電壓VSS。 圖3A及3B繪示根據某些實施例，在第一階段中，操作圖2所示電路20的方法。 參照圖3A，基於p-型電晶體T1至T7，控制信號S1、S3及EM經設定為負緣觸發。在時間點t1，將第一控制信號S1拉至負緣(falling edge)，第二控制信號S2保持在低邏輯位準，而位於高邏輯位準的第三與第四控制信號S3與EM則未經拉動。如此一來，參照圖3B，電晶體T1、T2、T3被開啟，而電晶體T5至T7則被關閉(圖中以"×"符號標記)。由於電晶體T1與T3是開啟的，節點A的電壓位準(下文標記為VA)被拉高至VDD。此外，在前一階段（下文參照圖5A與5B所述的第三階段）中，接點B的電壓位準(下文標記為VA)為VDD（因為電晶體T6被開啟）於第一階段中一開始保持此一電壓位準。由於驅動電晶體之閘極與源極的電壓位準(分別標記為Vg與Vs)是VDD，電晶體T4被關閉。 在時間點t2，第二控制信號S2變成邏輯高位，第一控制信號S1保持在低邏輯位準，且第三與第四控制信號S3與EM並未經拉動。隨著在時間點t2，第二控制信號S2在第二電容器C2的耦合功能作用下由低位準變換至高位準，原本處於VDD的VB被拉高到高於VDD+的位準，其中為電晶體T4的閾值電壓。於是，電晶體T4被開啟。如此一來，在第一階段中，將VA(或電晶體T4的Vg)重置為VDD。此外，在VB(或電晶體T4的Vs)建立了一補償電壓。可藉由調整第一控制信號S1的脈衝寬度pw，而使VB或Vs達到理想的數值，即VDD+。第一控制信號S1的脈衝寬度pw係指第一控制信號S1保持觸發的時期。舉例來說，在圖3A所示的實施例中，第一控制信號S1的脈衝寬度pw為時間點t1至t3。在本實施例中，與驅動電晶體T4相關的代表補償電壓。用以建立補償電壓的時間(下稱「補償時間」)和第一控制信號S1的脈衝寬度pw成正比。另，第一控制信號S1的脈衝寬度pw不會受限於顯示器10的解析度。隨著補償時間變長，VB的電壓位準會更接近第二電容器C2的飽和電壓，如此可提升顯示器10的顯示品質。所述的補償時間(或脈衝寬度pw)實際上可與訊框時間一樣長。 圖4A及4B繪示根據某些實施例，在第二階段中，操作圖2所示電路20的方法。 參照圖4A，在時間點t4，第三控制信號S3被拉至負緣，第二控制信號S2保持在高邏輯位準，且第一與第四控制信號S1與EM並未被拉動。如此一來，參照圖4B，電晶體T5被開啟，電晶體T1至T3被關閉，且電晶體T6與T7則保持在關閉狀態。由於電晶體T5被開啟，資料被寫入至第一節點A。因此，VA(Vg)變成Vdata。此外，當藉由第一電容器C1的耦合功能使VA從VDD(第一階段)變成Vdata(第二階段)時，VB成為VDD++[×(Vdata-VDD)]。為了便於說明，在本揭示內容中，一電容器的元件符號或標記亦用於表示其電容值，且反之亦然。舉例來說，雖然上文以元件符號"C1"來表示第一電容器，其亦可用以表示第一電容器的電容值。 圖5A及5B繪示根據某些實施例，在第三階段中，操作圖2所示電路20的方法。 參照圖5A，在時間點t5，第四控制信號EM被拉至負緣，第二控制信號S2被保持在高邏輯位準，而第一與第三控制信號S1與S3則未經拉動。如此一來，參照圖5B，電晶體T6與T7被開啟，電晶體T5被關閉，而電晶體T1至T3則被保持在關閉狀態。由於電晶體T6被開啟，將VB (Vs)由VDD++[×(Vdata-VDD)]拉至VDD。在第一電容器C1的作用下，VA (Vg)成為Vdata – {+[×(Vdata-VDD)]}。 此外，來自供應電源VDD的電流Isd會透過電晶體T6、T4與T7而流經EL裝置28到達VSS。可將上述電流Isd表達為下列方程式(1)。 2 方程式(1) 其中k為一常數，Vsg表示電晶體T4之源極至閘極電壓。 由於Vsg = Vs – Vg = VB – VA =+[×(VDD-Vdata)]，將其帶入方程式(1)，可將電流Isd重新表示如下。×(VDD-Vdata)]2 方程式(2) 上述電流Isd與電晶體T4之閾值電壓無關。由於方程式(2)不含Vth參數，可提升顯示器10的顯示品質。 圖6為根據某些實施例，一子像素單元的圖式。參照圖6，所述電路結構與上文參照圖2所述者類似，不同之處例如在於，沿著行的方向排列之子像素單元配置成接收被提供給位於下一列上緊鄰的一子像素單元的第四控制信號EM來作為第二控制信號S2。為了便於討論，此處僅繪示例示性的子像素單元60、61與62。如此一來，原本依圖3A、4A或5A所示，會被提供到位於第n列上之子像素單元的第二控制信號S2[n]就會被提供到位於第(n+1)列上之子像素單元的第四控制信號EM[n+1]所取代。具體來說。對子像素單元60而言，提供給子像素單元61的第四控制信號EM[n+1]亦可作為一第二控制信號，所述的第二控制信號係耦接至子像素單元60中第二電容器C2的第二端。除此之外，對於子像素單元61而言，提供給子像素單元62的第四控制信號EM[n+2]亦可作為耦接至子像素單元61中第二電容器C2第二端的一第二控制信號。如此一來，可有效地簡化控制機制。 圖7A繪示根據另一實施例的顯示器之子像素單元70的電路圖。 參照圖7A，所示電路與上文參照圖2所示的電路20相似，不同之處在於譬如可利用n-型TFT或n-型金氧半(NMOS)電晶體來取代圖2的p-型TFT或PMOS電晶體T1至T7。 具體來說，電晶體T1的閘極接收第一控制信號S1。電晶體T1的汲極耦接至第一節點A。此外，電晶體T3的閘極亦接收上述第一控制信號S1。電晶體T3的源極接收VSS。電晶體T3的汲極耦接至電晶體T1的源極。再者，電晶體T2的閘極亦接收上述第一控制信號S1。電晶體T2的源極耦接至電晶體T1的源極，並因而耦接至電晶體T3的汲極。電晶體T4的閘極耦接至第一節點A，並因而耦接至電晶體T1的汲極。電晶體T4的源極耦接至第二節點B。電晶體T4的汲極耦接至電晶體T2的汲極。 所述的第一電容器C1耦接於第一節點A和第二節點B之間。此外，第二電容器C2的第一端耦接至第二節點B，且第二端用以接收一第二控制信號S2。 再者，電晶體T5的閘極接收一第三控制信號S3。電晶體T5的汲極從源極驅動器15接收一相應資料線上的資料(標記為"DATA")。電晶體T5的源極耦接至第一節點A，並因而耦接至電晶體T4之閘極與電晶體T1的汲極。此外，電晶體T6與T7兩者的閘極接收第四控制信號EM。電晶體T6的源極接收VSS。電晶體T6的汲極耦接至第二節點B，並因而耦接至電晶體T4的源極。此外，電晶體T7的源極耦接至電晶體T2與T4兩者的汲極。電晶體T7的汲極耦接至EL裝置28的陰極。EL裝置28的陽極耦接至耦接至VDD。 圖7B為根據某些實施例，用以操作圖7A所示電路之控制信號的時序圖。 參照圖7B，控制信號S1、S3與EM和上文參照圖3A、4A或5A所述者相似，不同之處在於，例如，由於採用了n-型電晶體T1至T7，圖7B的控制信號S1、S3及EM為正緣觸發，或拉高至一正緣(rising edge)，而第二控制信號S2相較於圖3A、4A或5A所示者為反相。 可將流經圖7A之EL裝置28的電流Isd表示為下列方程式(3)。 2 =×(Vdata-VSS)]2 方程式(3) 同理，上述電流Isd與電晶體T4的閾值電壓無關。由於方程式(3)不涉及Vth參數，可提升顯示器10的顯示品質。此外，上文參照圖6所述的簡化控制機制亦可運用於圖7A的子像素單元70。 圖8為一流程圖，繪示在電致發光顯示器中進行電壓補償的方法。 參照圖8，在操作81，提供一電致發光(EL)顯示器。所述EL顯示器包含一像素單元陣列，其中的每一像素單元分別包含EL裝置、電晶體、第一電容器以及第二電容器。 接著，在操作83，於第一階段中，回應一第一控制信號，將電晶體閘極的電壓位準重置為供應電壓。 在操作85，回應一第二控制信號，在電晶體的一端部(源極)建立與電晶體閾值電壓相關的一補償電壓。 在操作87，回應一第三控制信號，將與該EL裝置相關的資料儲存於第一與第二電容器中。 其後，在操作88，回應一第四控制信號，使電流透過電晶體而流經所述EL裝置。上述電流的強度與所述電晶體的閾值電壓無關。 上文的敘述簡要地提出了本發明某些實施例之特徵，而使得本發明所屬技術領域具有通常知識者能夠更全面地理解本揭示內容的多種態樣。本發明所屬技術領域具有通常知識者當可明瞭，其可輕易地利用本揭示內容作為基礎，來設計或更動其他製程與結構，以實現與此處所述之實施方式相同的目的和/或達到相同的優點。本發明所屬技術領域具有通常知識者應當明白，這些均等的實施方式仍屬於本揭示內容之精神與範圍，且其可進行各種變更、替代與更動，而不會悖離本揭示內容之精神與範圍。
10‧‧‧顯示器
12‧‧‧主動區域
14‧‧‧閘極驅動器
15‧‧‧源極驅動器
16‧‧‧電源驅動器
18‧‧‧DC偏壓源
20、60~62‧‧‧子像素單元
28‧‧‧EL裝置
81~88‧‧‧步驟
A、B‧‧‧節點
C1、C2‧‧‧電容器
DATA‧‧‧資料
Isd‧‧‧電流
M‧‧‧行
N‧‧‧列
P‧‧‧像素單元
pw‧‧‧脈衝寬度
S1~S3、EM‧‧‧信號
t1~t5‧‧‧時間點
T1~T7‧‧‧電晶體
VDD‧‧‧工作電壓
Vref‧‧‧參考電壓
VSS‧‧‧接地電壓
在閱讀了下文實施方式以及附隨圖式時，能夠最佳地理解本揭露的多種態樣。應注意到，根據本領域的標準作業習慣，圖中的各種特徵並未依比例繪製。事實上，為了能夠清楚地進行描述，可能會刻意地放大或縮小某些特徵的尺寸。 圖1為根據一實施例之顯示器的區塊圖。 圖2為根據一實施例，圖1所示顯示器中一子像素單元的電路圖。 圖3A及3B繪示根據某些實施例，於第一階段中操作圖2所示電路的方法。 圖4A及4B繪示根據某些實施例，於第二階段中操作圖2所示電路的方法。 圖5A及5B繪示根據某些實施例，於第三階段中操作圖2所示電路的方法。 圖6為根據某些實施例，一子像素單元的電路結構圖式。 圖7A為根據另一實施例，一顯示器中一子像素單元的電路圖。 圖7B為根據某些實施例，用以操作圖7A所示電路之控制信號的波形圖。 圖8為流程圖，其繪示在一電致發光顯示器中進行電壓補償的方法。

Claims (20)

  1. 一種像素電路，包含： 一電致發光(EL)裝置； 一電晶體，耦接於一供應電壓和該EL裝置之間，該電晶體包含耦接至一第一節點的一閘極，以及耦接至一第二節點的一端部； 一第一電容器，耦接於該第一節點和該第二節點之間，用以回應一第一控制信號，而將該電晶體之該閘極重置為該供應電壓；以及 一第二電容器，包含耦接至該第二節點的一第一端，以及用以接收一第二控制信號的一第二端，該第二電容器用以回應該第二控制信號，以在該電晶體之該端部建立與該電晶體之一閾值電壓相關的一補償電壓， 其中該電晶體用以使一電流流經該EL裝置，該電流的強度與該電晶體之該閾值電壓無關。
  2. 如請求項1所述之電路，還包含另一電晶體，用以回應該第一控制信號，以提供該供應電壓給該電晶體之該閘極。
  3. 如請求項1所述之電路，還包含另一電晶體，用以回應一第三控制信號，以接收與該EL裝置相關之資料。
  4. 如請求項1所述之電路，還包含另一電晶體，用以回應一第四控制信號，以使該電流流經該EL裝置。
  5. 如請求項1所述之電路，其中該電流的強度為該第一與第二電容器各自之一電容的一函數。
  6. 如請求項1所述之電路，其中該電晶體包含一p-型電晶體，且該電流可表示為：×(VDD-Vdata)]2 其中Isd表示該電流之強度，k為一常數，C1及C2分別表示該第一與第二電晶體的電容，VDD表示該供應電壓，且Vdata表示與該EL裝置相關之資料的一電壓位準。
  7. 如請求項1所述之電路，其中該電晶體包含一n-型電晶體，且該電流可表示為：×(Vdata-VSS)]2 其中Isd表示該電流之強度，k為一常數，C1及C2分別表示該第一與第二電晶體的電容，VSS表示該供應電壓，且Vdata表示與該EL裝置相關之資料的一電壓位準。
  8. 如請求項1所述之電路，其中該第一控制信號的一脈衝寬度等於一訊框時間。
  9. 一種電致發光顯示器，包含： 一像素單元陣列，該像素單元陣列中的每一像素單元包含： 一電致發光(EL)裝置； 一電晶體，耦接於一供應電壓和該EL裝置之間，包含耦接至一第一節點的一閘極，以及耦接至一第二節點的一端部； 一第一電容器，耦接於該第一節點和該第二節點之間，用以回應一第一控制信號，以將該電晶體之該閘極重置為該供應電壓；以及 一第二電容器，包含耦接至該第二節點的一第一端，以及用以接收一第二控制信號的一第二端，該第二電容器用以回應該第二控制信號，以在該電晶體之該端部建立與該電晶體之一閾值電壓相關的一補償電壓， 其中該電晶體用以使一電流流經該EL裝置，該電流的強度與該電晶體之該閾值電壓無關。
  10. 如請求項9所述之電致發光顯示器，還包含另一電晶體，用以回應該第一控制信號，以提供該供應電壓給該電晶體之該閘極。
  11. 如請求項9所述之電致發光顯示器，還包含另一電晶體，用以回應一第三控制信號，以接收與該EL裝置相關之資料。
  12. 如請求項9所述之電致發光顯示器，還包含另一電晶體，用以回應一第四控制信號，以使該電流流經該EL裝置。
  13. 如請求項12所述之電致發光顯示器，其中該像素單元陣列包含位於第N列上之一第一像素單元，以及位於第(N+1)-列上且緊鄰該第一像素單元之一第二像素單元，N為一自然數，且其中該第四控制信號係提供給該第二像素單元，並作為該第一像素單元的該第二控制信號。
  14. 如請求項9所述之電致發光顯示器，其中該電流的強度為該第一與第二電容器各自之一電容的一函數。
  15. 如請求項9所述之電致發光顯示器，其中該電晶體包含一p-型電晶體，且該電流可表示為：×(VDD-Vdata)]2 其中Isd表示該電流之強度，k為一常數，C1及C2分別表示該第一與第二電晶體的電容，VDD表示該供應電壓，且Vdata表示與該EL裝置相關之資料的一電壓位準。
  16. 如請求項9所述之電致發光顯示器，其中該電晶體包含一n-型電晶體，且該電流可表示為：×(Vdata-VSS)]2 其中Isd表示該電流之強度，k為一常數，C1及C2 分別表示該第一與第二電晶體的電容，VSS表示該供應電壓，且Vdata表示與該EL裝置相關之資料的一電壓位準。
  17. 如請求項9所述之電致發光顯示器，其中該第一控制信號的一脈衝寬度等於一訊框時間。
  18. 一種電致發光(EL)顯示器的電壓補償方法，其中該EL顯示器包含一像素單元陣列，該像素單元陣列的每一像素單元包含一EL裝置、一電晶體、一第一電容器及一第二電容器，該方法包含： 將位於該電晶體之一閘極的一電壓位準重置為一供應電壓，以回應一第一控制信號； 在該電晶體之一端部建立與該電晶體之一閾值電壓相關的一補償電壓，以回應一第二控制信號； 將與該EL裝置相關之資料儲存於該第一與第二電容器，以回應一第三控制信號；以及 使一電流透過該電晶體而流經該EL裝置體，以回應一第四控制信號，該電流的強度與該電晶體之該閾值電壓無關。
  19. 如請求項18所述之方法，其中該像素單元陣列包含位於第N列上之一第一像素單元，以及位於第(N+1)-列上且緊鄰該第一像素單元之一第二像素單元，N為一自然數，該方法還包含： 利用提供給該第二像素單元的該第四控制信號作為該第一像素單元的該第二控制信號。
  20. 如請求項19所述之方法，還包含： 提供具有實質上等於一訊框時間之一脈衝寬度的該第一控制信號。
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TWI769767B (zh) * 2021-03-30 2022-07-01 友達光電股份有限公司 畫素電路以及顯示面板

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