1360214 九、發明說明： .【發明所屬之技術領域】 纟發明係有關於—種半導體裝置及其製法，尤指一種 半導體封裝基板及其製法。 v【先前技術】 — '駿高半導體晶片封裝用之基板之佈線精密度，業界 逐發展出-種增層技術（Build_up)，亦即在—核心基板 (Core board)表面利用線路增層技術交互堆疊多層介電 ♦層及線路層，並於該介電層中開設導電盲孔（㈤㈣以 • via)以供上下|線路之間電性連接，其巾，該線路增層製 知係影響基板線路密度的關鍵。 請參閱第1A至1H圖，係為習知增層基板之製法。首 先，如第1A圖所示’提供一例如銅箔基板（c〇pperc〇討ed laminated, CCL)之具金屬薄層1〇1之絕緣層1〇〇，並於 其中鑽設有複數個通孔1〇2。如第1B圖所示，再經過鍍 鲁鋼以於該金屬薄層101之表面及於該通孔1〇2之孔壁上形 成有金屬層103;如第1C圖所示，復填充一導電或不導 電之塞孔材料11(如絕緣性油墨或含銅導電膏等）以填滿 忒通孔102殘留空隙，俾形成一電鍍導通孔（pTH)1〇2a以 電性導H絕緣層1GG上下表面之金屬層1Q3;如第1D 圖所示，之後以刷磨製程去除多餘塞孔材料u，以維持 核心基板線路表面之平整度；如第1E圖所示，最後再將 該絕緣層100兩面之金屬薄層1〇1及金屬層1〇3進行圖案 化製程’藉以構成一具雙面之内層線路層1〇4的核心基板 110722 5 13,60214 10結構。 之後，如第IF圖所示，於該核心基板1〇上下表面之 内層線路層104上形成-介電層12，利用雷射鑽孔α咖 ^illing)技術於該介電層12上形成複數開孔12〇;接 著’如第1G圖所示，於該介電層12及開孔12〇表面以蛊 •電解電鐘銅方式形成-導電層13，在該導電層13±施加 -阻層14’並形成有外露出部分導電層13之開口後進行 電鍍製程，以於該導電層13表面形成線路層15。之後， ，如第1H圖所示，去除該阻層14並進行钮刻，以移除先前 覆蓋於阻層14下之導電層13。如此，運用該等流程重複 形成介電層及線路層，即製成一具多層線路之基板。 准上述之具多層線路之基板製程中，係採用表面包 =有金屬薄層之絕緣層結構作爲芯層（GQre)，並於該站 户曰上進订線路製程以形成_核心、基板核心基板於製程中 =了塞孔及刷磨製程，會增加基板製造步驟。尤其重要的 是’核心基板中形成有多數電鍵導通孔（ρτΗ),而一般電 鍍導通孔⑽）之孔㈣約在以上 因盲:之孔徑約在5 一左右，且可以電鑛線路方式形成 =此’比Μ言該電鍍導通孔之結構佔用過大佈線空間， 而不利於細線路結構之形成。 其:再者^述之夕層封裝基板製程中，需先製備一核心 =，接著再於該核心基板上形成介電層及線路層，方能 此技術具有佈線密度低’層數多，導線長且阻抗高 的問崎，對於高頻基板較難應用。又因疊層數多，盆製程 110722 6 1360214 步驟也較複雜。 因此，如何提供一種多層封裝基板及1 習知技術中佈線密度低，層數多，導線長^抗高及= 步驟複雜的問題’實已成爲目前業界亟待克服 【發明内容】 難喷° 鑑於上述習知技術之種種缺失，本發明之主要 於提供一種能形成細線路結構之封裝基板及其製法。、在 本發明之又一目的在於提供一種 基板及其製法。 ^間化製程之封裝 為達上述及其它目的，本發明揭露 .法’係包括··提供一核心板，並於核心板至== 黏著層，且於黏著層上形成金屬層；於該金 :7 ^成 -阻層，移除部分第一阻層及蝕刻移除部分金』二第 第-開口區，_£金屬層移除範圍之徑 第θ =成 範圍之柝宮0a 覓大於第一阻層移除 二Τ:ί 區中之金屬層上形成金屬柱;移 广第-防焊層，且第一防焊層第一表面 曰：而金屬柱設於該第—防焊層中並與第 面齊平’以使金屬柱外露於第 曰第：表 柱及第一防焊層第二表面上形成第二表面； 、於金屬 口區以露出金屬柱及A周圍曰，並形成第二開 中弗.、周圍之第一防焊層；於第二開口區 電性連接金屬柱；移除第二二層3第：電性接觸㈣ 焊層上形成增層結構;移除核:二:：線路層及第一防 ’、J匕板及黏著層，以完全露出 110722 7 金屬層；以及移除金屬層，以外露金屬柱及第一防痒層第 一表面。 依上㈣法，該金屬㈣可由化學錫及錢銅所構 成，且該化學錫外露於第一防焊層上以連結晶片；然，該 金屬柱亦可由電鍍焊錫及電鍍銅構成，且該電鑛焊錫外露 ^第1防焊層上。另外，該金屬層係可為銅箱，而該金屬 柱外露於第一防焊層之一端可呈凸階狀。 依上述製法，該增層結構係可包括：形成於第一防焊 :及第-線路層上之至少一介電層、及形成於介電層上之 第二線路層，且於增層結構上形成有第二防焊層及第二電 性接觸塾，該第二電性接觸塾電性連接該第二線路層，該 第二防悍層設於介電層及第二電性接觸墊上，並具有開孔1360214 IX. Description of the invention: [Technical field to which the invention pertains] The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor package substrate and a method of fabricating the same. v [Prior Art] — 'The precision of the wiring of the substrate used in Jungao semiconductor chip packaging, the industry has developed - a build-up technology (Build_up), that is, on the surface of the core board (Core board) using line build-up technology to interact Stacking a plurality of dielectric layers ♦ layers and circuit layers, and forming conductive blind holes in the dielectric layer ((5) (four) to • via) for electrical connection between the upper and lower lines, the towel, the line layering system affects the substrate The key to line density. Please refer to Figures 1A to 1H for the preparation of a conventional build-up substrate. First, as shown in FIG. 1A, an insulating layer 1 having a thin metal layer 1〇1, such as a copper foil substrate (CCL), is provided, and a plurality of through holes are drilled therein. Hole 1〇2. As shown in FIG. 1B, the plated steel is further formed on the surface of the metal thin layer 101 and the metal layer 103 on the hole wall of the through hole 1〇2; as shown in FIG. 1C, the filling is electrically conductive. Or a non-conductive plug material 11 (such as an insulating ink or a copper-containing conductive paste, etc.) to fill the residual space of the through-hole 102, and form a plated via (pTH) 1〇2a to electrically conduct the H insulating layer 1GG. a metal layer 1Q3 on the upper and lower surfaces; as shown in FIG. 1D, the excess plug material u is removed by a brushing process to maintain the flatness of the core substrate line surface; as shown in FIG. 1E, the insulating layer 100 is finally The two-sided metal thin layer 1〇1 and the metal layer 1〇3 are patterned to form a core substrate 110722 5 13,60214 10 structure having a double-sided inner wiring layer 1〇4. Then, as shown in FIG. IF, a dielectric layer 12 is formed on the inner wiring layer 104 of the upper and lower surfaces of the core substrate 1 , and a plurality of dielectric layers 12 are formed on the dielectric layer 12 by a laser drilling technique. Opening 12〇; then, as shown in FIG. 1G, a conductive layer 13 is formed on the surface of the dielectric layer 12 and the opening 12 by a copper electrolysis clock, and a resist layer is applied to the conductive layer 13± 14' is formed with an opening exposing a portion of the conductive layer 13, and then an electroplating process is performed to form a wiring layer 15 on the surface of the conductive layer 13. Thereafter, as shown in Fig. 1H, the resist layer 14 is removed and button-finished to remove the conductive layer 13 previously covered under the resist layer 14. Thus, the dielectric layer and the wiring layer are repeatedly formed by using the processes to form a substrate having a multilayer wiring. In the above-mentioned substrate process with multi-layer lines, the surface layer = the thin layer of the metal layer is used as the core layer (GQre), and the line process is formed on the station to form the core substrate core substrate. In the process, the plug hole and brushing process will increase the substrate manufacturing steps. It is especially important that 'the majority of the key vias (ρτΗ) are formed in the core substrate, and the holes (4) of the general plated vias (10) are about blind. The aperture is about 5, and can be formed by electric ore lines. This is more than rumor that the structure of the plated via hole occupies excessive wiring space, which is not conducive to the formation of a fine line structure. In addition, in the process of packaging the substrate, it is necessary to prepare a core = first, and then form a dielectric layer and a circuit layer on the core substrate, so that the technology has a low wiring density, and the number of layers is large. Takasaki, which has a long and high impedance, is difficult to apply to high-frequency substrates. Because of the large number of stacks, the pot process 110722 6 1360214 is also more complicated. Therefore, how to provide a multi-layer package substrate and a conventional technique in which the wiring density is low, the number of layers is large, the length of the wire is high, and the step of the step is complicated is a problem that has been urgently overcome in the industry [invention] In view of the various deficiencies of the prior art, the present invention is mainly directed to providing a package substrate capable of forming a fine wiring structure and a method of fabricating the same. Still another object of the present invention is to provide a substrate and a method of manufacturing the same. The encapsulation process package is for the above and other purposes, and the present invention discloses that the method comprises: providing a core board, and forming a metal layer on the core board to the == adhesive layer; and forming a metal layer on the adhesive layer; : 7 ^ into - resist layer, remove part of the first resistive layer and etch remove part of the gold "two first - open area, _ £ metal layer removal range of the diameter θ = into the range of the palace 0 0a 觅 greater than the a resist layer removes the second layer: a metal pillar is formed on the metal layer in the region; the first-solderproof layer is removed, and the first surface of the first solder resist layer is: and the metal pillar is disposed in the first solder mask layer And being flush with the first surface to expose the metal pillar to the second surface of the second pillar: the surface of the first solder resist layer; forming a second surface in the metal mouth region to expose the metal pillar and surrounding the crucible, and forming The second open middle and outer welcoming layer, the first solder mask layer around; the second open region electrically connected to the metal pillar; the second second layer 3: electrical contact (4) forming a buildup layer on the solder layer; removing the core : 2:: circuit layer and first anti-', J-plate and adhesive layer to completely expose 110722 7 metal layer; and remove metal layer, exposed metal And a first surface of the first layer of the anti-itch. According to the (4) method, the metal (4) may be composed of chemical tin and copper, and the chemical tin is exposed on the first solder resist layer to bond the wafer; however, the metal pillar may also be composed of electroplated solder and electroplated copper, and the electric The exposed solder is exposed on the first solder mask. In addition, the metal layer may be a copper box, and the metal column may be convexly shaped at one end of the first solder resist layer. According to the above method, the build-up structure may include: at least one dielectric layer formed on the first solder resist: and the first circuit layer, and a second circuit layer formed on the dielectric layer, and the build-up structure Forming a second solder mask and a second electrical contact, the second electrical contact is electrically connected to the second circuit layer, and the second anti-corrugated layer is disposed on the dielectric layer and the second electrical contact pad With a hole
以露出第二電性接觸塾，且可於該第二電性接觸墊 銲球。 'D 本發明復提供-種封裝基板，係包括：第一防焊声， 係具有相對之P表面及第二表面；金屬柱，係設於第一 =焊層中’且其一端呈凸階狀並突伸外露於第一防悍層第 :表面’而另一端與第一防焊層第二表面齊平；第一線路 係設於第-防焊層第二表面上，且具有第一電性接觸 塾以電性連接金屬柱；以及增層結構，係設於第一防焊層 第二表面及第一線路層上。 曰 依上述結構’該金屬柱係可由化學錫及核銅所構 ^ ’且化學錫外露於第-防焊層上以連結晶片；然，該金 屬柱亦可由電鍍焊錫及電鍍銅所構成，且電鍍焊锡外露於 11072： 8 第一防焊層上。 :增：結構係包括:設於第一防焊層及第 1至/—介電層、 曰上 層結構上1有望之第二線路層’且於增 捲觸執/有第一防焊層及第二電性接觸誓’該第二電性 :性連接該第二線路層，該第二防焊層 =:接!塾上’並具有開孔以露出第二電性接: μ第一电性接觸墊用以連結銲球。 心拓2可知，本發明之縣練及其製法，主要係於核 形成金屬柱及第一防焊層，接著於該第一防焊層 金屬柱上形成多層線路層’之後移除該核心、板以露出形 、於第-防谭層中之金屬柱’俾以形成無核心板之封裝基 板’其可提高佈線密度，另由於本發明係無核心板及免製 作電鍍導通孔，進而能簡化製程以及形成細線路結構。 又，於第一開口區中，因金屬層被移除之範圍大於第 一阻層，而使於第一開口區中形成之金屬柱，其一端呈凸 Ρ白狀以便於外接晶片。再者，本發明藉由金屬柱表面之電 鍍焊錫或化學錫作為蝕刻保護層，而可使金屬層迅速移除 且不破壞該金屬柱，以提高製程效率。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式’熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2Α至2Ρ圖係為本發明之封裝基板之製法之 剖面示意圖。 9 110722 1360214 如第2A圖所示，k供一核心板2〇，並於核心板2〇 至少一表面形成黏著層2(Π，且於黏著層2〇1上形成為鋼 箔之金屬層202。 如第2Β圖所示，於金屬層2〇2上形成第一阻層21心 且移除部份第H 21a及藉由濕㈣移除部分金屬層 以形成複數第一開口區21〇a，使金屬層2〇2外露於第一 開口區21〇a。其中’因等向性餘刻效應，故金屬層2〇2 被移除範圍之；^見大於第—阻@ 2! &被移除範圍之徑 寬，所述之第一阻層21a係為液態光阻或乾膜等光阻層 (Photoresist)。 曰 如第2C圖所示，於該第一開口區21〇3之金屬層2〇丨 上形成金屬柱24,而該該金屬柱24之製法亦可先形成一 層電鍍焊錫24G，再於電鍍焊錫24()上形成—層電錢銅 41 ’使該金屬柱24由電鍍焊錫24〇及電鍍銅241所構 成’其中’電鍍焊錫（Electroplating s〇lder)24〇係為The second electrical contact 塾 is exposed, and the ball can be soldered to the second electrical contact pad. 'D The present invention provides a package substrate comprising: a first solder resist sound having a relative P surface and a second surface; a metal pillar disposed in the first = solder layer and having a convex end at one end thereof And protruding outwardly from the first anti-mite layer: surface 'the other end is flush with the second surface of the first solder resist layer; the first line is disposed on the second surface of the first solder resist layer and has the first The electrical contact is electrically connected to the metal pillar; and the build-up structure is disposed on the second surface of the first solder resist layer and the first circuit layer. According to the above structure, the metal pillar can be constructed of chemical tin and nuclear copper, and the chemical tin is exposed on the first solder resist layer to bond the wafer; however, the metal pillar can also be composed of electroplated solder and copper plating, and The electroplated solder is exposed on 11072: 8 on the first solder mask. :增增: The structure includes: a second solder layer disposed on the first solder resist layer and the first to/or dielectric layers and the upper layer structure of the crucible, and the first solder mask and the first solder resist layer The second electrical contact swears the second electrical property: the second wiring layer is sexually connected, the second solder resist layer is: connected to the upper layer and has an opening to expose the second electrical connection: μ first electric The contact pads are used to connect the solder balls. Xintuo 2 knows that the county practice and its manufacturing method are mainly for forming a metal pillar and a first solder resist layer, and then removing the core after forming a multilayer wiring layer on the first solder mask metal pillar. The board is formed by exposing the metal pillars in the first anti-tank layer to form a package substrate without a core board, which can improve the wiring density, and the present invention has no core board and no plating through holes, thereby simplifying Process and form a fine line structure. Further, in the first opening region, since the metal layer is removed by a larger extent than the first resist layer, the metal pillar formed in the first opening region has a convex white end at one end to facilitate the external connection of the wafer. Furthermore, in the present invention, by electroplating solder or chemical tin on the surface of the metal post as an etch protection layer, the metal layer can be quickly removed without damaging the metal post to improve process efficiency. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily appreciate the other advantages and functions of the present invention from the disclosure herein. Please refer to Figures 2 to 2 for a cross-sectional view showing the method of manufacturing the package substrate of the present invention. 9 110722 1360214 As shown in FIG. 2A, k is provided for a core plate 2, and an adhesive layer 2 is formed on at least one surface of the core plate 2 (Π, and a metal layer 202 formed as a steel foil on the adhesive layer 2〇1) As shown in FIG. 2, a first resistive layer 21 is formed on the metal layer 2〇2 and a portion of the H 21a is removed and a portion of the metal layer is removed by wet (iv) to form a plurality of first open regions 21〇a The metal layer 2〇2 is exposed to the first opening region 21〇a. wherein the metal layer 2〇2 is removed due to the isotropic residual effect; ^ is greater than the first resistance@ 2! & The first resistive layer 21a is a photoresist such as a liquid photoresist or a dry film, as shown in FIG. 2C, in the first open region 21〇3. A metal pillar 24 is formed on the metal layer 2, and the metal pillar 24 can be formed by first forming a layer of electroplated solder 24G, and then forming a layer of electromotive copper 41' on the electroplated solder 24() to make the metal pillar 24 Electroplated solder 24 〇 and electroplated copper 241 constitute 'the 'electroplating solder (Electroplating s〇lder) 24 为
锡鉛(Sn/Pb)、錫銀(Sn/Ag)、無鉛焊料(sac)、及錫⑽ 之低熔點焊料其中一者。 如第2C，圖所示，該金屬柱24之製法亦可係包括 :積化學錫240，，接著於化學錫24〇，上形成一層電鍍 ，使该金屬柱24由化學錫24〇,及電鑛銅241所構成 乂下圖式則以延續第2C圖做說明。 如第2D、2E圖所示，移除第一阻層⑴；接著， C2及金屬柱24上形成第-防焊層…並移1 防焊層23至金屬纟24外露於第一防焊層23 110722 10 1360214 於此製程中’第一防焊層23具有相對之第 第二表面23b，且該第一防焊層23以並第一 / a 成於金屬層202上，而該金屬柱24 义2%形 邦征μ 〇又於第_防惊展9 中並與第一防焊層23第二表面曰 外露於第-防焊層23第二表面23br+以使金屬柱24 再於金屬柱24及第—防焊層23第二表面23b上 第二阻層21b，並形成複數第二開口區21〇b以露出金屬 柱24、其周圍及他處之第一防焊層23。 如第2F、2G圖所示，於第二開.口區21〇1)中形成第 -線路層24a’且該第-線路層24a具有第—電性接觸替 Μ以於第-防焊層23第二表面23b上電性連接該金屬柱 24 ;再移除第二阻層2ib。 如第2H圖所示，接著，進行線路增層製程，於第一 線路層24a及第一防焊層23第二表面2扑上形成介電層 251，並形成複數介電層開孔251〇，以露出部分第一線路 層 24a。 如第21圖所示，接著，於介電層251上、介電層開 孔2510表面及部分第一線路層24a上形成導電層252， 且於導電層252上形成第三阻層253，並形成複數第三開 口區2530，以露出導電層252。 所述之導電層252主要作為後述電鍍金屬所需之電 流傳導路徑’其可由金屬、合金、沉積數層金屬層、或導 電高分子材料所構成；該第三阻層253係為例如乾膜或液 態光阻等光阻層（Photoresist)，其利用印刷、旋塗或貼 11 110722 1360214 以二〔成層252上’再藉由曝光、顯影等方式 以進行♦辦rp〗+ 3由導电層252作為電流傳導路徑 ‘令之導：二二r〇Pl:ting)製程，於第三開口區_ ' * ^ 254 ^ ^上形成第二線路層254，且令該第二線路 曰254 M·生連接至該第—令 •層24a月笼砝々線層仏。其中，該第一線路 曰仏及#二線路層⑸之材料 ::錯(Hi—點金屬其中-者;惟： 由於銅為成熟之電鍍材料且成本較低，因 乂電鍍銅較佳，但非以此為限。 如第2K圖所示，移除第三阻層挪及其所覆蓋 電層252 ’以形成由介電芦導 之增層結構25。 及第一線路層254所構成 如第2L、2M圖所示，可依此增層製法繼續增加線路， ^於該增層結構25最外層形成有複數電性連接第二線路 f 254之第二電性接觸塾26 ;接著，於增層結構25最外 曰再形成有第二防焊層27’該第二防焊層27設於介電層 251及第二電性接觸墊26上，並具有開孔27〇以露出； 二電性接觸墊26。 如第2N圖所示，移除核心板2〇及黏著層2〇1，以* 全露出金屬層202。 凡 如第20圖所示，以蝕刻方式移除金屬層2〇2，以露 出該金屬柱24及第一防焊層23第一表面23a，且該金屬 柱24之電鍍焊錫240 (或化學錫240，）突伸外露於第一 110722 12 1360214 防焊層23第一表面23a，因先前製作第一開口區21 〇a的 步驟中，金屬層202移除範圍大於第一阻層2ia，使該金 屬柱24外露之一端呈凸階狀，亦即電鍍焊錫24〇或化學 錫240’突伸外露於第一防焊層23的外徑大於設置於第一 防焊層23中的電錢銅241外徑。 如第2P圖所示，於第二電性接觸墊26上連結銲球 31(S〇lderball)以供外接印刷電路板，而金屬柱％藉由 電鍍焊錫240連結晶片30，再進行迴焊（Refl〇w)。其中， 電鍍焊錫240及銲球31係為錫鉛（Sn/pb)、錫銀（Sn/Ag)、 無鉛焊料（SAC)、及錫（Sn)之低熔點焊料其中一者。然， 有關於電性接觸墊連結銲球之製程技術繁多，惟乃業界所 周知之技術，且其非本案技術特徵，故不再贅述。 另外為避免封裝基板產生輕曲，於第一防焊層23 =第一防焊層27上形成支樓層29,該支樓層29呈有支 ，層開口 290’以露出第二電性接㈣26、金屬柱24、 2第了焊層23及第二防焊層27。該支撐層29係為 ,:、陶竞或金屬複合材料’並以係為環氧樹脂 黏耆劑結合於第-防焊層23及第二防焊層27上。 如圖所示’依上述製法’本發明復提供 板’係包括：第一防焊層Μ、埜一 展基 Μ以及金屬柱24。 第—料層W、增層結構 其中，該第一防焊層23具有相對之第 τί 1/1Τ- Ο Ο λ. X α 策一主1 ηη, .......μ >不 取囬乙如 表面饥’該金屬柱Μ設於第-防焊層㈡中 端呈凸階狀並突伸外露於第-防焊層23第一表面: 110722 13 1360214 上’並其外露之電鎮禪錫24〇外徑大於設置 23中電鍍銅241的外徑，而另一端與 防，層 表面23b齊平；該第一曰3第二 二表面23b上，且ί有* —防焊層23第 屬柱24。且”有第一电性接觸塾22以電性連接金 另外，該增層結構25設於第一防谭層2 f及第—線路層24a上，係包括：設μ -防谭—/23 第-表面23b及第—線路層…上之至少 曰 及設於介電層251上之第二線路層⑸ .層⑽性連接第一線路層24a’ :254設有第二電性接觸㈣。又，於該; 層251及第二電性接觸 取外層之7丨電 具有開孔㈣以露出第二電性上接覆觸;二防焊層打，並 上述結構’該封裝基板復包括有設於第-防 …或第二防焊層27上之支撑層 方 開口 290,以露出第二電性 :、有支㈣ 第一防焊層23及部份第二防烊層27。金屬柱24、部份 因此，本發明之封録板及其製法， ==屬=—防焊層，接著於第-防焊二 二防焊層，之後移除核“二 其把金屬柱’俾以形成無核心板之封裝 ;:二1佈;密度’另由於本發明係無核心板及免 電鍵4料進而能—以及形·線路結構。 110722 14 1360214 —又’因金屬層被移除之範圍大於第一阻層，而使於第 曰開口區中形成之金屬柱’其—端呈凸階狀以便於外接 晶片。 再者’本發明藉由金屬柱表面之電鍍焊錫或化學錫作 為蝕刻保護層，而可使金屬層迅速移除且不破壞該金屬 才以避免钱刻金屬的繁複步戰及耗費時間，進而提高製 程效率。 上述實施例係用以例示性說明本發明之原理及其功 政’而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1Α至1Η圖係為習知封裝基板之製法示意圖； 第2A至2P圖係為本發明之封裝基板之製法之剖面示 意圖；以及 第2C’圖係為對應第2C圖之另一實施態樣示意圖。 【主要元件符號說明】 10 核心基板 100 絕緣層 101 金屬薄層 102 通孔 102a 電鑛導通孔 103 金屬層 15 110722 内層線路層 基孔材料 介電層 開孔 導電層 阻層 線路層 核心板 黏著層 金屬層 第一阻層 第一開口區 第二阻層 第二開口區 第一電性接觸墊 第一防焊層 第一表面 第二表面 金屬柱 電鍍焊錫 化學錫 電鍍銅 第一線路層 增層結構 16 110722 介電層 介電層開孔 導電層 第三阻層 第三開口區 第二線路層 第二電性接觸墊 第二防焊層 開孔 支撐層 支撐層開口 晶片 鲜球 17 110722One of tin-lead (Sn/Pb), tin-silver (Sn/Ag), lead-free solder (sac), and low-melting solder of tin (10). As shown in FIG. 2C, the method for manufacturing the metal pillar 24 may include: forming a chemical tin 240, and then forming a layer of electroplating on the chemical tin 24 ,, so that the metal pillar 24 is made of chemical tin 24 〇, and electricity The structure of the copper 241 is shown in the following figure. As shown in FIGS. 2D and 2E, the first resist layer (1) is removed; then, a C-solder layer is formed on the C2 and the metal pillars 24, and the solder resist 23 is removed from the solder mask 23 to the first solder resist layer. 23 110722 10 1360214 In the process, the first solder mask layer 23 has an opposite second surface 23b, and the first solder resist layer 23 is first and/or formed on the metal layer 202, and the metal pillar 24 The second 2% state is further disclosed in the first surface and the second surface of the first solder resist layer 23 is exposed on the second surface 23br+ of the first solder resist layer 23 so that the metal pillar 24 is further placed on the metal pillar 24 and the second resistive layer 23 have a second resist layer 21b on the second surface 23b, and a plurality of second opening regions 21b are formed to expose the metal pillars 24, the first solder resist layer 23 around them and elsewhere. As shown in FIGS. 2F and 2G, the first wiring layer 24a' is formed in the second opening region 21〇1) and the first wiring layer 24a has a first electrical contact for the first solder resist layer. The second surface 23b is electrically connected to the metal post 24; and the second resist layer 2ib is removed. As shown in FIG. 2H, next, a line build-up process is performed to form a dielectric layer 251 on the first circuit layer 24a and the second surface 2 of the first solder resist layer 23, and a plurality of dielectric layer openings 251 are formed. To expose a portion of the first wiring layer 24a. As shown in FIG. 21, a conductive layer 252 is formed on the surface of the dielectric layer opening 2510 and a portion of the first wiring layer 24a, and a third resist layer 253 is formed on the conductive layer 252. A plurality of third open regions 2530 are formed to expose the conductive layer 252. The conductive layer 252 is mainly used as a current conduction path required for a plating metal to be described later. It may be composed of a metal, an alloy, a deposited metal layer, or a conductive polymer material; the third resist layer 253 is, for example, a dry film or Photoresist, such as liquid photoresist, which is printed, spin-coated or affixed to 11 110722 1360214 by two layers [on layer 252 and then by exposure, development, etc. to perform rp" + 3 by conductive layer 252 As a current conduction path, the second circuit layer 254 is formed on the third opening region _ '* ^ 254 ^ ^, and the second circuit 曰 254 M· Connected to the first-order layer 24a month. Wherein, the material of the first circuit and the second circuit layer (5):: wrong (Hi-point metal among them; only: since copper is a mature electroplating material and the cost is low, because copper plating is better, but Without limitation, as shown in FIG. 2K, the third resist layer and its covered electrical layer 252' are removed to form a build-up structure 25 formed by the dielectric strip, and the first trace layer 254 is formed as 2L, 2M, the circuit can be further increased according to the layering method, and a second electrical contact 塾26 electrically connected to the second line f 254 is formed on the outermost layer of the layered structure 25; The second solder resist layer 27 is formed on the dielectric layer 251 and the second electrical contact pad 26, and has an opening 27 露出 to expose; Electrical contact pad 26. As shown in Fig. 2N, the core plate 2 and the adhesive layer 2〇1 are removed to completely expose the metal layer 202. As shown in Fig. 20, the metal layer 2 is removed by etching. 〇2 to expose the metal post 24 and the first surface 23a of the first solder resist layer 23, and the electroplated solder 240 (or chemical tin 240,) of the metal post 24 is exposed to the first surface a 110722 12 1360214 solder resist layer 23 first surface 23a, in the step of previously fabricating the first opening region 21 〇a, the metal layer 202 is removed from the first resistive layer 2ia, so that one end of the exposed metal pillar 24 is convex. The stepped shape, that is, the electroplated solder 24 〇 or the chemical tin 240 ′ is exposed to the outer diameter of the first solder resist layer 23 is larger than the outer diameter of the electric money copper 241 disposed in the first solder resist layer 23. As shown in FIG. 2P The solder ball 31 is connected to the second electrical contact pad 26 for external printed circuit board, and the metal pillar is connected to the wafer 30 by the plating solder 240, and then reflowed (Refl〇w). Among them, the electroplated solder 240 and the solder ball 31 are one of tin-lead (Sn/pb), tin-silver (Sn/Ag), lead-free solder (SAC), and tin (Sn) low-melting solder. Electrical contact pads are connected to the solder balls. The process technology is numerous, but it is a well-known technology in the industry, and it is not a technical feature of this case, so it will not be described. In addition, in order to avoid the light distortion of the package substrate, the first solder mask 23 = A soldering layer 27 is formed on the support floor 29, the branch floor 29 is branched, and the layer opening 290' is exposed to expose the second electrical property. (4) 26, metal pillars 24, 2 first solder layer 23 and second solder resist layer 27. The support layer 29 is:, Tao Jing or metal composite material 'and is bonded with epoxy resin adhesive agent - The solder resist layer 23 and the second solder resist layer 27. As shown in the above description, the "provided board" of the present invention includes: a first solder mask layer, a field base layer, and a metal pillar 24. Material layer W, build-up structure, wherein the first solder resist layer 23 has a relative τί 1/1 Τ - Ο λ λ. X α 策一主1 ηη, . . . μ > not retrieved B. If the surface is hungry, the metal pillar is disposed at the middle end of the first solder mask (2) and is convexly exposed and exposed on the first surface of the first solder resist layer 23: 110722 13 1360214 and its exposed electric Zen The outer diameter of the tin 24 大于 is larger than the outer diameter of the electroplated copper 241 in the setting 23, and the other end is flush with the anti-layer surface 23b; the first 曰3 second second surface 23b, and the 防*- solder resist layer 23 It belongs to column 24. And having a first electrical contact 22 to electrically connect the gold. In addition, the build-up structure 25 is disposed on the first anti-tank layer 2f and the first circuit layer 24a, including: setting μ-anti-tan-/23 At least the top surface 23b and the first circuit layer are disposed on the second circuit layer (5) disposed on the dielectric layer 251. The layer (10) is connected to the first circuit layer 24a': 254 to provide a second electrical contact (4). In addition, the layer 251 and the second electrical contact take-up layer have an opening (4) to expose the second electrical upper contact; the second solder resist layer is struck, and the above structure 'the package substrate includes The support layer side opening 290 is disposed on the first anti-prevention layer or the second solder resist layer 27 to expose the second electrical property: a branch (4) a first solder resist layer 23 and a portion of the second anti-crack layer 27. The metal pillar 24. Part of the reason, therefore, the sealing plate of the present invention and the method of manufacturing the same, == genus = - solder resist layer, followed by the first - solder resist 22 solder mask layer, after which the core "two metal pillars" are removed Forming a package without a core board;: two 1 cloth; density 'also because the invention is no core board and no electric key 4, and can be - and shape / line structure. 110722 14 1360214 - Again, because the metal layer is removed to a greater extent than the first resistive layer, the metal post formed in the open area of the first opening is convexly shaped to facilitate the tying of the wafer. Furthermore, in the present invention, by electroplating solder or chemical tin on the surface of the metal post as an etching protection layer, the metal layer can be quickly removed without damaging the metal, thereby avoiding complicated steps and time consuming of the metal, thereby improving Process efficiency. The above-described embodiments are intended to illustrate the principles of the invention and its functions, and not to limit the invention. Any of the above-described embodiments can be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are schematic diagrams of a conventional package substrate; FIGS. 2A to 2P are schematic cross-sectional views showing a method of manufacturing a package substrate of the present invention; and FIG. 2C' is a diagram corresponding to FIG. 2C Another embodiment of the schematic diagram. [Main component symbol description] 10 core substrate 100 insulation layer 101 metal thin layer 102 through hole 102a electric ore conduction hole 103 metal layer 15 110722 inner layer wiring layer base hole material dielectric layer opening conductive layer resistance layer circuit layer core plate adhesion layer Metal layer first resistive layer first open region second resistive layer second open region first electrical contact pad first solder resist layer first surface second surface metal pillar electroplated solder chemical tin electroplated copper first circuit layer buildup structure 16 110722 dielectric layer dielectric layer open hole conductive layer third resistive layer third open region second circuit layer second electrical contact pad second solder mask open hole support layer support layer open wafer fresh ball 17 110722