201002167 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路板及其製法，尤指一種電路 板之層間線路層的電性連接結構及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能㈣發方向。足半導體封裝件高積集度 (Integration)以及微型化（Miniaturizati〇n)的封裝 而求承載半‘體晶片之封裝基板，逐漸由雙層板演變成 多層板（Miilti-layer Board)，俾於有限的空間下，藉 由層間連接技術（interlayer c〇nnecti〇n)以擴大封裝 基板上可利用的線路面積，以因應高電子密度之積體電路 (I、ntegratedCircuit)的使用需求；為此，遂發展出一 種增層技術（build-up)，亦即在一核心電路板（c〇re Circuit board)表面利用線路增層技術交互堆疊多層介 電層及線路層，並於該介電層中開設導電盲孔 (conductive via)以供上、下層線路之間電性連接。 •為因應微處理器、晶片組、緣圖晶片與特殊應用積體 电路（ASIC)等高效能晶片之運算需要，佈有線路之半導體 基板亦需提昇其傳遞晶片訊號、改善頻寬、控制阻抗 專功月b’以因應高i/G數封裝件的發U為符合半導體 封裝件輕薄短小 '多功妒古、击 > ·" 回速度、南線路密度及高頻化 方向，封裝基板已朝向細線路及小孔徑發展，·現有 + ¥體封裝基板製程從傳統⑽微米之線路尺寸，已縮減 110823 5 201002167 至現在的30微米以下，其中，包括導線寬度（Une 及線路間距（space)等持續朝向更小的線路精度進行研 發0 、凊芩閱第1人至圖所示’係顯示習知封裝基板之製 法’如第1A圖所示，提供一核心板1〇，該核心板1〇具 有兩相對之表面10a，於該表面1〇a上形成有核心線路層 101 ’並於該核心板丨0中形成有導電通孔丨〇2，以電性連 接該核心板10表面10a之核心線路層101;如第α 不於該核心板10之表面1〇a及其上之核心線路層⑻ 2 土有第-介電層12a，且該第一介電層12a中形 …電層開孔120a，以顯露部份之核心線路層101;如 弟1C圖所示，於該第一介電層i2a上及其介 形成有導電層13,且於該導電層13上 2 “’並使該阻層14中形成有開口區 導電層！3之部份表面，且部份 == 電層開孔12〇a;如第— 〇對應各該介 1/1Λ ^ 弟1D圖所不，於該阻層14之開口區 140中的導電層13上電鍍形成有第一 £ 弟"電層12a之介電層開孔施中形成有第 孔15la，以電性連接至該核心線路層⑻；如第 ^ 不，移除該阻層14及其所 ^山圖 一線路層^如第心^ ¥電層13’以露出該第 第一介電層12&上开4右 於該第一線路層❿及 包括有 护/成有增層結構丨6,該增層結構16係 二介電層i2b、形成於該第二介電層上： 弟-線路層15b、以及複數形成於該第三介電層之中並電 Π0823 201002167 ‘性連接該第二線路層之第二導電盲孔151b，其中部份之 •第二導電盲孔151b電性連接該第一線路層心：如第π 圖所示，於該增層結構16最外層之第二線路層i5b形 •有複數電性接觸塾164,且於該增層結構16之最外声 =成有防焊们7,並於該防焊層17中形成有複數個二焊 曰開孔1 70以對應露出各該電性接觸墊丨64。 又該雷射鑽孔形成之介電層開孔120a係為外大内 之錐形孔，且於該錐形孔之底部因雷射形成有膠渣，使 該介電層開孔12〇a之孔壁、介電層開孔12〇&中之 路層m等表面與導電層13之間的結合性不佳，必:$ ^去膠渣（De槪ar)之製程，然後再 j 渣製程未必能將膠渣完全去除，且當錐形孔之孔4 軸查對後續再形成線路之結合性的影響越大二= :電：開孔12〇a顯露該核心線路層1〇1之底部的口徑較 ::面積，使得該第-導電盲孔仙與核心 之間的結合性降低，進而影響電性連接的可靠^層1〇1 且各該雷射鑽孔之精度及開孔的孔徑有里限益 法持續縮小，因而影響高 、、,、 線路製程能力之提升。 便用而求，有礙於細 因此，如何提高形成於該介電層開孔中之導 電性連接之線路之間的結合強度、及縮小介電二二 孔徑以提高佈線密产 丨晃層開孔之 【發㈣W 料在其技術瓶頸而有待克服。 110823 7 201002167 鑑於以上所述習知技術之缺201002167 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to an electrical connection structure of an interlayer circuit layer of a circuit board and a method of manufacturing the same. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-function and high-performance (four). The high-integration of the semiconductor package and the miniaturization (Miniaturizati〇n) package to carry the package substrate of the semi-body wafer, gradually evolved from a double-layer board to a Miilti-layer Board. In a limited space, the interlayer connection technology (interlayer c〇nnecti〇n) is used to expand the available circuit area on the package substrate to meet the demand for the use of a high electronic density integrated circuit (I, integrated circuit);遂 Developed a build-up technique in which a plurality of dielectric layers and circuit layers are alternately stacked on a surface of a core circuit board using a line build-up technique, and in the dielectric layer A conductive via is provided for electrically connecting the upper and lower lines. • In order to meet the computing needs of high-performance chips such as microprocessors, chipsets, edge chips, and special application integrated circuits (ASICs), the semiconductor substrate with wiring needs to improve its transfer of chip signals, improve bandwidth, and control impedance. Specialized month b' in response to the high i/G number of packages, U is in line with the semiconductor package is light and short, 'multi-function, ancient hitting · ·" return speed, south line density and high frequency direction, package substrate Developed toward thin wires and small apertures, the existing + ¥ body package substrate process has been reduced from the traditional (10) micron line size to 110823 5 201002167 to now less than 30 microns, including wire width (Une and line spacing (space) R&D continues to develop toward smaller line accuracy. 0. Referring to the first person to the figure, 'the method of displaying the conventional package substrate' is shown in FIG. 1A, and a core board 1 is provided. The core board 1 is provided. The crucible has two opposite surfaces 10a, and a core circuit layer 101' is formed on the surface 1a, and a conductive via hole 2 is formed in the core board ,0 to electrically connect the surface 10a of the core board 10. core The circuit layer 101; if the α is not on the surface 1〇a of the core board 10 and the core circuit layer (8) 2 on the ground has a first dielectric layer 12a, and the first dielectric layer 12a is shaped... The hole 120a is formed to expose a portion of the core circuit layer 101; as shown in FIG. 1C, a conductive layer 13 is formed on the first dielectric layer i2a, and a conductive layer 13 is formed on the conductive layer 13, and The resist layer 14 is formed with a part of the surface of the open region conductive layer! 3, and the portion == the electric layer opening 12 〇 a; if the first 〇 corresponds to each of the 1/1 Λ ^ 弟 1D map, The conductive layer 13 in the open region 140 of the resist layer 14 is plated with a first dielectric layer 12a. The dielectric layer is formed with a first hole 153a electrically connected to the core circuit layer (8). If the first layer is not removed, the resist layer 14 and its layer are removed, such as the first layer of the dielectric layer 13' to expose the first dielectric layer 12 & The circuit layer layer includes a protective layer/layered structure 6 and the second layer dielectric layer i2b is formed on the second dielectric layer: the gate layer 15b and the plurality of layers are formed in the first layer Between the three dielectric layers 823 201002167 'sexually connecting the second conductive blind via 151b of the second circuit layer, wherein a portion of the second conductive blind via 151b is electrically connected to the first interconnect layer core: as shown in FIG. The second circuit layer i5b of the outermost layer of the structure 16 has a plurality of electrical contacts 164, and the outermost sound of the layered structure 16 is formed with solder resists 7, and a plurality of solder resists 17 are formed in the solder resist layer 17. Two soldering holes 1 70 are formed to correspondingly expose the electrical contact pads 64. The dielectric layer opening 120a formed by the laser drilling is a tapered hole in the outer large hole, and the tapered hole is The bottom portion is formed with a slag due to the laser, so that the bonding between the surface of the hole of the dielectric layer opening 12 〇 a, the surface layer of the dielectric layer opening 12 amp & and the conductive layer 13 is not Good, must: $ ^ to the process of desmear (De槪ar), and then j slag process may not be able to completely remove the slag, and when the hole of the tapered hole 4 axis check the effect of the subsequent re-formation line The larger the two = : electricity: the opening 12〇a reveals that the diameter of the bottom of the core circuit layer 1〇1 is smaller than:: area, so that the bond between the first conductive blind hole and the core is lowered. Effect ^ and reliable electrical connection layer 1〇1 and a pore size of each of the laser drilling accuracy and hole are beneficial in limiting method continues to shrink, and thus high-impact ,,,, lifting capacity of the process line. In order to improve the bonding strength between the lines of the conductive connection formed in the opening of the dielectric layer, and to reduce the dielectric aperture to improve the wiring density, the wiring layer is opened. Kong Zhi [four (W) W material is in need of technical bottlenecks to be overcome. 110823 7 201002167 In view of the above-mentioned shortcomings of the prior art
山/ 之X目的係提供—種電路板及:M：製法，处L .南形成於該介電層開孔中之導電柱與其電I速處提 之間的結合強度。 /、/、' 妾之線路 發明之再-目的係提供—種電路板及其製法， J、Μ電層開孔之孔徑以提高佈線密度。 、 :達上述及其他目的’本發明揭露一種電路板 括.核心板，其具有相對之二表 路層.筮一入中a 衣®7於。亥表面具有核心線 設於211 係設於該核心板上；第一線路層，係 ;“ 電層上，且於該第一介電層中設有導電盲 孔以電性連接該ϋ路層；第二介電層，係設於該 二電層及第一線路層上；複數第一導電柱，係設於該第 二電層中’並電性連接該第—線路層，且該第—導電柱 之端，與第一介電層之表面齊平，·以及第二線路層，係設 ;/第"电層上，並具有複數電性連接墊以對應電性連 接至各該第一導電柱上。 -依上述之電路板，該核心板中具有導電通孔以電性連 接該核〜板之兩表面上的核心線路層；該電性連接墊係 大於、等於或小於該第一導電柱。 依上述之結構，復包括增層結構，係設於該第二介電 層及第二線路層上，該增層結構係包括有至少一第三介電 層、δ又於該第三介電層上之第三線路層、以及複數設於該 第二介電層之中並電性連接該第二及第三線路層之第二 8 110823 201002167 導電柱，該第二線路層復包括有複數電性連接墊，且該電 性連接墊係形成於該第二導電柱上，又該電性連接墊=大 於、等於或小於該第二導電柱。 依上所述，復包括複數電性接觸墊，係設於該增層結 構最外層之第三線路層，於該增層結構之最外層上設有防 焊層’並於該防焊I中設有複數個防焊層職， 出各該電性接觸墊。 〜 本發明復-種電路板，係包括：核心板，係具有相對 之二表面，於該表面具有核心線路層；第一介電層，係設 於該核心板上；第-線路層，係設於該第一介電層中並: 該第-介電層齊平，且該第一線路層具有複數第一導電 孔，以電性連接至該核心線路層；複數第一導電柱，係設 於該第一線路層上；以及增層結構，係設於該第一介； 層、第-線路層、及第-導電柱上，該增層結構並具有第 -線路層，且該第二線路層具有複數電 k:. 設於各該第一導電柱上。 按登以對應 依上述之電路板，該核心板中設有導電通孔 表面上的核心線路層;該第-介電層= 數弟-開孔及第一開槽’且該第一開孔露出部份之核 :各該第一線路層係設於該第一開槽中，並具有設 '各該第—開孔中之第一導電孔 路層’域電料接㈣切 依上述之結構，該增層結構係包括有至少—且 開槽之第二介/、有弟一 弟"電層、没於該第二介電層之第二開槽中之第 110823 9 201002167 二線路層、以及複數設於該第二介電 .m⑨中並電性連接該第 -搞層之第—導電柱，又該第二線路層之表面盘第 :層之表面齊平，該第二線路層復包括有複數電性軸 墊，且該些電性連接墊係對應設於各該第二 該電性連接塾係大於'等於或小於該第二導電柱。’且 外心所Ϊ二包括電性接觸墊，係設於該增層結構最 曰之第一線路4 ’於該增層結構之最外層上 層，並設有複數防焊層開孔， θ叹 ,^ τ題、路出各該電性接觸墊。 本毛明復提供-種電路板之製 心板，係具有相對之二表面，於_面係;;括4供一核 該核心板上形成有第一介電層；於該第 上形成有第一線路層，並 電0 孔，以電性連接# 介電層中形成有導電盲 錢形成有料層；”份之第-料層上電 -導電Γ上二=’於該第一介電層、第-線路層及第 π电狂上形成有第二介 ^ 層，以露出該第—道带L 曰 示口 Ρ份之第二介電 ΏΑ 電柱之端面，·於該第二介電層及導電 柱之碥面上形成有第丨^及導電 有第三阻層，且於兮s於該第二導電層上形成 以露出部份之第二：―阻層中形成有複數第三開口區， -導電柱之端面上的第:::之第三開口區對應該第 成有具有複數電性連接塾H層線路於声該第三開口區中形 墊對應電性遠M s A <弟一線路層，使該些電性連接 錢*主各該第—墓Φ · 層及其所覆蓋之第二導電層。I以及移除該第三阻 依上述電路板之製法，該核心板中形成有導電通孔以 110823 10 201002167 電性連接該核心板之兩表 •又依上述之製法，該第一=:線路層。 法’係包括：於該第一介電層中;及弟-導電桂之製 份之核心線路層上形層、盲孔之孔壁'及部 為成有弟-阻層，且該第— 弟-電層 露出部份之第-導電層，且部份c 一開口區以 -線路層，並於該盲孔中形成有導電盲：，=成有第 核心線路層；於該第一阻声 J'連接該 阻層，且該第二阻層Μ成曰有/二—線口路層上形成有第二 第一線路層；於該第二門口F由讦區，以露出部份之 柱；以及移除該第二阻形成有第-導電 電層。 "p 且層及其所覆蓋之第一導 後包括於該第二介電層及第二線路層上 ^構，該增層結構係包括有至少一第三介電層增層 弟二介電層上之室二綠放思 θ /成於s亥 μ “層、以及複數形成於該第三介雷 曰一並電性連接該第二及第三線路層之第二導 該第三線路層復包括有複數電性 ，又 成於各該第二導電柱上，且該=== 於、等於或小於該第二導電柱。 ’、大 復包括於該增層結構最外層之第三線路層步 數電性接觸墊，於該增層結構之最外層上形成有防^硬 亚於该防桿層中形成有複數個防焊層開孔’以對應露出曰各 110823 11 201002167 該電性接觸墊。 本發明復提供1電路板之製法 :板，係具有相對之二表面，於該表面上且有 =供一核 層；於該核心板上形成有 入 ，、有核心線路 •中开{忐古榮 w電層；於該第—介畲思 ::成有弟-線路層’且該第_線路層與 芦：層 士平，並於該第-介電層中形成有第電曰表面 接至該核心線路層；於邙 電孔，以電性連 二：電柱;以及於該第一介電層、第 =有 導電柱上形成有增層結構，該择 及弟一 路層，且該第-線路芦且古θ、、Ό 並形成有第二線 4-線路層具有複數電 於各該第-導電柱上。 侵！ w對應形成 依上述電路板之製法，該核心板中 電性連接該核心板之兩表面上的核心線路成層有導電通孔以 依上述之製法，該增層結構係包括有至少一且 開槽之第二介電層、形成於該第二介 一 路層、以及複數設於該第二介電層中並電性連接該 :-線路層之第二導電柱，又該第二線路層之表面盘第二 二電層之表面齊平’該第二線路層復包括有複數電性連接 墊，且該些電性連接墊係對應形成於各該第二導電柱上， 且該电性連接墊係大於、等於或小於該第二導電柱。 復包括於該增層結構最外層之第：線路層形成有複 、電性接觸墊，於該增層結構之最外層上形成有防谭層， 並於該防焊層中形成有複數個防焊層開孔以對應露出各 該電性接觸墊。 110823 12 201002167 成本發明之電路板及其製法，能形成導電柱作為層 路層之電性連接，而突 / s '、、 大砜_知猎由雷射於介電層進行開 可靠度 免產生膠渣的問題’以提高佈線密度及 【實施方式】 式，孰特定的具體實施例說明本發明之實施方 …技技人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 [第一實施例] 請參閱第2Α至2Μ圖，係顯示本發明 第-實施例之剖面示意圖。 ^月之電路板之製法 如弟2Α圖所示，首弁接很 ,. 之亥心板20 ’其具有相對 & ’於該表& 2〇a具有核心線路層2(Π，且节 核心板20中具有導雷诵？丨9η9 、，& 藏 之兩矣而1电性連接該核心板20 之兩表面20a上的核心線路層2〇1。 如第㈣所示’於該核心板2〇上形成有第一介電居 a且遠第一介電層21a中形成有複數盲孔 、: 出部份之核心線路層2 〇 1。 a以路 如第2C圖所示，於該第—介電 孔壁、及部份之核心線路層2〇1上 目孔210&之 ^之後，於該第一導電層22a上形成=弟-導電層 且該第-阻層23a中形成有第—開 阻層23a’ 之第-導電層22a，且部份之第= \23〇a以露出部份 孔2l〇a及其孔端周圍之第_導電層仏區230a對應該盲 110823 13 201002167 .緣路：=圖所示:於該第—開口區⑽中形成有第-線路層24a，亚於該盲孔2iGa中形成有導電盲孔 以電性連接至該核心線路層。 a， , %第2E圖所示，於該第-阻層23a上形成有第_r 層^’且該第二阻層挪中以曝光顯影方式快 複數第：開口區通’以露出部份之第一線路層％。有 如弟2F圖所示，藉由該第—導電層仏及第 二:=電流傳導路徑，以於該第二開口區_中： 23^-^23a 及第一導電柱25a。 #、線路層24a 如第2H圖所示，於該第一介電層2i MAI 成有第二介電層21b。 電声21b ,ν 1Φ^以係如刷磨方式移除部份之第一介 罨暦21b，以露出該第一 乐一）丨 如第2J圖所-導電柱25a之端面251a。 ❿之端面251a€^21b及第—導電柱 二導電層22b上形成有弟一導^層22b;接著，於該第 ., 巧第二阻層23c’且於兮筮- 230c,^；,；；；^ 層22b，且部份之第二 纷® °丨伤之第二導電 之端面251a上的第：：口區23〇C對應該第-導電柱25a 弟一導電層22b。 如第2K圖所示，於 、〜第二開口區230c中形成具有複 110823 14 201002167 2電性連接墊242b之第二線路層24b，且該電性連接整 .242b位於該第一導電柱25a上，該電性連接墊地並大 •於、等於或小於該第一導電柱25a。 ' 如第2L圖所示，移除該第三阻層23c及其所覆蓋之 .第二導電層22b，以露出該第二線路層24b。 孤 ' 如第2M圖所示，於該第二介電層21b及第二線路層 24^上形成有增層結構26，該增層結構26係包括有至少 -第三介電層21c、形成於該第三介電層上之第三線路二 …24c以及複數形成於該第三介電層之中並電性連接該第 二線路層之第二導電柱25b，其中部份之第二導電柱25b 電性連接該第二線路層24b，該第三線路層仏復包 數電性連㈣242c，且該電性連純处係形成於該第 二導電柱25b上，該電性連接墊242c係大於、等於或小 於該第二導電柱25b，又於該增層結構26最外層之第三 線路層24c形成有複數電性接觸塾m，且於該^層^ ν. 26之最外層上形成有防焊層27，並於該防焊層^中开;成 ^复數個防焊層開孔27G以對應露出各該電性接 Z64 〇 本發明復提供-種電路板，係包括：核心板2〇，係 具有相對之二表面20a，於該表面2〇a具有核心線路層 201，第-介電層21a，係設於該核心板2()上；第—線路 層24a’係設於該第一介電層21a上，且於該第一介電層 21a中設有導電盲孔241a，以電性連接該核心線路^ 201，弟一介電層21b，係設於該第—介電層…及第一 ]10823 15 201002167 線路層24a上；複數第一導餘❿，係設於該第二 層21b中，並電性連接該第一線路層 、心之端面251a與第二介電層21b之表面電 線路層24b，係設於該第二介電層21b上，並具 性連接塾242b’以對應電性連接至各該第一導電柱❿ 上。 依上述之電路板，該核心板2〇中具有導電通孔2〇2 Γ〇Γ=該Γ板20之兩表面2 一 201’復包括增層結構26,係設於該第二介電層2ib 二線路層24b上’該增層結構26係包括有至少人 =广形成於該第三介電層上之第三線路層2二 介電層之中並電性連接該第三線路 其中部份之第二導電柱25b電性連 連接 1 =路層24b’該第三線路層24c復包括複數電性 242c，且該電性連接塾⑽係形成於 = 連接塾2版係大於、等於或小於= ^开成有Γ於該增層結構26最外層之第三線路層 =成有稷數電性接㈣264，且於該增層結構％之最 :=1Γ，27’！於該防焊層27中形成有複數 Γ ^ 270以對應露出各該電性接觸墊264。 !_第—貫施例j 閱第3Α至3Ρ圖’係顯示本發明之電路板之製法 乐一霄施例之剖面示意圖。 如第3Α圖所示’提供一係如第2α圖所示之結構。 Π0823 16 201002167 如第3β圖所示，於該核心板20上形成有第—介電層 21a，且於該第一介電層21a中形成有複數第一開孔 及第一開槽212a，且該第一開孔211a露出部份之核心線 路層 201。 乂。、” 如第3C圖所示，於該第一介電層21a、第—開孔Mi 及第一開槽212a之孔壁、及部份之核心線路層2〇1上形 成有第一導電層22a。 乂 如第3D圖所示 金屬層24卜且於該第-開槽212a中形成有第一線❹ 24a，並於該第一開孔211a中形成有第一導電孔Mu。曰 如第3E及3E，圖所示，薄化該第一金屬層24丨，以 為第-薄化金屬層241，，如第3£圖所示；或完全 形成該第-線路層24a及第一導電孔2仙之第 241及為該第一金屬層所覆蓋之第-導電層22a，以心 該第一線路層24a及第一導雷a 9yMu 出 a 01 ^ 乐V電孔241b，再於該第一介 層21a、第一線路層24a及第一 ^ 、、· 入禾 v電孔241b上形成有另 一導電層22a，，如第3E,圖所干· > & ^ 有另 結構作說明。 所示之 如弟圖所示 ^ 得化金屬層24Γ上形忐士 弟一阻層23a，且於該第—阻 成有 _ ΟΟΛ 阻層23a中形成有複數第一 ρ气 口區230a，以對應露出部份 開 ,^ qr ^ ^ _ 1仞之弟一缚化金屬層241，。 如弟3G圖所不，於辞耸 %逆弟一開口 金屬層241，上電鍍形成有 2施中之第—薄化 如第3H圖所示，移除 往25a °〆弟一阻層23a及其所覆蓋之 110823 17 201002167 第-薄化金屬層241，及第_導電層22a，以露出該第一線 路層24a’並於該第一線路| 24&上形成該第一導電柱 25a’且使該第-線路層24a與第—介電層…之表 平。 如第31圖所示’於該第一介電層…、第一線路層 2如、及第-導妹25a上形成有第二介電層心，且於 該第-；I電層21b中形成有複數第二開槽2Ub，且該第 二開槽2Ub露出該些第一導電柱25a之端面251&。 如第3J圖所示’於該第二介電層別、第二開槽 之孔壁、及第一導電柱25a之端面251a上形成有第二導 電層22b。 如第3K圖所示，於該第二導電層奶上形成有第二 金屬層242’且於該第二開槽mb中形成具有複數電性 連接墊242b之第二線路層24b，且該電性連接墊2伽位 於該第-導電柱25a上，該電性連接墊242b並大於、等 於或小於該第一導電柱25a。 卜—及3L’圖所示，薄化該第二金屬層242，以成 為第二薄化金屬層242，，如第3L圖所示；或移除未形成 該第二線路層24 b及電性連接塾之第二金屬層如 及第二導電層22b 再於該第二介電層⑽、該第二線 路層24b及電性連接墊_上形成有另一導電層挪，， 如第3匕圖所不’之後以第礼圖所示之結構作說明。 〃如第3M圖所不，於該第二薄化金屬|⑽，上形成有 第-阻層23b’且於該第二阻層伽中形成有複數第二開 110823 18 201002167 口區230b，以露出部份夕哲 _ ®丨伤之第二薄化金屬層242 中形成有 如弟3 N圖所示，;^守货 第 丁於該弟二開口區230b 導電柱25b。 如第30圖所*，移除該第二阻層聊及 第二薄化金屬層242,及第二導電層⑽，以露出該J盍： 路層24b及第二導電柱25b。 乐—綠 如第3P圖所示，重覆前述之第31至3〇圖 以形成增層結構26,該增層結構26係包括有至少一： 第f開槽㈣之第二介電層21b、形成於該第二介電層 之弟二開槽211b中之第-綠曰 弟—線路層24b、以及複數形成於 該弟一；I電層中並電性連接該第二線路層2牝之第二導 電柱25b，又該第二線路層24b之表面與第二介電層一2ib 之表面齊平；於該增層結構26最外層之第二線路層S 2仆 形成有複數電性接觸塾264,且於該增層結構26之最外 層上形成有防焊層27，並於該防焊層27中形成有複數個 防焊層開孔270以對應露出各該電性接觸墊264。 本發明復提供一種電路板，係包括：核心板2〇，係 具有相對之二表面20a，於該表s 2〇a #有核心線路層 201’第一介電層21a，係設於該核心板2〇上，並設有複 =第—開孔211a及第一開槽212a，且該第—開孔2Ua 露出部份之核心線路層201;第一線路層24a，係設於該 第開槽212a中，並具有複數第一導電孔241b，且對應 設於各該第一開孔211a中，以電性連接至該核心線路層 2〇1，又該第一線路層24a之表面與第一介電層21a之表 110823 19 201002167 面齊平，複數第一導電柱25a，係設於該第一線路層24a 上’以及增層結構2 6，係設於該第一介電層21 a、第一 線路層24a、及第一導電柱25a上，該增層結構26並具 有第二線路層24b，且該第二線路層24b具有複數電性連 接墊242b，以對應設於各該第一導電柱25&上。 依上述之電路板，該核心板2〇中設有導電通孔202 以電性連接該核心板20之兩表面20a上的核心線路層 20卜 依上述之結構’該電性連接墊242b係大於、等於或 小於該第一導電柱25a。 又依上所述，該增層結構26係包括有至少一具有第 二開槽211b之第二介電層21b、設於該第二介電層2化 之第一開槽211b中之第二線路層24b、以及複數設於該 $二介電層21b中並電性連接該第二線路層2扑之第二導 電柱25b，又該第二線路層2扑之表面與第二介電層 之表面齊平；該第二線路層24b復包括有複數電性連接 =242b’且該些電性連接墊2421)係對應設於各該第二導 電柱25b上；又該電性連接塾襲係大於、等於或小於 該第二導電柱25b;復於該增層結構26最外層之第二線 路層2U電性接觸塾264，於該增層結構^之最 有防焊層27 '該防焊層27並設有複數防焊層 開孔270,以對應露出各該電性接觸墊264。 路父板及其製法’能形成導電柱作為層間線 電連接’而可突破習知藉由雷射於介電層進行開 110823 20 201002167 .孔之孔㈣似避免產生膠㈣_，以提高佈線密度及 可靠度。 • 上述實施例係用以例示性說明本發明之原理及其功 效’而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範訂，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A至1G圖係為習知電路板及其製法之剖視示意 圖； 第2A至2M圖係為本發明電路板及其製法第一實施例 剖視圖； 第3A至3P圖係為本發明電路板及其製法第二實施例 剖視圖； 【主要元件符號說明】 10、20 核心板 10a ' 20a 表面 101 、 201 核心線路層 102 、 202 導電通孔 12a、21a 第一介電層 12b 、 21b 弟—介電層 120a 介電層開孔 f3E’圖係為第3E圖之另一實施例剖視圖；以及 第3L圖係為第3L圖之另一實施例剖視圖。 21 110823 201002167 13 * 14 '140 15a 、 24a ' 151a 15b > 24b 151b 16、26 164 、 264 17、27 170 、 270 210a 211a 212a 211b 21cThe mountain / X objective is to provide a kind of circuit board and: M: method, where the strength of the bond between the conductive pillar formed in the opening of the dielectric layer and the electric I speed is raised. /, /, ' 妾 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的The present invention discloses a circuit board comprising a core board having two opposite surface layers. The core surface has a core line disposed on the core plate 211; the first circuit layer is; "on the electrical layer, and a conductive blind hole is disposed in the first dielectric layer to electrically connect the circuit layer a second dielectric layer is disposed on the second electrical layer and the first circuit layer; a plurality of first conductive pillars are disposed in the second electrical layer and electrically connected to the first circuit layer, and the first - the end of the conductive post is flush with the surface of the first dielectric layer, and the second circuit layer is provided on the / electrical layer, and has a plurality of electrical connection pads to electrically connect to each of the a first conductive column. - according to the circuit board, the core plate has conductive through holes for electrically connecting the core circuit layers on the two surfaces of the core to the board; the electrical connection pads are greater than, equal to or less than The first conductive pillar. According to the above structure, the multi-layered structure is disposed on the second dielectric layer and the second circuit layer, the build-up structure includes at least one third dielectric layer, and δ a third circuit layer on the third dielectric layer and a plurality of the second dielectric layer are electrically connected to the second dielectric layer The second 8 110823 201002167 conductive column of the three circuit layer, the second circuit layer further comprises a plurality of electrical connection pads, and the electrical connection pad is formed on the second conductive column, and the electrical connection pad is greater than The second conductive pillar is equal to or smaller than the second conductive pillar. According to the above, the plurality of electrical contact pads are disposed on the third circuit layer of the outermost layer of the buildup structure, and the outermost layer of the buildup structure is provided with an anti-layer The soldering layer 'and a plurality of solder masks are provided in the solder resist I, and each of the electrical contact pads is provided. ~ The composite circuit board of the present invention comprises: a core board having opposite surfaces, The surface has a core circuit layer; a first dielectric layer is disposed on the core plate; a first circuit layer is disposed in the first dielectric layer and: the first dielectric layer is flush, and the first a circuit layer having a plurality of first conductive holes electrically connected to the core circuit layer; a plurality of first conductive pillars disposed on the first circuit layer; and a build-up structure disposed on the first dielectric layer; And the first-line layer and the first-conducting column, the build-up structure has a first-line layer, and the The second circuit layer has a plurality of electric charges k: provided on each of the first conductive pillars. According to the circuit board corresponding to the above, the core board is provided with a core circuit layer on the surface of the conductive via hole; The electric layer = the number of the first hole - the opening and the first slot and the core of the exposed portion of the first opening: each of the first circuit layers is disposed in the first slot and has a setting of each of the first The first conductive via layer in the opening is formed by the above-mentioned structure, and the build-up structure includes at least one of the second slotted and/or has a younger brother" a 110823 9 201002167 second circuit layer in the second slot of the second dielectric layer, and a plurality of first conductive layers disposed in the second dielectric .m9 and electrically connected to the first conductive layer, The surface of the surface layer of the second circuit layer is flush; the second circuit layer includes a plurality of electrical axial pads, and the electrical connection pads are correspondingly disposed on the second electrical connection. The system is greater than 'equal to or smaller than the second conductive column. And the external contact includes an electrical contact pad, which is disposed on the uppermost layer 4' of the layered structure, and is provided on the outermost layer of the layered structure, and is provided with a plurality of anti-welding layer openings, θ sigh , ^ τ questions, out of each of these electrical contact pads. The present invention provides a core plate of a type of circuit board having opposite surfaces, a surface layer, and a core for forming a first dielectric layer on the core plate; The first circuit layer is electrically connected to the 0 hole, and is electrically connected. The conductive layer is formed in the dielectric layer to form a material layer; the first layer of the layer is electrically charged - the conductive layer is on the second layer = 'the first dielectric layer a second dielectric layer is formed on the layer, the first-line layer, and the π-electrode to expose an end surface of the second dielectric grid of the first channel L, and the second dielectric a layer of a layer and a conductive pillar are formed with a third conductive layer and a conductive third resistive layer, and the second conductive layer is formed on the second conductive layer to form a second portion of the exposed portion: a plurality of third layers are formed in the resist layer The opening area, the third opening area of the first::: on the end surface of the conductive column corresponds to the first layer having a plurality of electrical connections, the layer of the H layer is sounded, and the shape of the third opening area is corresponding to the electrical distance M s A <Digital circuit layer, so that the electrical connection money * the main tomb Φ · layer and the second conductive layer covered by it. I and remove the third barrier according to the above circuit board In the method, the conductive plate is formed with a conductive through hole to electrically connect the two tables of the core plate with 110823 10 201002167. According to the above method, the first =: circuit layer. The method includes: the first dielectric In the layer; the upper layer of the core circuit layer, the hole wall of the blind hole, and the portion of the hole-resistant layer, and the first-conducting portion of the exposed portion of the first-dipole-electric layer a layer, and a portion c of an open region is a circuit layer, and a conductive blind is formed in the blind hole: = a core circuit layer is formed; the resist layer is connected to the first sound blocking J', and the a second first circuit layer is formed on the second resistive layer/曰-line layer; the second gate F is formed by the buffer region to expose a portion of the pillar; and the second resistor is formed a first conductive layer and a first layer covered by the first conductive layer and the second conductive layer, the build-up structure comprising at least a third dielectric The second layer of the second layer is electrically connected to the third layer and the third layer is electrically connected to the second and third layers. Second guide passage of the third layer wiring layer comprises a plurality of electrically multiplexed, and as in each of the second conductive pillar, and the === than, equal to or smaller than the second conductive pillar. ', the large complex includes the third circuit layer step electrical contact pad at the outermost layer of the buildup structure, and the outermost layer of the buildup structure is formed with a plurality of anti-hard layers formed in the anti-bar layer The solder layer is opened to correspond to the exposed contact pads 110823 11 201002167. The invention provides a method for manufacturing a circuit board: a board having opposite surfaces on the surface and having a core layer; forming an in-core on the core board, and having a core line; Rongw electrical layer; in the first - Jiesi thinking:: into the brother-circuit layer 'and the _ circuit layer and the reed: layer Shi Ping, and the first dielectric layer is formed with the surface of the first electrical interface To the core circuit layer; in the electrical hole, electrically connected to the second: the electric column; and the first dielectric layer, the first conductive column has a build-up structure, the selected one-way layer, and the first - The line is remarked and the θ, Ό is formed with the second line 4-the wiring layer has a plurality of electric currents on each of the first conductive pillars. Invade! The method of forming the circuit board according to the above method, wherein the core circuit electrically connected to the core lines on the two surfaces of the core board is formed with a layer of conductive via holes according to the above method, and the layered structure includes at least one and slotted a second dielectric layer, a second dielectric layer, and a plurality of second conductive layers disposed in the second dielectric layer and electrically connected to the circuit layer, and the surface of the second circuit layer The surface of the second and second electrical layers of the disk is flush. The second circuit layer includes a plurality of electrical connection pads, and the electrical connection pads are formed on each of the second conductive columns, and the electrical connection pads are The system is greater than, equal to, or less than the second conductive pillar. The circuit layer is formed on the outermost layer of the build-up structure: a circuit layer is formed with a composite electrical contact pad, an anti-tantal layer is formed on the outermost layer of the build-up structure, and a plurality of anti-solder layers are formed in the solder resist layer The solder layer is opened to correspondingly expose each of the electrical contact pads. 110823 12 201002167 The circuit board of the invention and its preparation method can form a conductive column as an electrical connection of the layer layer, and the protrusion / s ', and the large sulfone _ hun hun ray from the dielectric layer to open the reliability to avoid generation The problem of the slag is to improve the wiring density and the embodiment of the present invention. The specific embodiments of the present invention are described in detail. Those skilled in the art can easily understand other advantages and effects of the present invention from the disclosure of the present specification. [First Embodiment] Referring to Figures 2 to 2, there are shown schematic cross-sectional views of a first embodiment of the present invention. ^月的电路板制制法如弟2Α图,首首接接,. The Haixin board 20' has a relative & 'On the table & 2〇a has a core circuit layer 2 (Π, and The core board 20 has a conductive layer 丨 9 9 9 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A first dielectric layer is formed on the board 2, and a plurality of blind holes are formed in the first dielectric layer 21a, and the core circuit layer 2 〇1 is formed. The road is as shown in FIG. 2C. After forming the first dielectric layer 22a, the first conductive layer 22a is formed on the first conductive layer 22a, and the first resistive layer 23a is formed in the first dielectric layer 22a. The first conductive layer 22a of the first-opening resist layer 23a', and the portion of the second portion \ \ 〇 a to expose a portion of the hole 2l 〇 a and the first conductive layer 230 region 230a around the hole end corresponds to the blind 110823 13 201002167 . The edge path: = shown in the figure: a first circuit layer 24a is formed in the first opening region (10), and a conductive blind hole is formed in the blind hole 2iGa to be electrically connected to the core circuit layer. , , % As shown in FIG. 2E, a first _r layer is formed on the first resist layer 23a, and the second resist layer is formed by exposing the development mode to a plurality of openings: the open region is turned on to expose a portion of the first circuit layer. As shown in FIG. 2F, the first conductive layer and the second:= current conduction path are in the second opening region _: 23^-^23a and the first conductive pillar 25a. As shown in FIG. 2H, the circuit layer 24a has a second dielectric layer 21b formed on the first dielectric layer 2i. The electroacoustic 21b, ν1Φ^ removes a portion of the first dielectric layer by brushing.暦21b, to expose the first end of the first pole, such as the end face 251a of the conductive post 25a. a second layer 22b is formed on the end surface 251a2^21b of the crucible and the second conductive layer 22b of the first conductive pillar; then, in the second, the second resist layer 23c' and the crucible - 230c, ^; The layer 22b, and the portion of the second conductive surface 251a of the second portion of the wounded portion 251a corresponds to the first conductive pillar 25a. As shown in FIG. 2K, a second wiring layer 24b having a plurality of electrical connection pads 242b of 110823 14 201002167 2 is formed in the second opening region 230c, and the electrical connection is located at the first conductive pillar 25a. The electrical connection pad is greater than, equal to, or smaller than the first conductive pillar 25a. As shown in FIG. 2L, the third resist layer 23c and the second conductive layer 22b covered therein are removed to expose the second wiring layer 24b. As shown in FIG. 2M, a build-up structure 26 is formed on the second dielectric layer 21b and the second circuit layer 24, and the build-up structure 26 includes at least a third dielectric layer 21c. a third line 2...24c on the third dielectric layer and a plurality of second conductive pillars 25b formed in the third dielectric layer and electrically connected to the second wiring layer, wherein a portion of the second conductive portion The pillar 25b is electrically connected to the second circuit layer 24b, and the third circuit layer is electrically connected to the electrical connection (four) 242c, and the electrical connection is formed on the second conductive pillar 25b. The electrical connection pad 242c The second conductive layer 25b is greater than, equal to or smaller than the second conductive pillar 25b, and the third electrical wiring layer 24c of the outermost layer of the buildup structure 26 is formed with a plurality of electrical contacts 塾m, and on the outermost layer of the layer ν. A solder resist layer 27 is formed and opened in the solder resist layer; a plurality of solder resist layer openings 27G are formed to correspondingly expose the respective electrical contacts Z64. The present invention provides a circuit board comprising: a core The board 2 has an opposite surface 20a, and the surface 2〇a has a core circuit layer 201, and a first dielectric layer 21a is disposed on the core board 2() The first circuit layer 24a is disposed on the first dielectric layer 21a, and a conductive blind hole 241a is disposed in the first dielectric layer 21a to electrically connect the core line ^201. The second layer 21b is electrically connected to the first layer The circuit layer, the end surface 251a of the core, and the surface circuit layer 24b of the second dielectric layer 21b are disposed on the second dielectric layer 21b, and are electrically connected to the first 222b' to electrically connect to each of the first Conductive column ❿. According to the above circuit board, the core board 2 has a conductive through hole 2 〇 2 Γ〇Γ = the two surfaces 2 - 201 ′ of the Γ board 20 include a build-up structure 26, which is disposed on the second dielectric layer The second layer of the second circuit layer 24b includes a second dielectric layer formed on the third dielectric layer and electrically connected to the middle portion of the third circuit. The second conductive pillar 25b is electrically connected 1 = the road layer 24b'. The third circuit layer 24c includes a plurality of electrical 242c, and the electrical connection 10 (10) is formed at the = 塾 2 system is greater than, equal to or Less than = ^ is opened to the third circuit layer of the outermost layer of the build-up structure 26 = has a number of electrical connections (four) 264, and the most % of the build-up structure: = 1 Γ, 27 '! A plurality of Γ ^ 270 are formed in the solder resist layer 27 to correspondingly expose the respective electrical contact pads 264. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ As shown in Fig. 3, a structure as shown in Fig. 2α is provided. Π0823 16 201002167 As shown in FIG. 3β, a first dielectric layer 21a is formed on the core plate 20, and a plurality of first openings and first slots 212a are formed in the first dielectric layer 21a, and The first opening 211a exposes a portion of the core wiring layer 201. Hey. As shown in FIG. 3C, a first conductive layer is formed on the first dielectric layer 21a, the first opening 304 and the first slot 212a, and a portion of the core circuit layer 2〇1. 22a. As shown in FIG. 3D, a metal layer 24 is formed, and a first coil 24a is formed in the first opening 212a, and a first conductive hole Mu is formed in the first opening 211a. 3E and 3E, as shown, the first metal layer 24 is thinned to be the first thinned metal layer 241, as shown in FIG. 3; or the first wiring layer 24a and the first conductive via are completely formed. The second conductive layer 241 and the first conductive layer 22a covered by the first metal layer, the first circuit layer 24a and the first lightning guide a 9yMu are a 01 ^ Le V electric hole 241b, and then Another conductive layer 22a is formed on the first layer 21a, the first wiring layer 24a, and the first and second via holes 241b, as shown in FIG. 3E, and the other structures are made. Illustrated as shown in the figure, the metal layer 24 is formed on the upper layer of the barrier layer 23a, and a plurality of first ρ port regions 230a are formed in the first barrier layer 23a. Corresponding to the exposed part份开, ^ qr ^ ^ _ 1 仞 一 一 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚 缚As shown in FIG. 3H, the first resistive layer 23a and the 110823 17 201002167 first thinned metal layer 241 and the first conductive layer 22a are removed to expose the first wiring layer 24a. And forming the first conductive pillar 25a' on the first line|24& and flattening the surface of the first wiring layer 24a and the first dielectric layer... as shown in Fig. 31 a second dielectric layer is formed on the first layer 2, and the first layer 25a, and a plurality of second slots 2Ub are formed in the first-electrode layer 21b, and the first layer The second slot 2Ub exposes the end faces 251 & of the first conductive pillars 25a. As shown in FIG. 3J, 'the second dielectric layer, the second slotted hole wall, and the end surface 251a of the first conductive pillar 25a. A second conductive layer 22b is formed thereon. As shown in FIG. 3K, a second metal layer 242' is formed on the second conductive layer milk and a plurality of electrical connection pads 242b are formed in the second trench mb. a second circuit layer 24b, and the electrical connection pad 2 is located on the first conductive pillar 25a, and the electrical connection pad 242b is greater than, equal to, or smaller than the first conductive pillar 25a. Thinning the second metal layer 242 to form the second thinned metal layer 242, as shown in FIG. 3L; or removing the second metal layer not forming the second wiring layer 24b and the electrical connection germanium For example, the second conductive layer 22b and the second dielectric layer (10), the second circuit layer 24b, and the electrical connection pad _ are formed with another conductive layer, as shown in the third figure. The structure shown in the ceremony diagram is for explanation. For example, in the second thinned metal|(10), a first resistive layer 23b' is formed thereon, and a plurality of second openings 110823 18 201002167 are formed in the second resistive layer gamma to The exposed portion of the second thinned metal layer 242 of the 夕 _ _ 丨 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ As shown in FIG. 30, the second barrier layer and the second thinned metal layer 242, and the second conductive layer (10) are removed to expose the via layer 24b and the second conductive pillar 25b. Le-green as shown in FIG. 3P, repeating the aforementioned 31st to 3rd views to form a build-up structure 26, the build-up structure 26 comprising at least one: a second dielectric layer 21b of the f-th slot (four) a first-green brother-circuit layer 24b formed in the second trench 211b of the second dielectric layer, and a plurality formed in the first one; the first electrical layer and electrically connected to the second circuit layer 2 The second conductive pillar 25b, the surface of the second circuit layer 24b is flush with the surface of the second dielectric layer 2ib; the second circuit layer S2 of the outermost layer of the buildup structure 26 is formed with a plurality of electrical properties. A solder resist layer 27 is formed on the outermost layer of the build-up structure 26, and a plurality of solder resist openings 270 are formed in the solder resist layer 27 to correspondingly expose the respective electrical contact pads 264. . The present invention further provides a circuit board comprising: a core board 2〇 having opposite surface 20a, wherein the table s 2〇a # has a core circuit layer 201 ′, a first dielectric layer 21a, is disposed at the core The first circuit layer 201 is formed on the board 2, and is provided with a first opening/first opening 211a and a first opening 212a, and the first opening layer 2a is exposed. The slot 212a has a plurality of first conductive holes 241b, and is correspondingly disposed in each of the first openings 211a to be electrically connected to the core circuit layer 2〇1, and the surface of the first circuit layer 24a and the first The surface 110823 19 201002167 of a dielectric layer 21a is flush, a plurality of first conductive pillars 25a are disposed on the first wiring layer 24a, and a build-up structure 26 is disposed on the first dielectric layer 21a. The first circuit layer 24a and the first conductive pillar 25a, the build-up structure 26 has a second circuit layer 24b, and the second circuit layer 24b has a plurality of electrical connection pads 242b corresponding to each of the first A conductive column 25 & According to the above circuit board, the core plate 2 is provided with a conductive via 202 for electrically connecting the core circuit layer 20 on the two surfaces 20a of the core board 20. According to the above structure, the electrical connection pad 242b is larger than Is equal to or smaller than the first conductive pillar 25a. In addition, the build-up structure 26 includes at least one second dielectric layer 21b having a second recess 211b and a second dielectric layer 211b disposed in the second dielectric layer. a circuit layer 24b, and a plurality of second conductive pillars 25b disposed in the second dielectric layer 21b and electrically connected to the second circuit layer 2, and the surface of the second circuit layer 2 and the second dielectric layer The surface of the second circuit layer 24b includes a plurality of electrical connections = 242b' and the electrical connection pads 2421 are correspondingly disposed on each of the second conductive posts 25b; The second conductive layer 25b is greater than, equal to or smaller than the second conductive layer 25b; the second circuit layer 2U of the outermost layer of the build-up structure 26 is electrically contacted with the germanium 264, and the most protective layer 27 of the build-up structure The solder layer 27 is provided with a plurality of solder mask openings 270 to correspondingly expose the respective electrical contact pads 264. The road parent board and its method of 'can form a conductive column as the interlayer line electrical connection' can be broken through the laser to open the dielectric layer 110823 20 201002167. The hole of the hole (four) seems to avoid the production of glue (four) _ to improve the wiring density And reliability. The above embodiments are intended to illustrate the principles of the invention and its functions, and are not intended to limit the invention. Any of the above-described embodiments can be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are schematic cross-sectional views of a conventional circuit board and a method of manufacturing the same; FIGS. 2A to 2M are cross-sectional views showing a first embodiment of a circuit board and a method of manufacturing the same according to the present invention; FIGS. 3A to 3P A cross-sectional view of a second embodiment of the circuit board of the present invention and its manufacturing method; [Description of main components] 10, 20 core board 10a ' 20a surface 101, 201 core circuit layer 102, 202 conductive vias 12a, 21a first dielectric layer 12b, 21b - Dielectric layer 120a Dielectric layer opening f3E' is a cross-sectional view of another embodiment of FIG. 3E; and 3L is a cross-sectional view of another embodiment of FIG. 3L. 21 110823 201002167 13 * 14 '140 15a , 24a ' 151a 15b > 24b 151b 16, 26 164 , 264 17 , 27 170 , 270 210a 211a 212a 211b 21c
K 22a 22b 22c 22a，，22b， 23a 230a 23b 230b 導電層 阻層 開口區 第一線路層 第一導電盲孔 第二線路層 第二導電盲孔 增層結構 電性接觸墊 防焊層 防焊層開孔 盲孔 第一開孔 第一開槽 第二開槽 第三介電層 第一導電層 第二導電層 第三導電層 另一導電層 第一阻層 第一開口區 第二阻層 第二開口區 201002167 23c 230c '241 241’ "242 241a 241b 242’ 242b ' 242c 24c 25a 251a 25b 第三阻層 第三開口區 第一金屬層 第一薄化金屬層 第二金屬層 導電盲孔 第一導電孔 第二薄化金屬層 電性連接墊 第三線路層 第一導電柱 端面 第二導電柱 23 110823K 22a 22b 22c 22a,, 22b, 23a 230a 23b 230b Conductive layer resistive open area first line layer first conductive blind hole second line layer second conductive blind hole build-up structure electrical contact pad solder resist layer solder resist layer Open hole blind hole first opening first slot second slot third dielectric layer first conductive layer second conductive layer third conductive layer another conductive layer first resist layer first open region second resist layer Two open areas 201002167 23c 230c '241 241' "242 241a 241b 242' 242b ' 242c 24c 25a 251a 25b third resistive layer third open area first metal layer first thinned metal layer second metal layer conductive blind hole a conductive hole second thinned metal layer electrical connection pad third circuit layer first conductive column end face second conductive column 23 110823