200819004 ‘ 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種嵌埋被動元件之電路板結構，尤 指一種將被動元件嵌埋於電路板中之結構。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 - 能、高性能的方向研發。為滿足半導體封裝件高積集度 - (Integration )以及微型化的封裝需求，提供多數主、被 馨動元件及線路載接之電路板，亦逐漸由單層板演變成多層 板，俾於有限的空間下，藉由層間連接技術擴大電路板上 可利用的電路面積以因應高電子密度之積體電路之使用需 求0200819004 ′ IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure in which a passive component is embedded, and more particularly to a structure in which a passive component is embedded in a circuit board. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance development. In order to meet the high integration of semiconductor packages - (Integration) and miniaturized packaging requirements, most of the main, singular components and circuit-loaded circuit boards are provided, and gradually evolved from single-layer boards to multi-layer boards. In the space, the circuit area available on the circuit board is expanded by the inter-layer connection technology to meet the demand for the use of integrated circuits with high electron density.
為提高電路板之佈線精密度，業界發展出一種增層技 術（Build-up)，亦即在一核心板表面利用線路增層技術交互 形成複數介電層及線路層，並於該介電層中形成有複數導 電結構，如導電盲孔（Conductive via)及電鍍導通孔（plating through hole，PTH)以供上下層線路之間的電性連接。 此外，又隨著各式電子產品輕薄短小化之發展趨勢， 業界遂發展出將如半導體晶片等主動元件，或係如電阻、 電容、電感等被動元件嵌埋於電路板中，之後於該電路板 上製作線路，藉以形成嵌埋主、被動元件之電路板結構。 習知在電路板中嵌埋被動元件及製作電鍍導通孔的 方式，請參閱第1A至1H圖。 如第1A圖所示，提供一係如樹脂壓合銅箔之核芯板 5 19707 200819004 Π，該核芯板11之表面具有薄金屬層lla，且於該核芯板 11中形成有至少一貫穿開孔11()。 如第1B圖所示，於該核芯板n表面之薄金屬層lla 及開孔110中形成有一導電層12，藉由該導電層12具有 導電之特性以供後續之電鍍製程。 如第1C圖所示，於該核芯板i丨表面之薄金屬層} J a 及開孔110中的導電層12表面電鍍形成一金屬層13，以 於该開孔110中形成一空心部i 12的導電結構。 如第1D圖所示，接著於該開孔11〇中的空心部112 真入係如树爿曰之基孔材料丨4，以將該空心部丨〗2填滿，避 免在電路板結構中因空洞所包含的氣泡導致後續熱循環製 程中產生爆板的情況。 如第1E圖所示，然後該金屬層13、導電層12及薄金 屬層lla進订圖案化製程以在核芯板u表面形成第一線路 層15及至少一第一電極墊16a，並且於該開孔中形 一電鍍導通孔15a。 如第1F圖所示，於該核芯板Π、線路層15及第一電 極墊16a上形成一高介電材料層16七。 如第1G圖所示，於該高介電材料層i6b表面形成第 二線路層17及相對應於該第一電極塾16&之第二電極墊 16c’使該第一電極墊16a、高介電材料層⑽及第二電極 塾16c構成一電容元件1 $。 如第1H圖所示’於該第二線路層17及第二電極墊16c 表面形成-線路增層結構18，該線路增層結構i8係包括 6 19707 200819004 有介電層181、疊置於該介電層上 於贫介+β^ - θ上之、、泉路層182,以及形成 、η黾層中之導電結構183，且該導帝蛀M + α _ 接至該第1靜17 ”“ 亥W結構183電性連 弟_、.泉路層17，又該線路增層結構Μ外表面且有 硬數-电性連接墊〗84，另 — 另於°亥、'泉路增層結構18外表面覆蓋 ，：g 且5亥防焊層19中具有複數開孔190以露出 该、、泉路增層結構18外表面之電性連接墊184。 X前述習知嵌埋有電容元件16之電路板結構，於 .電性連接時，必須藉由形成於該核芯板π :===:線路層15作㈣ ,^板11兩表面的電容元件16所經之路徑增長，因 =增加佈線的複雜度’且因訊號傳導路徑較長而增加阻 抗’故降低電性功能。 又_以供電容作串聯電性導接之電料通孔⑸必 、’、土孔材料14，在製程上來說必須增加製作步驟，因 而增加製程_難度及複雜度；且對於厚度較小之核芯板 不易進行基孔製程，導致薄化電路板結構的困難度增 並且於„玄包鍍導通孔丨5a中必須填入塞孔材料14，故 =開孔m之孔徑不宜過小，否則該塞孔材料14無法在電 二導通孔15a形成後被填人，使得該電料通孔⑸無法 縮小尺寸，而不利於高密度佈線之需求。 、是以，習知電鍍導通孔必須充填塞孔材料之製程，不 僅流程複雜、製造成本高’尤其為其製程設備投資更是昂 貴，且製程時間（Cycletime)冗長，因而不利於大量生產。 再者，於後續熱製程中，該第一及第二電極墊16&、 19707 7 200819004 16c與高介電材料層16b或高介電材料層16b與塞孔材料 14之間的熱膨脹係數（CTE)不同，因熱應力不同而容易產 生分層（Delamination)的情況，導致可靠度問題增加，且影 響電容值之精確度，嚴重影響製程之良率。 是故，如何有效解決上述習知技術之缺失，而獲取一 製程簡化、成本下降且良率提昇之電路板結構及其製造方 法，實已成為目前亟欲解決之課題。 【發明内容】In order to improve the wiring precision of the circuit board, the industry has developed a build-up technology, that is, a plurality of dielectric layers and circuit layers are alternately formed on the surface of a core board by using a line build-up technology, and the dielectric layer is formed on the surface of the core board. A plurality of conductive structures are formed, such as a conductive via and a plating through hole (PTH) for electrical connection between the upper and lower layers. In addition, with the development trend of light and thin various electronic products, the industry has developed active components such as semiconductor wafers, or passive components such as resistors, capacitors, inductors, etc. embedded in the circuit board, and then in the circuit. The circuit is fabricated on the board to form a circuit board structure in which the main and passive components are embedded. For the manner in which passive components are embedded in the board and the vias are made, please refer to Figures 1A to 1H. As shown in FIG. 1A, a core board 5 19707 200819004 such as a resin laminated copper foil is provided, the surface of the core board 11 having a thin metal layer 11a, and at least one formed in the core board 11 Through the opening 11 (). As shown in Fig. 1B, a conductive layer 12 is formed in the thin metal layer 11a and the opening 110 of the surface of the core board n, and the conductive layer 12 has an electrically conductive property for subsequent electroplating. As shown in FIG. 1C, a thin metal layer on the surface of the core plate, J a , and a surface of the conductive layer 12 in the opening 110 are plated to form a metal layer 13 to form a hollow portion in the opening 110. The conductive structure of i 12. As shown in FIG. 1D, the hollow portion 112 in the opening 11〇 is actually inserted into the base material 丨4 of the tree raft to fill the hollow portion ,2 to avoid the circuit board structure. The bubbles contained in the cavity cause a burst in the subsequent thermal cycle process. As shown in FIG. 1E, the metal layer 13, the conductive layer 12, and the thin metal layer 11a are then subjected to a patterning process to form a first wiring layer 15 and at least a first electrode pad 16a on the surface of the core board u, and A through-hole 15a is formed in the opening. As shown in Fig. 1F, a high dielectric material layer 16 is formed on the core plate, the wiring layer 15, and the first electrode pad 16a. As shown in FIG. 1G, a second wiring layer 17 and a second electrode pad 16c' corresponding to the first electrode 塾16& are formed on the surface of the high dielectric material layer i6b such that the first electrode pad 16a and the high dielectric layer are The electrically material layer (10) and the second electrode 塾 16c constitute a capacitive element 1 $. As shown in FIG. 1H, a line-generating structure 18 is formed on the surface of the second circuit layer 17 and the second electrode pad 16c. The line build-up structure i8 includes a dielectric layer 181 of 6 19707 200819004, and is stacked thereon. The dielectric layer is on the lower layer +β^ - θ, the spring layer 182, and the conductive structure 183 formed in the η黾 layer, and the conducting 蛀M + α _ is connected to the first static 17 ” "Hai W structure 183 electric slut _,. Spring road layer 17, and the line build-up structure Μ outer surface and has a hard-electric connection pad〗 84, another - another at ° Hai, 'spring road layer The outer surface of the structure 18 is covered, and the g-welding layer 19 has a plurality of openings 190 for exposing the electrical connection pads 184 of the outer surface of the spring-added structure 18. X. The above-mentioned circuit board structure in which the capacitor element 16 is embedded is electrically connected, and must be formed on the core board by the π:===: circuit layer 15 (four), the capacitance of both surfaces of the board 11 The path through which the component 16 passes increases, because the complexity of the wiring is increased 'and the impedance is increased due to the long signal conduction path', so that the electrical function is lowered. Moreover, the electric material through hole (5) must be used for the electrical connection of the capacitor for the series, and the soil material 14 must be added in the manufacturing process, thereby increasing the process _ difficulty and complexity; and for the small thickness The core plate is not easy to perform the base hole process, which leads to the difficulty of thinning the structure of the circuit board and must be filled with the plug material 14 in the through-hole 5a of the black plate, so the aperture of the opening m should not be too small, otherwise The plug material 14 cannot be filled after the formation of the electrical via 15a, so that the dielectric via (5) cannot be downsized, which is disadvantageous for the high-density wiring. Therefore, the conventional via hole must be filled with a plug hole. The process of materials not only has complicated process and high manufacturing cost, especially the investment in process equipment is more expensive, and the cycle time is long, which is not conducive to mass production. Furthermore, in the subsequent thermal process, the first and the first The two electrode pads 16 & 19707 7 200819004 16c differ from the high dielectric material layer 16b or the high dielectric material layer 16b and the plug material 14 in thermal expansion coefficient (CTE), and are susceptible to delamination due to different thermal stresses ( Delamination) leads to an increase in reliability problems and affects the accuracy of the capacitance value, which seriously affects the yield of the process. Therefore, how to effectively solve the above-mentioned lack of the prior art, and obtain a process simplification, cost reduction and yield The improved circuit board structure and its manufacturing method have become the subject of current problems.
有鑑於上述習知之缺失，本發明之目的係在提供一種 嵌埋被動元件之電路板結構，係以一導電柱直接電性連接 兩電容元件，俾得縮短路徑以提升電性品質。 本發明之主要目的係在提供一種嵌埋被動元件之電 路板結構，得藉由導電柱作為電性連接以減少佈線空間， 並可提南導線佈線密度。 本發明之另一目的係在提供一種嵌埋被動元件之電 路板結構，得避免電容元件之局介電材料層及第二電極塾 間或高介電材料與電鍍導通孔中之塞孔材料兩者間熱膨脹 係數之差異造成分層之問題。 本發明之又一目的係在提供一種嵌埋被動元件之電 路板結構，得以導電柱取代習知塞孔之電鍍導通.孔，俾得 縮小核芯板的厚度。 為達上述之目的及其它目的，本發明一種嵌埋被動元 件之電路板結構，係包括：核芯板，具有至少一貫穿之開 孔；導電柱，係電鍍形成於該核芯板之開孔中；高介電材 8 19707 200819004 料層，係形成於該核芯板及導電柱上； 該高介電材斜羼本& 电極墊，係形成於 置，俾料十曰i ’而該電極墊係位於對應該導電柱位 置俾使该電極墊、高介電材料厗β才位 1 %材糾料妹構成-電容元 依上述之結構，該核芯板係為陶瓷板 線路之電路板，·声今紅外 匕各傲Α具有 上，一Μ _又一弟一線路層係形成於該核芯板表 弟了，路層係形成於該高介電材料層表面，且該 層儀藉ώ道發a w Μ工h . 面上In view of the above-mentioned shortcomings, the object of the present invention is to provide a circuit board structure in which a passive component is embedded, which is directly electrically connected to two capacitor elements by a conductive pillar, thereby shortening the path to improve electrical quality. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a circuit board structure in which a passive component is embedded, by electrically connecting the conductive posts to reduce wiring space, and to increase the south wire wiring density. Another object of the present invention is to provide a circuit board structure embedding a passive component, which can avoid the dielectric material layer of the capacitor component and the second electrode inter- or high-dielectric material and the plug hole material in the plated via hole. The difference in thermal expansion coefficient between the two causes a problem of stratification. It is still another object of the present invention to provide a circuit board structure in which a passive component is embedded, by which a conductive post is substituted for a conventional via hole, and the thickness of the core plate is reduced. In order to achieve the above and other objects, a circuit board structure embedding a passive component includes: a core board having at least one through hole; and a conductive pillar formed by plating on the core board. Medium; high dielectric material 8 19707 200819004 The material layer is formed on the core board and the conductive column; the high dielectric material oblique && electrode pad is formed in the set, and the material is ten The electrode pad is located at a position corresponding to the conductive column, so that the electrode pad, the high dielectric material 厗β is 1%, and the capacitor element is formed according to the above structure, and the core plate is a circuit of the ceramic plate line. The board, the sound of the infrared 匕 匕 匕 Α Α _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ By the way, the aw is completed.
第二線路層係藉由導電A構以™ ’且έ 另本發明之電路板結構復 0 拎“祕料結構，該線路 構具有介電層、疊置於該介電層上之線路層，以及 形成於該介電層中之缉_ + έ士士接 導t 該料增層結構中具有 、包、。f %性連接至該第二線路層’又該線路增層 1 卜有複數電性連接塾，及於該線路增層結構夕^面 防焊層’且該防焊層中具有複數開孔以露出該線 曰層結構外表面之電性連接墊。 本發明之歲埋被動元件之電路板結構另一實施例係 括U ’具有至少—貫穿之開孔；導電柱，係電鑛 形成於該核芯板之開孔中；第一電極墊，係形成於該核芯 =表面上’且該第-電極㈣形成於該導電柱之端面；高 介電材料層，係形成於該核芯板及第一電極墊上；以及第 二電極墊，係形成於該高介電材料層表面以對應於該導電 柱端面之第一電極墊位置，俾使該第一電極墊、高介電材 料層及第二電極墊構成一電容元件。 又依上述之結構，該核芯板係為陶瓷板、絕緣板或具 19707 9 200819004 之板::包括-第-線路層係形成於該核芯板 該第二線路高介電材料層表 層，其中4 = 以電性連接至該第-線路 八甲„亥罘一線路層係電性連接該+ =一線路增層結構，係形成於該第二線路;包 :上’且遠線路增層結構係包括有介電層、疊；二：人2 層上之線路層，以及形成於該介電層中之導二構二： - 之線路層你、秦、a、苦 等包、、、口構’其中 ’、、過‘電結構以電性連接至兮笛_ 6 並於該線路增層結構外表面， $路增層結構外表面覆蓋有—防焊層， 中^該 數=以露出該線路增層結構外表面之電性連有锼 ^二匕命本發明之巍埋被動元件之電路板結構，係以導 电 电性連接位在核芯板兩相對表面之電容元件，而 可免除習知必須經由線路 ， 失，因而得縮短路徑以提升乂 !：阻抗及佈線之缺 為恭性魏，； f’·且直接以導電柱作 :: 可免除習知技術必須填入塞孔材料，以避 t㈣係數不同導致熱製程中造成分層之缺失；又以該 導电柱私1•生連接核芯板兩表面的電容元件，得免除習知夷 孔材料填孔，而可縮小隸，㈣減少佈線提土 =並且可減少核芯板的厚度，以達薄化電路板 【實施方式】 、以下係藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 19707 10 200819004 瞭解本發明之其他優點與功效。 [第一實施例] 睛茶閱第、 電路板結構第之係為本發明之嵌埋被動元件之 她之製法剖面示意圖。 線路=二I:、提:一㈣ --貫穿開孔21。板21，於該核芯板21中形成有至少 ^ 如第2B及2Γ闰仏- •電鑛形成有—實二、曾斤不’於該核芯板21之開孔210中 面形成一第一線 #於_心板21表 線路層2 3之夢法# \ =而该電錢形成導電柱2 2及第一 如 為成热之技術，於此不再為文贅述。 -線路層23 i开所Γ ’然後於該核芯板2卜導電柱22及第 — 形成一高介電材料層24。 如第2E圖所示，再於該高介狄一 線路層25及電極塾％，該 :曰^ (導乐^士 構⑸以Μ料㈡25係可透過導電結 形成於該高介電 /路層2 3，而該電極墊2 6係 俾使該電極塾26 j 1 對應至該導電柱22位置， 容元件2a。 ^電材料層24及導電柱22構成一電 第2F圖所示，於該第二線路岸25及+ μ轨^ 形成線路增岸妹爐Μ分治々、，峪層25及甩極墊26上 層27卜疊置: 增層結構27係包括有介電 電層中之導乂Λ 上之線路層272,以及形成於該介 屯曰Τ <導電結構273， /1 至該第二線路展7S， ， ^ ·电、、々構273係可電性連接 θ ’又該線路增層結構27外表面具有複 19707 11The second circuit layer is made of a conductive A structure, and the circuit board structure of the present invention is multiplexed with a "secure structure" having a dielectric layer and a wiring layer stacked on the dielectric layer. And 缉 + έ 形成 形成 形成 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该a connection layer, and an electrical connection pad having a plurality of openings in the solder resist layer to expose an outer surface of the wire layer structure. The buried passive component of the present invention Another embodiment of the circuit board structure includes a U' having at least a through opening; a conductive pillar formed by forming an electric ore in the opening of the core plate; and a first electrode pad formed on the core = surface And the first electrode (four) is formed on the end surface of the conductive pillar; the high dielectric material layer is formed on the core plate and the first electrode pad; and the second electrode pad is formed on the high dielectric material layer The surface is corresponding to the position of the first electrode pad of the end face of the conductive post, so that the first electrode pad and the high dielectric layer The electric material layer and the second electrode pad constitute a capacitor element. According to the above structure, the core board is a ceramic board, an insulating board or a board having 19707 9 200819004: a -first-line layer is formed on the core a second layer of the high dielectric material layer of the core layer, wherein 4 = electrically connected to the first line of the eighth layer of the first layer of the layer is electrically connected to the + = a line buildup structure, formed in the The second line; the package: the upper and far line build-up structure includes a dielectric layer, a stack; the second: a circuit layer on the human 2 layer; and a second structure formed in the dielectric layer: - the line Layers of you, Qin, a, bitter, etc., and the mouth structure 'where', and the 'electric structure is electrically connected to the flute _ 6 and on the outer surface of the added structure of the line, the outer surface of the add-on structure Covered with - solder mask, the number of the ^ = to expose the outer surface of the line build-up structure, electrically connected to the circuit board structure of the passive component of the present invention, electrically connected Capacitor elements located on opposite surfaces of the core board, which can be dispensed with the need to pass the line, and thus lose Short path to improve 乂!: The lack of impedance and wiring is Gong Wei,; f'· and directly with conductive column:: It can be exempted from the conventional technology must be filled with plug material to avoid the difference in t (four) coefficient caused by thermal process The lack of delamination; and the conductive element of the conductive column is connected to the two surfaces of the core plate, so that the hole can be removed from the conventional hole material, and the wire can be reduced, and the wiring can be reduced and the core can be reduced. The thickness of the core board is to achieve a thinned circuit board. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily understand the contents disclosed in the present specification by 19707 10 200819004. Other advantages and benefits of the present invention. [First Embodiment] The eye tea reading and the circuit board structure are the schematic cross-sections of the method for forming the embedded passive component of the present invention. Line = two I:, mention: one (four) - through the opening 21. The plate 21 is formed in the core plate 21 with at least ^ 2B and 2 Γ闰仏 - • an electric ore formed - a solid two, a squash not formed in the opening 210 of the core plate 21 The first line #于_心板21表线层2 3的梦法# \ = and the electric money forms the conductive column 2 2 and the first as a technology of heat generation, which is not described here. The circuit layer 23i is opened and then a high dielectric material layer 24 is formed on the core plate 2 and the conductive pillars 22 and the first. As shown in FIG. 2E, in addition to the high-tech layer 25 and the electrode 塾%, the 曰^ (the 乐^^ (5) is formed by the ( (2) 25 series permeable conductive junction formed on the high dielectric/road Layer 2 3, and the electrode pad 26 is configured such that the electrode 塾 26 j 1 corresponds to the position of the conductive post 22, the capacitive element 2a. The electrical material layer 24 and the conductive post 22 form an electric 2F diagram, The second line bank 25 and the + μ track form a line, and the upper layer 25 and the upper layer of the drain pad 26 are stacked. The build-up structure 27 includes a guide in the dielectric layer. a circuit layer 272 on the ,, and formed on the dielectric <conductive structure 273, /1 to the second line extension 7S, ^ · electric, 々 273 series can be electrically connected θ 'and The outer surface of the line build-up structure 27 has a complex 19707 11
I 200819004 數電性連接墊274’另於該線路增層結構27外表面覆蓋一 防焊層28,且該防焊層28中具有複數開孔28〇以露出該 線路增層結構27外表面之電性連接墊274。 依上述之製法，本發明亦揭示一種嵌埋被動元件之電 路板結構，係包括：核芯板21，具有至少―貫穿之開孔 21〇’導電柱22’係電鍍形成於該核芯板21之開孔21〇中; 線路層23,係形成於該核芯板21表面上；高介電材 ;:;層24’係形成於該核芯板21、導電柱^及第一線路層 I3方’以及第二線路層25及電極墊26,係形成於該高介 电材料層24表面，該第二線路層^可透過導電結構⑸ 電性連接至該第-線_23，該電極墊 南介電材料層24表面對應於該導電柱22之位置 :a極塾26、局介電材料層“及導電柱22構成—電容元件 本結構於導電柱端面並未形成有延伸出之 本貫施例係可減少佈線空間並提高佈線密度。 又依上述之電路板結構，復包括有線路增層 亥第二線路層25及電極墊26上，該線路增岸 構⑺係可電性連^至\層第之Γ結構273，且該導電結 甩注連接至该昂二線路層25，又誃 構27外表面具有複數電性連接塾274,另於^敗冒層結 構W外表面覆蓋有-防焊層28，且該防谭結 數開孔280以露出該線路增層結構27外表=有複 〜兔性連接墊 19707 12 200819004 274。 [弟二實施例] 凊參閱第3A至3P Rj々 ^好圖，係為本發明之嵌埋被動元件之 $路板結構弟二實施之製法剖面示意圖 同處在於該導電柱鱼箧.,^ a 一 戶、轭例不 狂，、昂一線路層相連接。 如弟3 A圖所示，接獻^一 49- ^ a -瓷板、料m 士“一核心才反31 ’該核芯板係為陶 瓦板％緣板或具有線路之電路板 壓合銅箔之核芯板31作1明相、， 况月係以树月曰 • 31之#而且古疒人.乍月’仁亚不以此為限，·該核芯板 々八有溥至屬層31 a，且於琴按# ^ 少-貫穿開孔31〇。 、氣板”中形成有至 如第3B圖所示，於I 200819004, the electrical connection pad 274' is further covered with a solder resist layer 28 on the outer surface of the line build-up structure 27, and the solder resist layer 28 has a plurality of openings 28 to expose the outer surface of the line build-up structure 27. Electrical connection pad 274. According to the above method, the present invention also discloses a circuit board structure embedding a passive component, comprising: a core board 21 having at least a through hole 21 〇 'a conductive post 22 ′ is electroplated on the core board 21 . The circuit layer 23 is formed on the surface of the core board 21; the high dielectric material; the layer 24' is formed on the core board 21, the conductive pillars, and the first circuit layer I3. The square and the second circuit layer 25 and the electrode pad 26 are formed on the surface of the high dielectric material layer 24, and the second circuit layer is electrically connected to the first line _23 through the conductive structure (5). The surface of the south dielectric material layer 24 corresponds to the position of the conductive pillar 22: a pole 26, a layer of dielectric material "and a conductive pillar 22" - the capacitor element is not formed on the end surface of the conductive pillar. The embodiment can reduce the wiring space and increase the wiring density. According to the above-mentioned circuit board structure, the second circuit layer 25 and the electrode pad 26 of the line-increasing layer are further included, and the line-increasing structure (7) can be electrically connected. To the layer 第 structure 273, and the conductive junction is connected to the erection layer 25, and the structure 27 The outer surface has a plurality of electrical connections 塾 274, and the outer surface of the smashed layer structure W is covered with a solder resist layer 28, and the anti-tamper layer openings 280 are exposed to expose the line build-up structure 27 appearance = there is a complex ~ Rabbit connection pad 19707 12 200819004 274. [Different embodiment] 凊 Refer to the 3A to 3P Rj々^ good diagram, which is the schematic diagram of the method of the implementation of the embedded circuit component of the present invention. It lies in the conductive column fish 箧., ^ a household, yoke is not mad, and the Ang line layer is connected. As shown in Figure 3 A, the offer is a 49- ^ a - porcelain plate, material m A core is only anti-31'. The core board is a lining plate% edge plate or a core board 31 with a circuit board pressed copper foil for a clear phase, and the month is a tree month 曰• 31# Moreover, the ancient monk. Haoyue 'Renya is not limited to this, · The core board has eight layers to the genus layer 31 a, and Yuqin press # ^ less - through the opening 31 〇. , the gas plate is formed as shown in Figure 3B,
及㈣；1Λ 士， 、°亥核心板31表面之薄金屬層3U 汗1孔310中形成有一導電層32，藉由該 導電之特性以供後續之電鍍製程。^ 、、有 如弟3 C圖所示，於琴仿γ 士 Ή〇 . ^ 、〜杉心板31表面之薄金屬層3la 及開孔3H)中的導電層32表面電鑛形成 於該開孔310中形成—實心之導電柱34。 以 如第3D圖所示’然後該金屬層33、導電層3 屬層31 a進行圖幸介制4口丨、，产上务&上 寻隻 路厚…『一 芯板11表面形成第-線 r θ 乂一乐—電極墊36a;其中該第一電極墊36a 係形成於該導電柱34之端面。 如第3E圖所示，然後於該核芯板21、 介電材料層灿表面形成第二線路層37及第二電極塾门 36c，且該第二線路層37係可透過導電結構奶電性連接 19707 13 200819004 至該第一線路層35，俾 恭 層36b及第二帝搞孰Q以 电極墊3以、高介電材料 -線路層35及1 t 成一電容元件36。其中，該第 表示）。^ 一電極塾36係可相互電性連細式中未 如第3F圖所示，於該第二線路層3 上形成線路增層姓椹μ _ ,, 包極塾36c =%μ 381 θ 、'° ，该、，泉路增層結構％係包括有介 包曰381、畳置於該介電 介電層中之導電，構二曰之線路層382’以及形成於該 籲結構383帝性、隶垃s 以供線路層382透過該導電 38外表面覆蓋：防=妾=4’另於該線路增層結構 防J：干層39，且該防焊層39中且 孔390以露出該線路 有&數開 384。 屑、、、口構38外表面之電性連接墊 I之衣法，本發明係提供一種嵌埋被動元件之帝 板、:構’係包括：核芯板31，具有至少一貫穿之開孔 =0’導電柱34,係電鑛形成於該核芯板31之開孔31〇中； 弟一線路層35及第-電極墊36a，係形成於該核芯板幻 表面上，且該第一電極墊36a係形成於該導電柱Μ之端 面；高介電材料層36b，係形成於該核芯板31、第一線路 層35及第一電極墊36a上；以及第二線路層”及第二電 極墊36c ’係形成於該高介電材料層36b表面，該第二綠 路層37係藉由導電結構371以電性連接至該第一線路層 35’而該第二電極墊36c係對應該導電柱34端面之第—電 極塾36a位置，且形成於該高介電材料層36b表面，俾^ 14 19707 200819004 . 該第一電極墊36a、高介電材料芦 構成電容元件36。包材抖層灿及弟二電極墊36c 此外，該第-電極塾36a係可電性連接 35,使該核芯板31其中_表 +- 乐、求峪層 . 表面之電谷兀件36得單獨使用， 或者可直接藉由該導電柱34串聯另一夺面 以合併使用。 表面之電容元件36 -因此^發明之嵌埋被動元件之電路板結構，係在該 柱之兩W卿成電容元件’而可藉由該導電柱直接 t性連接位在該核芯板兩相對表面之電容元#，㈣㈣ ==及免除佈線，因而得以提升電性品f;且直接以實心 ^電柱作電性連接，而得免㈣知技術填人塞孔材料造 係數不同導致熱製程中造成脫層之缺失；又以該 ^ ^性連接核芯板兩表面的電容元件，得免除習知塞 L =料填孔，而可縮小孔徑’以達減少佈線空間提高佈線 ^ ’並且可減少核芯板的厚度，以達薄化電路板結構之 ㈢的。 上述實施例僅為例示性說明本發明之原理及苴功 效，而非用於限制本發明。任何熟習此項技藝之^士均可 ^違背本發明之精神及範訂，對上述實施例進行㈣ ^交化。因此，本發明之權利保護範圍，應如後述之 專利範圍所列。 【圖式簡單說明】 …第1A至1H圖係習知電容元件形成於核芯板表面並以 兔鍍導通孔電性連接之製程剖視圖； 19707 15 200819004 , 第2A至2F圖係為本發明之嵌埋被動元件之電路板結 構之第一實施例之製法剖面示意圖；以及 第3A至3F圖係為本發明之嵌埋被動元件之電路板結 構之第二實施例之製法剖面示意圖。 【主要元件符號說明】 11、21、31 核芯板 110、210、310 核芯板開孔 . 190、280、390 防焊層開孔 _ 112 空心部 11a、31a 薄金屬層 12、32 導電層 13 > 33 金屬層 14 基孔材料 15、182、272、382 線路層 15 > 23 〜35 第一線路層 15a 電鐘導通孔 16、2a、36 電容元件 16a、36a 第一電極墊 16b、24、36b 南介電材料層 16c、36c、17 第二電極墊 18、27、38 線路增層結構 181、271、381 介電層 183、251、273 、371、383 導電結構 184、274、384 電性連接墊 16 19707 200819004 . 19、28、39 防焊層 22、32、34 導電柱 25、37 第二線路層 26 電極塾 17 19707And (4); 1 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ^, , as shown in the figure 3 C, the surface of the conductive layer 32 in the thin metal layer 3la and the opening 3H of the surface of the sapphire board 31 is formed in the opening. A solid conductive pillar 34 is formed in 310. As shown in Fig. 3D, 'the metal layer 33, the conductive layer 3 is a layer 31a, and the four layers of the layer are formed, and the surface is formed on the surface of the upper layer. The line r θ 乂 乐-electrode pad 36a; wherein the first electrode pad 36a is formed on an end surface of the conductive post 34. As shown in FIG. 3E, a second wiring layer 37 and a second electrode shutter 36c are formed on the surface of the core board 21 and the dielectric material layer, and the second circuit layer 37 is permeable to the conductive structure. Connecting 19707 13 200819004 to the first circuit layer 35, the smear layer 36b and the second dynasty smashed the electrode pad 3 into a capacitor element 36 with the high dielectric material-circuit layers 35 and 1 t. Where the first is indicated). ^ One electrode 塾 36 series can be electrically connected to each other. As shown in FIG. 3F, a line build-up layer 椹μ _ is formed on the second circuit layer 3, and a package 塾 36c =% μ 381 θ , '° , the , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And the wiring layer 382 is covered by the outer surface of the conductive layer 38: anti-妾=4' and the additional layer structure anti-J: dry layer 39, and the solder resist layer 39 and the hole 390 to expose the The line has & number 384. The invention relates to a method for electrically connecting the outer surface of the mouth structure 38, and the invention provides a method for embedding a passive component, the structure comprising: a core plate 31 having at least one through hole =0' conductive pillar 34, the electric ore is formed in the opening 31 of the core board 31; the first circuit layer 35 and the first electrode pad 36a are formed on the magic surface of the core board, and the first An electrode pad 36a is formed on an end surface of the conductive post; a high dielectric material layer 36b is formed on the core board 31, the first circuit layer 35 and the first electrode pad 36a; and a second circuit layer" The second electrode pad 36c' is formed on the surface of the high dielectric material layer 36b, and the second green channel layer 37 is electrically connected to the first circuit layer 35' by the conductive structure 371 and the second electrode pad 36c The position of the first electrode 36a corresponding to the end face of the conductive post 34 is formed on the surface of the high dielectric material layer 36b, 俾^14 19707 200819004. The first electrode pad 36a and the high dielectric material reed constitute the capacitor element 36. The cladding electrode layer and the second electrode pad 36c are further electrically connected to the core electrode 36 to make the core board 31 Medium_table+-le, seek layer. The surface of the electric grid element 36 can be used alone, or can be directly combined by the conductive column 34 in series with another surface. The capacitive element of the surface 36 - thus ^ invention The circuit board structure embedded with the passive component is connected to the two capacitors of the column and can be directly t-connected to the capacitor element on the opposite surfaces of the core plate by the conductive column, (4) (4) == and Eliminating the wiring, thus improving the electrical product f; and directly connecting the solid ^ electric column for electrical connection, and obtaining (4) the technology to fill the plug material material coefficient is different, resulting in the lack of delamination in the thermal process; ^Sensitively connecting the capacitive elements on both surfaces of the core board, it is possible to eliminate the conventional plug L = material filling hole, and can reduce the aperture 'to reduce the wiring space to improve the wiring ^ ' and reduce the thickness of the core board to achieve thinning The above-mentioned embodiments are merely illustrative of the principles and advantages of the present invention, and are not intended to limit the present invention. Anyone skilled in the art can violate the spirit and scope of the present invention. , (4) ^ Intersection of the above embodiment. Therefore, the scope of protection of the present invention should be as listed in the following patent range. [Simple Description of the Drawings] ... 1A to 1H are conventional capacitive elements formed on the surface of a core board and electrically connected by a rabbit plated through hole. Process cross-sectional view; 19707 15 200819004, 2A to 2F are schematic cross-sectional views of a first embodiment of a circuit board structure embedding a passive component of the present invention; and 3A to 3F are embedded passives of the present invention Schematic diagram of the manufacturing method of the second embodiment of the circuit board structure of the component. [Description of main component symbols] 11, 21, 31 core board 110, 210, 310 core board opening. 190, 280, 390 solder mask opening _ 112 Hollow portion 11a, 31a Thin metal layer 12, 32 Conductive layer 13 > 33 Metal layer 14 Base material 15, 182, 272, 382 Circuit layer 15 > 23 to 35 First circuit layer 15a Electric clock via 16 2a, 36 capacitive elements 16a, 36a first electrode pads 16b, 24, 36b south dielectric material layers 16c, 36c, 17 second electrode pads 18, 27, 38 line build-up structures 181, 271, 381 dielectric layer 183 , 251, 273, 371, 383 conductive junction 184,274,384 conductive pads 1,619,707,200,819,004. The second wiring layer 25, 37 19,28,39 22,32,34 solder resist layer 26 conductive pillars electrode Sook 1,719,707