1305120 i . 九、發明說明： 【發明所屬之技術領域】 有關於一種嵌埋被動元件之電路板結構，尤 才曰-種將被動元件喪埋於電路板中之結構。 【先前技術】 二 =產業的蓬勃發展，電子產品亦逐漸邁 月匕、间性1的方向研發。為収半導體封料高積率度 丨nation)以及微型化的封裝需求，提 '主、 動元件及線路載接之雷踗拓 .^ ± 被 板，俾於有：:;:二::::層板演變成多層 求。 口應以子松度之積體電路之使用需 電：板之佈線精密度，業界發展出-種增層技 up) ’亦即在一核心板表面利用線路 =數二及線路層’並於該介電層心有複數導 此外，又隨著各式電子產=^^間；^性連接。 業界遂發展出將如半導體晶片等主動二匕=展趨勢， 電容、電感等被動元件後埋於電路：：件，或係如電阻、 形输主、被動元件之電路板結構。 方式嵌埋被動元件及製作鶴通孔的 、 明苓閱弟1Α至1 η圖。 如第1Α圖所示，提供-係如樹脂壓合銅箱之核芯板 19707 5 1305120 核芯板u之表面具有薄金屬層lla，且於該核芯板 11中形成有至少一貫穿開孔丨1〇。 如第1B圖所示，於該核芯板丨丨表面之薄金屬層… ^開孔UG中形成有—導電層12，藉由該導電層^具有 導電之特性以供後續之電鍍製程。 士第1C圖所不，於該核芯板J J表面之薄金屬層11 & 及開孔110中的導電層12表面電鍍形成—金屬層13，以1305120 i. Description of the Invention: [Technical Field of the Invention] Regarding a circuit board structure in which a passive component is embedded, a structure in which a passive component is buried in a circuit board is particularly exemplified. [Prior Art] II = The booming industry, electronic products are gradually developing in the direction of the Moonlight and Interstitial 1. In order to meet the high-capacity rate of semiconductor sealing materials and the miniaturized packaging requirements, the Thunder extension of the main and moving components and the line is connected. ^ ± is the board, and there are::;::2::: : Layers evolve into multiple layers. The port should be used for the use of the sub-slung integrated circuit: the wiring precision of the board, the industry has developed a kind of layering technology up) 'that is, using the line = number two and the circuit layer on the surface of a core board The dielectric layer has a plurality of conductors, and is connected with various types of electronic products. The industry has developed active semiconductors such as semiconductor wafers, and passive components such as capacitors and inductors are buried in the circuit::, or circuit boards such as resistors, inductors, and passive components. The method is to embed the passive component and make the Hetong hole, the Ming dynasty 1Α to 1 η diagram. As shown in FIG. 1 , a core plate 19707 5 1305120 of a resin-bonded copper box is provided, and a surface of the core board u has a thin metal layer 11a, and at least one through hole is formed in the core board 11.丨1〇. As shown in Fig. 1B, a thin metal layer is formed on the surface of the core plate. The conductive layer 12 is formed in the opening UG, and the conductive layer has an electrically conductive property for subsequent electroplating. No. 1C, the surface of the thin metal layer 11 & and the conductive layer 12 in the opening 110 of the core board J J is plated to form a metal layer 13 to
於戎開孔110中形成一空心部i 12的導電結構。 如第1D圖所示，接著於該開孔110中的空心部J12 填入係如㈣之塞孔材料14，謂該“部m填滿 免在包路板結構中因空洞所包含的氣泡導致後續熱猶 程中產生爆板的情況。 衣 如第1E圖所示，然後該金屬層13、導電層12及薄全 :層m進行圖案化製程以在核芯板u表面形成第一線路 層15及至少一第一電極墊16a，並且於該開孔Η。A conductive structure of a hollow portion i 12 is formed in the opening 110. As shown in FIG. 1D, the hollow portion J12 in the opening 110 is then filled with a plug material 14 such as (4), which means that the "part m is filled with air bubbles contained in the wrapping plate structure due to voids. In the subsequent hot stage, a burst is generated. As shown in FIG. 1E, the metal layer 13, the conductive layer 12, and the thin layer: layer m are patterned to form a first circuit layer on the surface of the core board u. 15 and at least one first electrode pad 16a, and in the opening.
一電鍍導通孔15a。 X 如第1F圖所示’於該核芯板U、線路層15及第— 極墊16a上形成一高介電材料層工讣。 兔 —如第1G圖所不，於該高介電材料層⑽表面形 二線路層17及相對應於該第一電極墊—之第二電極墊 16c，使該第一電極勢]6 ^ 翌i6a同介電材料層16b及第二電極 墊16c構成一電容元件16。 如弟1Η圖所示，於贫笛_说 万、4弟一線路層17及第二電極墊16c 表面形成一線路增層妹爐〗s # a嘈、、口構18，该線路增層結構18係包括 19707 6 1305120A plating via 15a is formed. X, as shown in Fig. 1F, forms a high dielectric material layer on the core plate U, the wiring layer 15, and the first pad 16a. Rabbit - as shown in FIG. 1G, a two-layer layer 17 is formed on the surface of the high dielectric material layer (10) and a second electrode pad 16c corresponding to the first electrode pad, so that the first electrode potential is 6 ^ 翌The i6a dielectric material layer 16b and the second electrode pad 16c constitute a capacitor element 16. As shown in the figure 1 of the brother, on the surface of the poor whistle _ yan, 4 brothers, a circuit layer 17 and the second electrode pad 16c, a line-increasing layer furnace is formed, and the structure of the line is increased. 18 series including 19707 6 1305120
^ I 有）丨電層181、疊置於該介電岸 於該介+厗Φ +θ上之、、泉路層182,以及形成 接二;構I且該導電結㈣電性連 複數電性二=另又二路增層結構18外表面具有 -防焊層，且該防焊二 該岣致描昆/、有複數開孔190以露出 -㈢層，、，口構18外表面之電性連接墊184。 惟，前述習知嵌埋有電容元件16 *進行如串聯之雷祕、Φ拉π* 4路扳、、、口構’於 •中之带 τ ’必須藉由形成於該核芯板11 咖通孔15a及第一線路層15作電性導接，如此將 而：力亥：板U兩表面的電容元件16所經之路徑增長，因 日：：線的複雜度，且因訊號傳導路徑 抗，故降低電性功能。 日刀丨且 ::用以供電容作串聯電性導接之電鑛導通孔…必 二入，材料14,在製程上來說必須增加製作步驟，因 11 ;Γ進“rt度及複雜度；且對於厚度較小之核芯板 1不易進订塞孔製程’導致薄化電路板結構的困難度增 加，亚且於該電鍍導通孔15a中 、 哕間$ 11Λ Τ 乂肩填入塞孔材料14,故 之孔徑不宜過小，否則該塞孔材料14無法在恭 鍍導通孔15a形成後被填入’使得該電鍍導通孔…無： 縮小尺寸，而不利於高密度佈線之需求。 …/ 是以，習知電鍍導通孔必須充填塞孔材料之製程，不 =流程複雜、製造成本高，尤其為其製程設備投資^是昂 貝，且製程時間（Cycle time)冗長，因而不利於大量生產。 再者，於後續熱製程中，該第一及第二電極=16&、 19707 7 1305120 16c與高介電材料層16b或高介電材料層16b與塞孔材料 14之間的熱膨脹係數（CTE)不同’因熱應力不同而容易產 生分層（Delamination)的情況，導致可靠度問題增加，且影 響電容值之精確度，嚴重影響製程之良率。 是故，如何有效解決上述習知技術之缺失，而獲取一 製程，化、成本下降且良率提昇之電路板結構及其製造方 法，實已成為目前亟欲解決之課題。 【發明内容】 有鑑於上述習知之缺失，本發明之目的係在提供 嵌埋被動元件之電路板結構，係以—導電柱 兩電容元件，俾得縮短路徑以㈣電性品質。 接 本ic明之主要目的係在提供—種嵌埋被動元件 ^反結構’得藉由導電柱作為電性連接以減 並可提高導線佈線密度。 間 路板2明^另—目的係在提供—種嵌埋被動元件之電 門=避免電容元件之高介電材料層及第二電極墊 係數之差異造成孔材料兩者間熱膨服 路板、:：明二:目的係在提供一種嵌埋被動元件之電 縮小核芯㈣厚度。自塞孔之電料通孔，俾得 為達上述之目的及其它目的， 件之電路板結構,係包括:核芯板月種== 孔；導電柱，係命如…、 令主V貝牙之開 ’、甩4形成於該核芯板之開孔中；高介電材 19707 8 * 4 1305120 =介=Γ芯板及導電柱上;電極墊，係形成於 置：=’而該電極墊係位於對應該導電柱位 二。俾使㈣極墊、高介電材料層及導電柱構成_電容元 線路：ίίΓ結構’該核芯板係為陶瓷板、絕緣板或具有 面上，一 、、泉路層係形成於該核芯板表 第-後二層係形成於該高介電材料層表面，且該 丨藉由導電結構以電性連接至該第-線妳 增^構且:ί板結構復可包括有線路增層結構，該線路 妒：二二，電層、疊置於該介電層上之線路層，以及 中之導電結構，且該線路增層結構中具有 外表面且右生t接至该第二線路層’又該線路增層結構 Μ右二⑨丈電性連接塾，及於該線路增層結構外表面 且該防焊層中具有複數開孔以露出該線 曰、、'°構外表面之電性連接墊。 ，包括==嵌埋被動元件之電路板結構另—實施例係 m二Γ反’具有至少—貫穿之開孔；導電柱，係電鑛 板板之開孔中·’第一電極塾’係形成於該核芯 入亥第一電極塾係形成於料電柱之端面；高 ==層：係形成於該核芯板及第-電極些上；以及第 妓 係形成於該高介電材料層表面以對應於該導電 弟—電極墊位置，俾使該第-電極塾、高介電材 枓層：弟二電極塾構成—電容元件。 述之結構，該核芯板係為陶瓷板、絕緣板或具 9 19707^ I has a tantalum layer 181, stacked on the dielectric bank on the dielectric + 厗 Φ + θ, the spring layer 182, and the formation of the second; the structure I and the conductive junction (four) electrical connection complex electricity Sex 2 = the other two-way build-up structure 18 has a solder mask on the outer surface, and the solder resist 2 has a plurality of openings 190 to expose the - (three) layer, and the outer surface of the mouth structure 18 Electrical connection pads 184. However, the above-mentioned conventional embedded capacitive element 16* performs such as the series connection of the jerk, the Φ pull π*4 way, and the mouth structure 'the middle τ' must be formed on the core board 11 The through hole 15a and the first circuit layer 15 are electrically connected, so that the path of the capacitive element 16 on both surfaces of the board U increases, due to the complexity of the line: and the signal conduction path Resistance, so reduce electrical functions. The Japanese knives are:: The electro-conducting vias for the capacitors to be electrically connected in series... must be inserted, material 14, in the process must increase the production steps, because 11; into the "rt degree and complexity; Moreover, for the core board 1 having a small thickness, it is difficult to customize the plug hole process, which results in an increase in the difficulty of thinning the circuit board structure, and the plug hole material is filled in the plated through hole 15a and the space is $11Λ 乂14. Therefore, the aperture should not be too small. Otherwise, the plug material 14 cannot be filled after the formation of the via hole 15a. This makes the plating via... no: downsizing, which is not conducive to high-density wiring. .../ Yes Therefore, it is known that the plating via hole must be filled with the plug material material, which is not complicated in process and high in manufacturing cost, especially for the investment of the process equipment, and the process time is long, which is not conducive to mass production. Furthermore, in the subsequent thermal process, the thermal expansion coefficients (CTE) between the first and second electrodes=16&, 19707 7 1305120 16c and the high dielectric material layer 16b or the high dielectric material layer 16b and the plug material 14 ) different 'easy due to different thermal stresses In the case of delamination, the reliability problem increases, and the accuracy of the capacitance value is affected, which seriously affects the yield of the process. Therefore, how to effectively solve the above-mentioned lack of the prior art, and obtain a process, The circuit board structure with reduced cost and improved yield and its manufacturing method have become the subject of current problems. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings, the object of the present invention is to provide a circuit board with embedded passive components. The structure is made up of two conductive elements of the conductive column, and the path is shortened to (4) electrical quality. The main purpose of the present invention is to provide an embedded passive element ^ anti-structure 'to be electrically connected by a conductive column Decrease and increase the wire wiring density. The circuit board 2 is clearly provided that the gate is provided with a buried passive component = the difference between the high dielectric material layer and the second electrode pad coefficient of the capacitor element is caused to cause two holes material Thermal expansion of the road board, :: Ming 2: The purpose is to provide a buried passive component of the electrical reduction core (four) thickness. Self-plugging electrical material through hole, won the up For the purpose and other purposes, the circuit board structure of the piece includes: core board monthly == hole; conductive column, the life is like ..., the main V bei's opening ', 甩 4 is formed on the core board In the opening; high dielectric material 19707 8 * 4 1305120 = dielectric = core plate and conductive column; electrode pad, formed in the set: = ' and the electrode pad is located in the corresponding conductive column 2. (4) Pole pad, high dielectric material layer and conductive column structure_Capacitor element line: ίίΓ structure 'The core board is a ceramic board, an insulating board or a surface, and a spring road layer is formed on the core board The first-second layer is formed on the surface of the high-dielectric material layer, and the germanium is electrically connected to the first-side germanium by a conductive structure and: the plate structure includes a line build-up structure The circuit 妒: 22, an electrical layer, a circuit layer stacked on the dielectric layer, and a conductive structure in the middle, and the line build-up structure has an outer surface and the right-handed t is connected to the second circuit layer 'The additional layer structure of the line is the right second 9 ft electrical connection 塾, and the outer surface of the added layer structure of the line and has a complex in the solder resist layer Said openings to expose the line ,, 'is electrically connected to the outer surface of the pad configuration °. , including == embedded circuit board structure of the passive component - the other embodiment is m Γ Γ 具有 具有 具有 具有 具有 具有 具有 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The first electrode formed on the core is formed on the end surface of the electric column; the high== layer is formed on the core plate and the first electrode; and the third system is formed on the high dielectric material layer The surface corresponds to the position of the conductive electrode pad, so that the first electrode 塾, the high dielectric material layer: the second electrode 塾 constitutes a capacitor element. In the structure, the core board is a ceramic board, an insulating board or a piece of 9 19707
I 1305120 * 有線路之電路板；復包括一第一線 表面上，一笛成於該核芯板 該第二線路:：=係形成於該高介電材料層表面，且 層，1中：，错由導電結構以電性連接至該第-線路 乂该弟-線路層係電性連接該第一電極塾； 、-、路增層結構，係形成於該第二線 匕 層上，Η兮A A &岭智及回介電材料 錢路增層結構係包括有介電層、4£於 層上之線路層，以及形成於該介電層中之導電，士構= 之線路層係可透過導電結構以電性連接至：：：=;中 > #你e a、 <牧王成弟一線路層， ' ^Λ路增層結構外表面具有複數電性連 線路增；么士 士塞从± 堂及於5亥 數開/Hr面覆蓋有一防焊層，該防焊層中具有複 乂路出该線路增層結構外表面之電性連接墊。 本發明之嵌埋被動元件之電路板結構，係以導 二 2電性連接位在核芯板兩相對表面之電容元件，而 L免除白知必須經由線路層傳導而增加阻抗及佈線之缺 ’因而得縮短路徑以提升電性品質；且直接以導電柱作 t電性連接，而可免除習知技術必須填入塞孔材料，以避 、富f膨脹係數不同導致熱製程中造成分層之缺失；又以該 V兒柱電性連接核芯板兩表面的電容元件，得免除習知塞 =材料填孔，而可縮小孔徑，以達減少佈線空間提高佈ς ' ^並且可減少核芯板的厚度，以達薄化電路板結構之 目的。 【實施方式】 、以下係藉由特定的具體實施例說明本發明之實施方 式，热悉此技蟄之人士可由本說明書所揭示之内容輕易地 10 19707 1305120 瞭解本發明之其他優點與功效。 [第一實施例] 之 請參閱第2A至2F岡总劣丄々 電路板:構第一實施之製::;:f件 如弟2A圖所示’挺也 線路之電路板的核芯板2 :、，於:亥二:反2 ;:緣板ί具有 -貫穿開孔210。 …亥核心板21中形成有至少 如第2B及2C圖所千 電鍍形成有一實 ：，。亥核芯板21之開孔210中 面形成-第-線㈣^ 。接著，於該核芯板21表 妗,々β λ e 23 ’而該電鍍形成導電枉22 >5筮 線路層23之製法 二“主22及弟一 如第2D圖所_ 技術，於此不再為文贅述。 __ θ不，然後於該核芯板21、導命妇菸馇 —線路層23上形成—高介電材料層24。 及第 如弟2Ε圖戶斤千，$ 線路層25及電極墊％該高介電材料層表面形成第二 構25】以電性連接至^以二線路層25係可透過導電結 形成於該高介線路層23，而該電極墊％係 俾使該電對應至該導電柱22位置， 容元件2a。 一材料層24及導電柱22構成一電 如第2F圖所示’於該第 形成線路增層結構2 曰25及电極墊26上 層27卜疊置於該路增層結構27係包括有介電 電層中之導電冓之線路層272，以及形成於該介 至該第二線路;該導電結構⑺係可電性連接 曰 線路增層結構27外表面具有複 Π 19707 1305120 ^性連接墊274，另於該線路増層結構27外表面覆蓋一 2層28 ’且該防焊層28中具有複數開孔2_出該 線路增層料27外表面之電性連接墊27[ 依上述之製法’本發明亦揭示—種欲埋被動元件之電 21〇反U系包括.核芯板21 ’具有至少-貫穿之開孔 mV主22 ’係電鑛形成於該核芯板21之開孔210中； 料：線路層23 ’係形成於該核思板21表面上；高介電材 ㈢2 4 ’係形成於該核芯板21、導電柱2 2及第一線路層 ”二^二線路層25及電極塾26，係形成於該高介 二:、4表面：§亥第二線路層25可透過導電結構251 古：=:^“一線路層23’該電極墊26係形成於該 應於該導電柱22之位置，俾使該 =亟塾26、局介電材料層24及導電柱22構成—電容元件 本結構於導電柱端面並未形成有延伸出之電極塾，故 本實施例係可減少佈線空間並提高佈線密度。 又依上述之电路板結構，復包括有線路增層 其係形成於該第二線路層25及電極墊26上，該= 結構27係包括有介電層27卜疊置於該介兩屉^ 7曰曰 272，以及形成於該介電層中::構J θ之線路層 « ΐ〜守电、?口構2 7 3，且該墓雷妊 構273係可電性連接至該第_ . V ^ '''° ㈣外表面具有複數電二^4=:路增層結 構27外表面復盍有一防焊層28，且該防谭層u中 數開孔280以露出該線路增層結構27外表面之電性連接^ 19707 12 1305120 «( 274。 [弟一貫施例] 請參閱第3八至3 乂 電路板結構第二實纟θ系為本發明之嵌埋被動元件之 同處在於該導電柱血μ、 °不思圖，與前一實施例不 如第3Α圖所二 線路層相連接。 圖所不，提/j£ 一妨〇 瓷板、絕緣板或I古& ’、 X心板3 1，該核芯板係為陶 ’線路之電路柘，，、，τ 壓合銅箱之核芯板31 乂下之說明係以樹脂 31之表面具有薄金 ° —亚不以此為限；該核芯板 少一貫穿開孔31G層3U，且於該核芯板Μ中形成有至 如第3Β圖所干 ^ 及開孔3iG中形成有L 芯板1表面之薄金屬層&I 1305120 * A circuit board having a line; a plurality of first line surfaces, a flute formed on the core board, the second line: : = formed on the surface of the high dielectric material layer, and the layer, 1 in: The electrically conductive structure is electrically connected to the first circuit, and the first-electrode layer is electrically connected to the first electrode; the -, the road-adding layer structure is formed on the second wire layer,兮AA & Lingzhi and Hui dielectric materials Qianlu addition structure includes a dielectric layer, a circuit layer on the layer, and a conductive layer formed in the dielectric layer. Through the conductive structure, it can be electrically connected to:::=;中>#你ea,<牧王成弟一线路层, ' ^Λ路增层结构外面 has a complex electrical connection line increase; The plug is covered with a solder mask from the ± Hall and the 5th open/Hr surface, and the solder resist layer has an electrical connection pad which is formed by the resurfacing of the outer surface of the line build-up structure. The circuit board structure of the embedded passive component of the invention is electrically connected to the capacitive components located on opposite surfaces of the core board, and the L is exempted from being transmitted through the circuit layer to increase the impedance and the shortage of the wiring. Therefore, the path is shortened to improve the electrical quality; and the conductive column is used for the electrical connection directly, and the prior art technology can be dispensed with the plug material to avoid the delamination caused by the difference in the expansion coefficient of the fr. Missing; the V-pillar is electrically connected to the capacitive elements on both surfaces of the core board, so that the conventional plug = material filling hole can be eliminated, and the aperture can be reduced to reduce the wiring space to improve the fabric ' ^ and can reduce the core The thickness of the board is used for the purpose of thinning the structure of the board. [Embodiment] The following embodiments of the present invention are described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and advantages of the present invention from the disclosure of the present disclosure 10 19707 1305120. [First Embodiment] Please refer to the 2A to 2F gang's total inferiority circuit board: the first implementation of the system::;: f is the core board of the circuit board of the line 2 :,, in: Hai 2: anti 2;: edge plate ί has - through the opening 210. The core plate 21 is formed at least as shown in Figs. 2B and 2C. The middle surface of the opening 210 of the core panel 21 is formed - a - line (four) ^. Then, in the core board 21, 々β λ e 23 ' and the electroplating to form the conductive 枉 22 > 5 筮 circuit layer 23 method 2 "main 22 and the same as the 2D figure _ technology, here It is no longer described in the text. __ θ does not, and then forms a high dielectric material layer 24 on the core board 21, the life guide layer - the circuit layer 23 and the second layer of the second layer of the dielectric layer. And the electrode pad %, the surface of the high dielectric material layer is formed into a second structure 25] electrically connected to the second circuit layer 25, and the conductive layer is formed on the high dielectric layer 23, and the electrode pad is made up of The electric current corresponds to the position of the conductive post 22, and the capacitive element 2a. A material layer 24 and the conductive post 22 constitute an electric device as shown in FIG. 2F, and the upper layer 27 of the electrode forming layer 2 and the electrode pad 26 are formed. The stacked layer structure 27 includes a circuit layer 272 having a conductive germanium in the dielectric layer, and is formed on the second line; the conductive structure (7) is electrically connectable to the line build-up structure The outer surface of the 27 has a reticular 19707 1305120 ^ splicing pad 274, and the outer surface of the 増 layer structure 27 is covered with a 2 layer 28 ' and The solder resist layer 28 has a plurality of openings 2 - an electrical connection pad 27 for the outer surface of the line build-up material 27 [according to the above method], the present invention also discloses an electric 21 〇 anti-U system for burying passive components The core board 21' includes at least a through hole mV main 22' system electric ore formed in the opening 210 of the core board 21; a material: a circuit layer 23' is formed on the surface of the board The high dielectric material (3) 2 4 ' is formed on the core board 21, the conductive pillars 2 2 and the first circuit layer "the second circuit layer 25 and the electrode layer 26, which are formed on the surface of the high dielectric 2:, 4: § The second circuit layer 25 is permeable to the conductive structure 251. Ancient: =: ^ "One circuit layer 23'. The electrode pad 26 is formed at the position of the conductive column 22, so that the = 亟塾 26, the bureau The electric material layer 24 and the conductive column 22 constitute a capacitor element. The structure does not form an extended electrode 于 on the end surface of the conductive post, so the embodiment can reduce the wiring space and increase the wiring density. Further comprising a line buildup layer formed on the second circuit layer 25 and the electrode pad 26, the structure 27 includes a dielectric layer 27 叠 叠 置于 该 屉 屉 屉 屉 屉 , , , , 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 The 273 series can be electrically connected to the first _. V ^ '''° (4) The outer surface has a plurality of electric electrodes 2: 4: the outer surface of the road-adding layer structure 27 is embossed with a solder resist layer 28, and the anti-tank layer u Number of openings 280 to expose the electrical connection of the outer surface of the line build-up structure 27 ^ 19707 12 1305120 « ( 274. [The brothers consistently apply] Please refer to the third embodiment of the circuit board structure The buried passive component of the present invention is co-located in that the conductive column blood is not reflected, and is not connected to the circuit layer of the third embodiment as shown in the third embodiment. The figure is not, mention / j £ 〇 〇 板, insulation board or I ancient & ', X heart board 3 1, the core board is Tao 'circuit circuit 柘,,,, τ pressure copper box The core plate 31 is described as having a thin gold surface on the surface of the resin 31. The core plate is less than one through the opening 31G layer 3U, and is formed in the core plate a thin metal layer & formed on the surface of the L core plate 1 in the dry hole and the opening 3iG as in the third drawing
It όΡ> ^ . 冷电層32，藉由該導電層32具有 導電之特性以供後續之電鍍製程。 -有 如第3C圖所示， 及開孔310中的導電層 於該開孔3 10中形成一 31a 以 於§亥核芯板31表面之薄金屬層 32表面電鍍形成一金屬層33, 實心之導電柱34。 如第3D圖所示，然後該金屬層33、導電層32及薄金 屬層31a進行圖案化製程以在該核芯板11表面形成第一線 路層35及至少一第一電極墊36a;其中該第一電極墊 係形成於該導電柱34之端面。 如第3E圖所示，然後於該核芯板21、第一線路層％ 及第一電極墊36a上形成一高介電材料層36b，再於該高 介電材料層36b表面形成第二線路層37及第二電極墊 36c ’且該第二線路層37係可透過導電結構371電性連接 13 19707 1305120 4 · 至該第-線路層35,俾 層36b及第二電極塾36c構介電材料 一線路層35及第一電極墊 ，、中，该弟 表示）。 係了相互電性連接（圖式中未 如第3F圖所示’於該第二線路層 上形成線路增層結㈣，該線路增層結構;^ :層38卜畳置於該介電層上之線路層3 ; 介電層中之導電結構3 8 3，且以供線路層3 8 2透及二成於= 結構383電性連接至該第二線路層37,又 _ 3"卜表面具有複數電性連接塾 ：：：構 冰本品φ 力7、4綠路增層結構 外表面後盍—防焊層39，且該防焊層39中具有複數門 孔390以露出該線路增層結構％外表面之電性連接塾汗 384 〇 依上述之製法，本發明係提供一種後埋被動元件之命 係包括：核芯板31，具有至少-貫穿之開： Η0, ν %柱34’係電鍍形成於該核芯板31之開孔31〇中； 第一線路層35及第—電極墊36a，係形成於該核芯板η’ 表面上，且該第一電極墊36a係形成於該導電柱％之端 面；高介電材料層36b，係形成於該核芯板31、第一線路 層35及第一電極墊36a上；以及第二線路層37及第二電 極墊36c，係形成於該高介電材料層3讣表面，該第二線 路層37係藉由導電結構371以電性連接至該第一線路層 35 ’而該第二電極墊36c係對應該導電柱34端面之第一曰電 極塾36a位置，且形成於該高介電材料層36b表面，俾^ 19707 14 1305120 l · 該第一電極墊36a、高介電材料層36b及第二電極墊36e 構成電容元件36。 此外，該第一電極墊36a係可電性連接該第—線路層 35,使該核芯板31其中—表面之電容元件36得單獨使用曰， 或者可直接藉由該導電柱34串聯另—表面之電 以合併使用。 因此’本發明之嵌埋被動元件之電路板結構，係在該 柱之兩端分別形成電容元件，而可藉由該導電柱直接 電性連接位在該核怎板兩相對表面之電容 限抗及免除佈線，因而得以提升電性品質；且直==低 的導電柱作電性連接，而得免除習知 Λ " 數不同導致熱製程中造成脫層之缺Π = “柱電性連接核芯板兩表面的電容元件，得免除二 孔材料填孔，而可縮小孔徑， “自σ基 密度，並且可減少核芯板:提高佈線 目的。 度以達潯化電路板結構之 上，實施例僅為例示性說明本發明 二限制本發明。任何熟習此項技藝::二可 廷月本發明之精神及範疇下， = 與變化。因此，本發明之權利 ^把例進行修飾 專利範圍所列。 …耗圍’應如後述之申請 【圖式簡單說明】 第1Α至1 η圖係習知電容 電錢導通孔電性連接之製程剖視圖^於核芯板表面並以 19707 15 1305120 第2A至2F圖係為本發明之嵌埋被動元件之電路板結 構之第一實施例之製法剖面示意圖；以及 第3A至3F圖係為本發明之嵌埋被動元件之電路板結 構之第二實施例之製法剖面示意圖。 【主要元件符號說明】 11、 21、31 核芯板 110、210、310 核芯板開孔 190、280、390 防焊層開孔 φ 112 空心部 1 la、31a 薄金屬層 12、 32 導電層 13、 33 金屬層 14 塞孔材料 15、182、272、382 線路層 15 ' 23 、 35 15a 16 ' 2a ' 36 16a、36a 16b、24、36b 16c 、 36c 、 17 18 、 27 、 38 181 、 271 、 381 第一線路層 電鍍導通孔 電容元件 第一電極墊 南介電材料層 第二電極墊 線路增層結構 介電層 183、 251、273、371、383 導電結構 184、 274、384 電性連接墊 16 19707 1305120 19、28、39 防焊層 22、32、34 導電柱 25、37 第二線路層 26 電極塾It όΡ> ^. The cold electric layer 32 is electrically conductive for the subsequent electroplating process. - as shown in FIG. 3C, and the conductive layer in the opening 310 forms a 31a in the opening 3 10 to form a metal layer 33 on the surface of the thin metal layer 32 on the surface of the core board 31, solid Conductive column 34. As shown in FIG. 3D, the metal layer 33, the conductive layer 32, and the thin metal layer 31a are patterned to form a first wiring layer 35 and at least a first electrode pad 36a on the surface of the core board 11; The first electrode pad is formed on an end surface of the conductive pillar 34. As shown in FIG. 3E, a high dielectric material layer 36b is then formed on the core board 21, the first circuit layer % and the first electrode pad 36a, and a second line is formed on the surface of the high dielectric material layer 36b. The layer 37 and the second electrode pad 36c' are electrically connected through the conductive structure 371 to the first circuit layer 35, and the second layer 36b and the second electrode 36c are dielectrically connected. The material is a circuit layer 35 and a first electrode pad, and the middle body is shown). Electrically connected to each other (not shown in FIG. 3F in the drawing, forming a line build-up junction (4) on the second circuit layer, the line build-up structure; ^: layer 38 is placed on the dielectric layer The upper circuit layer 3; the conductive structure 383 in the dielectric layer, and the circuit layer 382 is transparent and the second structure is 383 electrically connected to the second circuit layer 37, and _ 3 " Having a plurality of electrical connections :::: ice constituting the product φ force 7, 4 green road layering structure outer surface back 盍-soldering layer 39, and the solder resist layer 39 has a plurality of gate holes 390 to expose the line increase Electrical connection of the outer surface of the layer structure % 384 384 According to the above method, the present invention provides a lifeline of the buried passive component comprising: a core plate 31 having at least a through opening: Η0, ν % column 34 The plating is formed in the opening 31 of the core board 31; the first wiring layer 35 and the first electrode pad 36a are formed on the surface of the core board η', and the first electrode pad 36a is formed. a surface of the conductive pillar %; a high dielectric material layer 36b formed on the core board 31, the first wiring layer 35, and the first electrode pad 36a; The second circuit layer 37 and the second electrode pad 36c are formed on the surface of the high dielectric material layer 3, and the second circuit layer 37 is electrically connected to the first circuit layer 35' by the conductive structure 371. The second electrode pad 36c is disposed at a position corresponding to the first germanium electrode 36a of the end surface of the conductive pillar 34, and is formed on the surface of the high dielectric material layer 36b, 19^19707 14 1305120 l · the first electrode pad 36a, high dielectric The material layer 36b and the second electrode pad 36e constitute the capacitor element 36. In addition, the first electrode pad 36a is electrically connected to the first circuit layer 35, so that the capacitive element 36 of the core plate 31 is used separately.曰, or directly by the conductive column 34 in series with the other surface of the electricity for combination. Therefore, the circuit board structure of the embedded passive component of the present invention forms a capacitive element at each end of the column, and can be borrowed The conductive column is directly electrically connected to the capacitance limit of the opposite surfaces of the core plate and the wiring is eliminated, thereby improving the electrical quality; and the direct == low conductive column is electrically connected, and the conventional connection is eliminated. Λ " The number is different and causes the heat process to be made The defect of delamination = "The column is electrically connected to the capacitive components on both surfaces of the core board, which eliminates the hole filling of the two-hole material, and can reduce the aperture, "self-sigma basis density, and can reduce the core board: improve the wiring purpose. The present invention is merely illustrative of the present invention, and is merely illustrative of the present invention. Any skill in the art: the spirit and scope of the present invention, = and change. The invention of the present invention is exemplified by the scope of the modified patents. ... The consumption should be as described later [Simplified description of the drawings] The first to the 1st η diagram is a cross-sectional view of the process of electrical connection of the capacitor electric money via hole ^ FIG. 2 is a schematic cross-sectional view showing a first embodiment of a circuit board structure embedding a passive component of the present invention on the surface of the core board and 19707 15 1305120; and FIGS. 3A to 3F are diagrams of the present invention A schematic cross-sectional view of a second embodiment of a circuit board structure embedding a passive component. [Main component symbol description] 11, 21, 31 Core board 110, 210, 310 Core board opening 190, 280, 390 Solder mask opening φ 112 Hollow part 1 la, 31a Thin metal layer 12, 32 Conductive layer 13, 33 metal layer 14 plug material 15, 182, 272, 382 circuit layer 15 ' 23, 35 15a 16 ' 2a ' 36 16a, 36a 16b, 24, 36b 16c, 36c, 17 18, 27, 38 181, 271 381 first circuit layer electroplated via capacitor element first electrode pad south dielectric material layer second electrode pad line buildup structure dielectric layer 183, 251, 273, 371, 383 conductive structure 184, 274, 384 Pad 16 19707 1305120 19, 28, 39 solder mask 22, 32, 34 conductive post 25, 37 second wiring layer 26 electrode
17 1970717 19707