DE112004003046B4 - Power semiconductor devices - Google Patents

Abstract

A semiconductor device (3300) comprising: - a drift region (3306) of a first conductivity type, - a well region (p) extending over the drift region (3306) and having a second conductivity type opposite to the first conductivity type, - a plurality of active trenches (3302) extending through the well region (p) and into the drift region (3306), wherein within each of the plurality of active trenches (3302) are formed: a first conductive gate electrode (3310) is disposed along and insulated from a first trench sidewall, a second conductive gate electrode (3310) disposed along and insulated from a second trench sidewall, a conductive shield electrode (3311) disposed between the first (3310) and the second (3310) conductive gate electrode is arranged, wherein the shielding electrode (3311) opposite to the first (3310) and the second (331 0) gate electrode and extends deeper into the trench (3302) than the first (3310) and second (3310) gate electrodes, the conductive shield poly extending vertically to the silicon surface along the height of the trench extends to above a height of the first and second conductive gate electrodes, first conductivity type source regions (n +) formed within the well region (p) and adjacent to the plurality of active trenches (3302), and a circumferential trench (2603A, 3213) extending at least partially around the plurality of active trenches (3302) so that at least some of the trenches (3302) of the plurality of active trenches (3302) are perpendicular to the circumferential trench (2603A, 3213) wherein the conductive shield electrode (3311) is electrically connected to the source metallization, wherein the peripheral trench (2603A, 3213) is lined with a dielectric (2605A) and coated with conductive material (2607A) wherein the first conductive gate electrode (3310) and the second conductive gate electrode (3310) are connected along a third dimension within the plurality of active trenches (3302).

Description

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor devices and, more particularly, to various embodiments for improved power semiconductor devices, such as transistors and diodes, and their fabrication processes, including packages and circuits incorporating the same.

The key component in power electronics applications is the solid state switch. From ignition control in automotive applications to end-user battery-powered electronic devices, as well as to power converters in industrial applications, there is a need for a circuit breaker that optimally meets the needs of the particular application. Solid-state switches, including, for example, the power metal oxide semiconductor field effect transistor (MOSFET), the insulated gate bipolar transistor (IGBT), and various types of thyristors, have been continually evolving to meet this need. In the case of the power MOSFET, for example, double-diffused structures (DMOS) with lateral channel (e.g. US 4 682 405 A for Blanchard et al.), trench gate structures (e.g. U.S. Patent No. 6,429,481 for Mo et al.) and various techniques for charge compensation in the transistor drift region (eg US 4,941,026 A for Temple US 5 216 275 A for Chen and US Pat. No. 6,081,009 A for Neilson) along with many other techniques have been developed to address the divergent and often conflicting performance requirements.

Some of the defining performance characteristics for the circuit breaker are its on-resistance, breakdown voltage and switching speed. Depending on the requirements of a particular application, a different emphasis is placed on each of these performance criteria. For example, for power applications greater than about 300-400 volts, the IGBT exhibits an inherently lower on-resistance compared to the power MOSFET, but its switching speed is lower because of its slower turn-off characteristics. Therefore, for applications of more than 400 volts with low switching frequencies requiring low on-resistance, the IGBT is the preferred switch, whereas the power MOSFET is often the device of choice for relatively higher frequency applications. When the frequency requirements of a given application dictate the type of switch that is used, the voltage requirements determine the structural design of the particular switch. For example, in the case of the power MOSFET, improving the voltage _{capability of} the transistor while maintaining a low R _{DSon poses} a challenge because of the proportional relationship between the drain-source on-resistance R _DSon and the breakdown voltage. To address this challenge, Various charge balancing structures have been developed in the transistor drift area with varying degrees of success.

The performance parameters of the device are also affected by the manufacturing process and packaging of the chip. Attempts have been made to address some of this challenge by developing a variety of improved processing and packaging techniques.

Whether this is in particularly portable consumer electronic devices or routers and hubs in communications systems, the types of circuit breaker applications continue to grow with the spread of the electronic industry. The power switch therefore remains a semiconductor device with a high development potential.

Semiconductor devices of the type mentioned are, for example, from US 2003/0197220 A1 , of the WO 03/023861 A2 , of the EP 1 369 927 A2 , of the US Pat. No. 5,998,833 , of the US Pat. No. 6,037,628 , of the EP 1 168 455 A2 , of the US 2003/0 006 452 A1 , of the US 2003/0 080 378 A1 , of the US 2003/0 047 776 A1 , and the DE 100 38 177 A1 known.

BRIEF SUMMARY OF THE INVENTION

The present invention provides various embodiments of power devices for a wide variety of power electronics applications. More broadly, an aspect of the invention combines a number of charge balancing techniques and other techniques to reduce parasitic capacitance to arrive at various embodiments for power devices having improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. According to another aspect of the invention, charge balanced power devices include temperature and current sensing elements, such as diodes, on the same chip. Other aspects of the invention improve equivalent series resistance (ESR) or gate resistance for power devices.

These and other aspects of the invention will be described in more detail below in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

1 FIG. 12 is a cross-sectional view of a portion of an exemplary n-type trench power MOSFET; FIG.

2A shows an exemplary embodiment of a dual trench power MOSFET;

2 B shows an exemplary embodiment for a planar gate MOSFET and a source-shield trench structure;

3A FIG. 12 shows part of an exemplary embodiment of a shielded gate trench power MOSFET; FIG.

3B FIG. 12 illustrates an alternative embodiment for a shielded gate trench power MOSFET that incorporates the dual trench structure of FIG 2A with the shielded gate structure of 3A combined;

4A FIG. 10 is a simplified partial diagram of an exemplary embodiment of a dual-gate trench power MOSFET; FIG.

4B shows an exemplary power MOSFET combining a planar dual gate structure with vertical charge control trench electrodes;

4C FIG. 12 shows an exemplary implementation of a power MOSFET that combines the dual gate and shielded gate techniques within the same trench; FIG.

4D and 4E FIG. 12 are cross-sectional diagrams of alternative embodiments for a power MOSFET having a deep body structure; FIG.

4F and 4G illustrate the influence of trenched deep body structures on the distribution of potential lines within the power MOSFET near the gate electrode;

6 shows a simplified cross-sectional view of a power MOSFET that combines an exemplary vertical charge control structure with a shielded gate structure;

7 shows a simplified cross-sectional view of another power MOSFET combining an exemplary vertical charge control structure with a dual gate structure;

12 FIG. 12 shows an exemplary embodiment for power MOSFETs combining shielded gate and double gate techniques, each with charge compensation across a buried diode; FIG.

14 shows a simplified embodiment of an exemplary power transistor of the accumulation mode with alternating conductivity regions, which are arranged parallel to the current flow;

15 Fig. 10 is a simplified diagram of another accumulation mode device with trench electrodes for charge propagation purposes;

16 FIG. 10 is a simplified diagram of an exemplary accumulation mode dual trench device; FIG.

24 FIG. 12 shows an exemplary embodiment for dual-gate or dual-gate superconducting power MOSFETs; FIG.

25A shows a top view of an active and termination trench layout for a trench transistor;

25B - 25F show simplified layout views of alternative embodiments for trench termination structures;

26A - 26C FIG. 10 is cross-sectional views of exemplary trench termination structures; FIG.

27 shows an exemplary device with termination trenches having large radii of curvature;

30A shows an example of edge bonding for trench devices;

30B - 30F show exemplary process steps in forming the edge contacting structure for a trench device;

31A FIG. 10 is an example of an active area contact structure for multiple buried poly layers; FIG.

31B - 31M FIG. 10 illustrates an example process flow for forming a shield contact structure of an active area for a trench; FIG.

31N FIG. 12 is a cross-sectional view of an alternative embodiment for a shield contact structure of an active area; FIG.

32A and 32B FIG. 10 is a layout view of an exemplary trench device having a shield contact structure of an active area; FIG.

32C - 32D FIG. 10 are simplified layout diagrams of two embodiments for making contact with the circumferential trench in a trench device having a broken trench structure; FIG.

33A Figure 4 is an alternative embodiment for contacting trench-shielding poly layers in the active area;

33B - 33M FIG. 12 shows an example of a process flow for contacting a shielding structure of an active area with that in FIG 33A type shown;

60 is a simplified diagram of a MOSFET with a current measuring device;

61A is an example of a charge balance MOSFET having a planar gate structure and an isolated current sensing structure;

61B shows an example of integrating a current measuring device with a trench MOSFET;

62A - 62C show alternative embodiments for a MOSFET with series temperature measuring diodes;

63A and 63B show alternative embodiments for a MOSFET with ESD protection;

64A - 64D show examples of ESD protection circuits;

65 FIG. 10 illustrates an example process for forming charge balance and lower ESR power devices. FIG.

The FIG. are not consecutively numbered.

DETAILED DESCRIPTION OF THE INVENTION

The power switch may be implemented by any one of power MOSFET, IGBT, various types of thyristors, and the like. Many of the novel techniques presented herein are described in connection with the power MOSFET for purposes of illustration. It should be understood, however, that the various embodiments of the invention described herein are not limited to the power MOSFET and can be applied to many other types of power switching technologies, including IGBTs and other types of bipolar switches, and various types of thyristors and diodes include. Further, for purposes of illustration, the various embodiments of the invention are shown to include specific p- and n-type regions. It will be understood by those skilled in the art that the teachings herein are equally applicable to devices in which the conductivities of the various regions are reversed.

In 1 FIG. 12 is a cross-sectional view of a portion of an exemplary n-type power MOSFET. FIG 100 to see with n-type trench (trench). As with all other figures described herein, it should be understood that the relative dimensions and sizes of various elements and components illustrated in the figures do not accurately reflect the actual dimensions and are for illustrative purposes only. The trench MOSFET 100 includes a gate electrode that resides within trenches 102 is formed, extending from the top surface of the substrate through a p-type well or body area 104 extend and in an n-type drift or epitaxial region 106 end up. The trenches 102 are with thin dielectric layers 108 lined and with conductive material 110 , such as doped polysilicon, substantially filled. N-type source regions 112 are within the body area 104 adjacent to the trenches 102 educated. A drain connection for MOSFET 100 is formed on the backside of the substrate, which has a heavily doped n + substrate region 114 connected is. In the 1 The structure shown is repeated many times on a common substrate made, for example, of silicon to form an array of transistors. The array can be configured in various cellular or strip architectures formed in the art. When the transistor is turned on, it will be between the source areas 112 and the drift area 106 along the walls of the gate trenches 102 vertically formed a conductive channel.

Because of its vertical gate structure, the MOSFET allows 100 a higher packing density compared with a planar gate device, and the higher packing density results in a relatively low on-resistance. To improve the breakdown voltage capability of this transistor is a strong p + body region 118 inside the p-tub 104 formed such that at the interface between the strong p + body 118 and the p-tub 104 an abrupt transition is formed. By the depth of the strong p + body 118 is controlled relative to the trench depth and the depth of the well, electric fields generated when voltage is applied to the transistor are moved away from the trenches. This increases the avalanche current handling capability of the transistor. Variations of this improved structure and these improved processes for forming the transistor, and in particular the abrupt junction, are described in more detail in US Pat US Pat. No. 6,429,481 B1 for Mo et al. described.

Although a vertical trench MOSFET 100 With good on-resistance and improved roughness, it has a relatively high input capacitance. The input capacitance for the trench MOSFET 100 has two components: gate-source capacitance Cgs and gate-drain capacitance Cgd. The gate-source capacitance Cgs results from the overlap between the conductive material 110 of the gate and the source areas 112 near the top of the trench. The capacitance formed between the gate and the inverted channel in the body also contributes to Cgs, since in typical power switching applications the body and the source electrodes of the transistor are shorted together. The gate-drain capacitance Cgd results from the overlap between the conductive material 110 of the gate at the bottom of each trench and the drift area 106 which is connected to the drain. The gate-drain capacitance Cgd or the Miller capacitance limits the transition time of the transistor V _DS . Therefore, higher Cgs and Cgd lead to significant switching losses. These switching losses are becoming increasingly important as power management applications move toward higher switching frequencies.

One way to reduce the gate-to-source capacitance Cgs is to decrease the channel length of the transistor. A shorter channel length directly reduces the gate channel component of Cgs. A shorter channel length is also directly proportional to R _DSon and allows obtaining the same device _{current capability} with fewer gate trenches. This reduces both Cgs and Cgd by reducing the amount of gate-source and gate-drain overlap. However, a shorter channel length renders the device prone to punch-through when the depletion layer formed as a result of the reverse biased body-drain junction pushes deeply into the body region and approaches the source regions. Reducing the doping concentration of the drift region to carry more of the depletion layer has the undesirable effect of _increasing the on-resistance R _{DSon of} the transistor.

An improvement in the transistor structure that allows channel length reduction and is also effective to address the above drawbacks uses additional "shield" trenches that are laterally spaced from gate trenches. In 2A is an exemplary embodiment of a double trench MOSFET 200 shown. The terminology "double trench" refers to the transistor having two different types of trenches as opposed to the total number of similar trenches. In addition to the design features that the MOSFET of 1 in common includes the double trench MOSFET 200 Abschirmgräben 220 that exist between the neighboring gate trenches 202 are arranged. In the in 2A In the exemplary embodiment shown, the shield trenches extend 220 from the surface through p + area 218 , Body area 204 and in the drift area 206 well below the depth of the gate trenches 202 , The trenches 220 are with a dielectric material 222 lined and are with conductive material 224 , such as doped polysilicon, substantially filled. A metal layer 216 connects the conductive material 224 inside the trenches 220 electrically with n + source regions 212 and strong p + body areas 218 , In this embodiment, the trenches may therefore be referred to as source shielding trenches. An example of this type of dual trench MOSFET and a process for making and circuiting the same are described in more detail in U.S. Patent No. 5,309,866 US 2004/0 021 173 A1 entitled "Dual Trench Power MOSFET" by Steven Sapp.

The importance of deeper source shielding trenches 220 is, the depletion layer, which is formed as a result of the reverse biased body-drain junction, deeper into the drift region 206 to push. Thus, a wider depletion region can result without increasing the electric field. This allows the drift region to be doped higher without lowering the breakdown voltage. A higher doped drift region reduces the on-resistance of the transistor. Moreover, the reduced electric field in the vicinity of the body-drain junction allows the channel length to be substantially reduced, further reducing the on-resistance of the transistor and further reducing the gate-to-source capacitance Cgs. Also compared with the mosfet of 1 allows the dual trench MOSFET to obtain the same transistor current capability with far fewer gate trenches. This significantly reduces the gate-to-source and gate-to-drain overlap capacities. It should be noted that in the exemplary in 2A In the embodiment shown, the conductive layer 210 of the gate trench is buried within the trench, thereby eliminating the need for the interlayer dielectric dome above the trenches 102 in the 1 shown MOSFET 100 is available. Also, the use of source shield trenches as contemplated herein is not limited to trench gate MOSFETs, and similar advantages are obtained when source shield trenches are employed in planar MOSFETs in which the gate is disposed horizontally on the top surface of the MOSFET Substrate is formed. An exemplary embodiment for a planar gate MOSFET and source-shield trench structure is shown in FIG 2 B shown.

In order to further reduce the input capacitance, additional design improvements focusing on reducing the gate-drain capacitance Cgd may be made. As discussed above, the gate-drain capacitance Cgd is caused by the overlap between the gate and drift regions at the bottom of the trench. One method of reducing this capacitance increases the thickness of the gate dielectric layer at the bottom of the trench. Again after 2A are gate trenches 202 shown to have a thicker dielectric layer 226 at the bottom of the trench, where there is an overlap with the drift area 206 There are (the transistor-drain terminal), as compared with the dielectric layer along the side walls of the gate trench. This reduces the gate-drain capacitance Cgd without degrading the conduction of the transistor in the forward direction. The creation of a thicker dielectric layer at the bottom of the gate trench can be accomplished in a variety of ways. An exemplary process for providing the thicker dielectric layer is shown in FIG US Pat. No. 6,437,386 B1 for Hurst et al. described. Another way to minimize the gate-drain capacitance is to include a centrally located second dielectric core within the trench that extends upwardly from the dielectric liner on the trench bottom. In one embodiment, the second dielectric core may extend all the way up to cover the dielectric layer over the conductive material 210 to contact the trench. An example of this embodiment and modifications thereof are more fully described in U.S.P. US Pat. No. 6,573,560 B1 described for Shenoy.

Another technique for reducing the gate trench capacitance Cgd involves shielding the gate using one or more biased electrodes. According to this embodiment, within the gate trench and under the conductive material forming the gate electrode, one or more electrodes are formed to shield the gate from the drift region, thereby substantially reducing the gate-drain overlap capacitance. In 3A is part of an exemplary embodiment of a trench MOSFET 300A Shielded gate shown. The trenches 302 in MOSFET 300A comprise a gate electrode 310 , and in this example two additional electrodes 311 and 311b under the gate electrode 310 , The electrodes 311 and 311b shield the gate electrode 310 from any significant overlap with the drift region 306 , which almost eliminates the gate-drain overlap capacity. The shielding electrodes 311 and 311b can be independently biased with optimal potential. In one embodiment, one of the shield electrodes 311 or 311b be biased with the same potential as the source terminal. Similar to the double trench structure, biasing the shield electrodes may also help in expanding the depletion region formed at the body-drain junction, further reducing Cgd. It should be understood that the number of shielding electrodes 311 Depending on the switching application and in particular the voltage requirements of the application may vary. Similarly, the size of the shield electrodes may vary in a given trench. For example, the shielding electrode 311 larger than the shielding electrode 311b , In one embodiment, the smallest shield electrode is closest to the bottom of the trench, and the size of the remaining shield electrodes gradually increases as they approach the gate electrode. Independently biased electrodes within the trenches may also be used for vertical charge control purposes to achieve smaller forward voltage loss and higher blocking capability. This aspect of the transistor structure, which will be described below in connection with higher voltage devices, is also described in greater detail in U.S. Patent No. 5,376,474 US 2003/0 073 287 A1 entitled "Semiconductor Structure with Improved Smaller Forward Voltage Loss and Higher Blocking Capability" by Kocon.

3B illustrates an alternative embodiment for a shielded gate trench MOSFET 300B who made the double-trench structure of 2A with the shielded gate structure of 3A combined. In the in 3B The exemplary embodiment shown includes the gate trench 301 a gate poly 310 over a shielding poly 311 similar to the ditch 302 of MOSFET 300A , MOSFET 300B however, includes non-gate trenches 301 that can be deeper than the gate trenches 302 , for vertical charge control purposes.

While the cargo control trenches 301 a single layer of conductive material (e.g., polysilicon) bonded to the source metal at the top of the trench, as in FIG 2A , uses the in 3B As shown embodiment poly-electrode stacked several times 313 that can be independently biased. The number of electrodes 313 which are stacked in a trench may vary depending on the application requirements, as well as the sizes of the 3B shown electrodes 313 can. The electrodes may be independently biased or electrically connected together. The number of charge control trenches within a device will also depend on the application.

Yet another technique for improving the switching speed of the power MOSFET reduces the gate-drain capacitance Cgd by applying a double-gate structure. According to this embodiment, the gate structure within the trench is split into two segments: a first segment that satisfies the conventional gate function that receives the switching signal, and a second segment that covers the first gate segment before the drift (drain ) Area and can be independently biased. This drastically reduces the gate-drain capacitance of the MOSFET. 4A FIG. 4 is a simplified partial diagram of an exemplary embodiment of a dual-gate trench MOSFET. FIG 400A , As it is in 4A is shown, the gate of the MOSFET 400A two segments G1 and G2. Unlike the shielding electrodes ( 311 and 311b ) in MOSFET 300A from 3A indicates the conductive material, the G2 in MOSFET 400A forms an overlap area 401 with the channel on and therefore acts as a gate terminal. However, this secondary gate G2 is biased independently of the primary gate G1 and does not receive the same signal driving the switching transistor. Instead, in one embodiment, G2 is biased with a constant potential just above the threshold voltage of the MOSFET to the channel in the overlap region 401 to invert. This will ensure that a continuous channel is formed when making a transition from the secondary gate G2 to the primary gate G1. Also, Cgd is reduced because the potential at G2 is higher than the source potential, and the charge transfer away from the drift region and into the secondary gate G2 further contributes to a reduction in Cgd. In another embodiment, the secondary gate G2 may be biased, rather than having a constant potential, with a potential above the threshold voltage just prior to the switching event. In other embodiments, the potential at G2 may be variably set and optimally adjusted to minimize any parasitic portion of the gate-drain capacitance Cgd. The dual-gate structure can be applied in planar gate MOSFETs as well as in other types of trench-gate power devices, including IGBTs and the like. Variations on gate-controlled double-gate MOS devices and processes for fabricating such devices are described in more detail in US Pat US 2004/0 113 202 A1 entitled "Improved MOS Gating Method for Reduced Miller Capacitance and Switching Losses" by Kocon et al. described.

Another embodiment for an improved power MOSFET is shown in FIG 4B shown, wherein an exemplary MOSFET 400B combined a planar double-gate structure with trench electrodes for vertical charge control. Primary and secondary gate terminals G1 and G2 function in a similar manner to the trench double-gate structure of FIG 4A , with deep trenches 420 provide an electrode in the drift region to spread the charge and increase the breakdown voltage of the device. In the illustrated embodiment, the shielding or secondary gate G2 overlaps the upper portion of the primary gate G1 and extends over the p-well 404 and the drift area 406 , In an alternative embodiment, the primary gate G1 extends across the shield / secondary gate G2.

The various techniques so far described, such as gate shielding and vertical charge control trench electrodes, can be combined to obtain power devices including lateral and vertical MOSFETs, IGBTs, diodes and the like whose performance characteristics are optimized for a given application. For example, the in 4A shown trench double-gate structure advantageous with vertical charge control trench structures of the in the 3B or 4B combined types are combined. Such a device would include a dual-gate active trench as shown in FIG 4A as well as deeper charge control trenches, which are either substantially filled with a single layer of conductive material (as in trenches 420 in 4B ), or through several stacked conductive electrodes (as in trenches 301 in 3B ). For lateral devices in which the drain terminal is on the same surface of the substrate as the source terminal (ie, the current flows laterally), the charge control electrodes arranged laterally would form field plates instead of being stacked in vertical trenches are. The orientation of the charge control electrodes is generally parallel to the direction of current flow in the drift region.

In one embodiment, the dual gate and shielded gate techniques are combined within the same trench to provide switching speed and reverse voltage improvements. 4C shows a MOSFET 400C , being a ditch 402C a primary gate G1, a secondary gate G2 and a shielding layer 411 which are stacked in a single trench, as shown. The ditch 402C can be made just as deep and can have as many shielding layers 411 include as the application requires. The use of the same trench for both charge balance and shield electrodes allows for higher density because it eliminates the need for two trenches and combines them into one. It also allows for greater current spreading and device on-resistance.

The devices so far described employ shielded gate, double gate, and other techniques to reduce parasitic capacitance. However, due to parasitics, these techniques do not completely minimize the gate-to-drain capacitance Cgd. In 4D FIG. 10 is a partial cross-sectional view of an exemplary embodiment of MOSFET. FIG 400D shown with a deep body construction. According to this embodiment, the body structure is through a trench 418 formed, which is etched through the middle of the mesa, between the gate trenches 402 is formed and as deep or deeper than the gate ditch 402 extends. The body trench 418 is filled with source metal as shown. The source metal layer may comprise a thin heat-resistant metal at the metal diffusion boundary (not shown). In this embodiment, the body structure comprises a p + body implantation layer 419 that dig the body 418 essentially surrounds. The p + implantation layer 419 allows additional shielding to change the potential distribution within the device, in particular close to the gate electrode. In an in 4E shown alternative embodiment is the body trench 418 essentially substantially filled with epitaxial material using, for example, selective epitaxial growth (SEG) deposition. Alternatively, the body trench 418E substantially filled with doped polysilicon. In each of these two embodiments, instead of implanting a p + shield junction 419 Following a temperature treatment, dopants diffuse from the filled body into the silicon to form a p + shield junction 419 to build. A number of modifications to a trenched body structure and their formation are more fully described in US Pat US Pat. No. 6,437,399 B1 and US Pat. No. 6,110,799 B1 both for Huang.

In both in the 4D and 4E In embodiments shown, the distance L between gate trenches 402 and body digging 418 and the relative depths of the two trenches are controlled to minimize a floating gate-drain capacitance. In the embodiments using SEG or poly-filled body trenches, the distance between the outer edges of the layer may 419 and the wall of the gate trench by adjusting the doping concentration of the SEG or poly within the body trench 418 is varied. The 4F and 4G illustrate the influence of the trenched deep body on the distribution of potential lines within the device near the gate electrode. For illustrative purposes, use the 4F and 4G MOSFETs with shielded gate structures. 4F shows the potential lines for a reverse biased MOSFET 400F with shielded gate and a ditch deep body 418 , and 4G shows the potential lines for a reverse-biased MOSFET 400G with shielded gate with a flat body structure. The contour lines in each device show the potential distribution within the device when it is reverse biased (ie, blocking off state). The white line indicates the well junction and also defines the bottom of the channel immediately adjacent to the gate electrode. As can be seen from the diagrams, there is a lower potential and a lower electric field applied to the channel and the surrounding gate for the MOSFET 400F with a ditch and a deep body of 4F is created. This lowered potential allows a reduced channel length, which reduces the overall gate charge for the device. For example, the depth of the gate trench 102 on under z. B. 0.5 microns and can be flatter than the body trench 418 be set, wherein the distance L is about 0.5 microns or smaller. In an exemplary embodiment, the distance L is less than 0.3 μm. Another advantage of this invention is the reduction in gate-to-drain charge Qgd and Miller capacitance Cgd. The lower the value of these parameters, the faster the device can switch. This improvement is realized by reducing the potential immediately adjacent to the gate electrode. The improved structure has a much lower potential that will be switched, and the induced capacitive current in the gate is much lower. This in turn allows the gate to switch faster.

The ditch-deep body structure, as used in conjunction with the 4D and 4E can be combined with other charge balancing techniques such as shielded gate or double gate structures to further improve the switching speed, on-resistance and blocking capability of the device.

The improvements provided by the above power devices and variations thereof have yielded robust switching elements for relatively low voltage power electronics applications. Low voltage, as used herein, refers to a voltage range of, for example, about 30V-40V and below, although this range may vary depending on the particular application. Applications that require blocking voltages substantially beyond this range require some form of constructive modification to the power transistor. Typically, the doping concentration in the drift region of the power transistor is reduced to make the device higher Can carry voltages during the blocking state. However, a rather lightly doped drift region leads to an increase in the on-resistance R _{DSon of} the transistor. the higher resistivity directly increases the power loss of the switch. The power loss has gained importance as recent advances in semiconductor fabrication have further increased the packing density of the power devices.

Attempts have been made to improve the on-resistance and power loss of the device while maintaining the high reverse voltage. Many of these attempts use various vertical charge control techniques to provide a substantially flat electric field vertically in the semiconductor device. A number of device structures of this type have been proposed which incorporate the lateral depletion device incorporated into the US Pat. No. 6,713,813 B2 entitled "Field Effect Transistor Having a Lateral Depletion Structure" by Marchant, and which include apparatuses disclosed in U.S. Pat US Pat. No. 6,376,878 B1 are described by Kocon.

In 6 Figure 3 is a simplified cross-sectional view of a power MOSFET suitable for higher voltage applications that also require faster switching. The MOSFET 600 Combines vertical charge control to improve breakdown voltage, with a shielded gate structure that improves switching speed. As it is in 6 is shown is a shield electrode 611 within the gate trench 602 between the conductive material of the gate 610 and the bottom of the trench. The electrode 611 shields the gate of the transistor from the underlying drain region (drift region 606 ), which significantly reduces the gate-drain capacitance of the transistor and thus increases its maximum switching frequency. Dielectric filled trenches 620 with p-doped linings 626 help to create vertically a largely flat electric field to improve the breakdown voltage of the device. In operation, the combination of dielectric filled trenches reduces 620 with p-conducting lining 626 and the shielded gate structure, the parasitic capacitance and helps to deplete the n-drift region, which scatters the electric field, which is concentrated at the edge portion of the gate electrode. Devices of this type can be used in an RF amplifier or in high frequency switching applications.

7 shows an alternative embodiment for another power MOSFET suitable for higher voltage and higher frequency applications. In the in 7 shown simplified example combines MOSFET 700 a vertical charge control to improve a breakdown voltage, with a double-gate structure that improves the switching speed. Similar to the in 6 The device shown becomes the vertical charge control through the use of dielectric filled trenches 720 with p-doped linings 726 implemented. A reduction of the parasitic capacitance is achieved through the use of a double-gate structure, whereby a primary gate electrode G1 in front of the drain (n-drift region 706 ) is shielded by a secondary gate electrode G2. The secondary gate electrode G2 may either be continuously biased or biased only before a switching event to close the channel in the range 701 to invert and thus ensure a continuous flow of current through a continuous channel when the device is turned on.

12 is a cross-sectional view of a MOSFET 1200 which combines the double-gate technique with the trench diode structure. An active ditch 1202 in MOSFET 1200 includes a primary gate G1 and a secondary gate G2 and operates in the same manner as the active trenches in the double gate MOSFET used in conjunction with FIG 4B is described. The diode trenches 1220 provide a charge balance to increase the blocking voltage of the device, while the active double-gate trench structure improves the switching speed of the device.

Any of the resulting embodiments may also be combined with the trench body technique to further minimize the harmful parasitic capacitance associated with MOSFETs 400D or 400E of the 4D and E4 is described. Other modifications and equivalents are possible. For example, the number of regions of opposite conductivity within the diode trenches may vary, as well as the depth of the diode trenches. The polarities of the regions of opposite conductivity can be reversed, as well as the polarity of the MOSFET. Also, any of the PM regions may be independently biased, if desired, by, for example, extending the respective regions along the third dimension and then up to the silicon surface where electrical contact may be made therewith. In addition, multiple diode trenches may be used, as required by the size of the device and the voltage requirements of the application, and the spacing and arrangement of the diode trenches may be implemented in various strip or cellular constructions.

In another embodiment, a class of accumulation mode transistors is provided, which are different Use charge balance techniques for a smaller forward voltage drop and higher blocking capability. In a typical accumulation mode transistor, there is no blocking transition and the device is turned off by slightly inverting the channel region adjacent to the gate to prevent current flow. On the contrary, when the transistor is turned on by applying a gate bias, an accumulation layer is formed as an inversion layer in the channel region. Since there is no formation of an inversion channel, the channel resistance is minimized. In addition, there is no PN body diode in a accumulation mode transistor, which minimizes the losses that otherwise occurred in certain circuit applications, such as synchronous rectifiers. The disadvantage of the conventional accumulation mode devices is that the drift region must be lightly doped to support reverse bias when the device is in blocking mode. A light doped drift region converts to a higher on-resistance. The embodiments described herein overcome this limitation by applying various charge balancing techniques in an accumulation mode device.

In 14 FIG. 10 is a simplified embodiment of an exemplary accumulation mode transistor. FIG 1400 shown with alternating conductivity regions, which are arranged parallel to the current flow. In this example, the transistor is 1400 an n-channel transistor with a gate connection inside trenches 1402 is formed, an n-channel channel region 1412 formed between the trenches, a drift area 1406 , the columnar n-type and p-type portions 1403 and 1405 of opposite polarity, and an n-type drain region 1414 , Unlike transistors of the enrichment mode, the transistor comprises 1400 from the accumulation mode no blocking well (p-conducting in this example) or body region in which the channel is formed. Instead, a conductive channel is formed when an accumulation layer is in the region 1412 is formed. The transistor 1400 is normal on or off, depending on the doping concentration of the area 1412 and the doping type of the gate electrode. He is off when the n-type area 1412 completely depleted and slightly inverted. The doping concentrations in the areas 1403 and 1405 with opposite polarity are set to maximize charge spread, allowing the transistor to carry higher voltages. The use of columnar regions of opposite polarity in parallel with the flow of current flattens the electric field distribution, but does not allow it to decrease linearly away from the junction between the regions 1412 and 1406 is formed. The charge propagation effect of this structure allows the use of a higher doped drift region, which reduces the on-resistance of the transistor. The doping concentration of the various regions may vary, for example, n-type regions 1412 and 1403 have the same or different doping concentrations. Those skilled in the art will appreciate that an improved p-channel transistor can be obtained by adjusting the polarities of the various regions of the in 14 shown device are reversed. Other variations of the columnar regions of opposite polarity within the drift region are described in detail in connection with ultrahigh voltage devices described below.

15 is a simplified diagram of another device 1500 from the accumulation mode and with trench electrodes for charge propagation purposes. All areas 1512 . 1506 and 1514 are of the same conductivity type, n-type in this example. For a normally off device, the gate polysilicon is 1510 furnished p-conducting. The doping concentration of the area 1512 is set such that an impoverished barrier junction is formed under no bias conditions. Inside every ditch 1502 are one or more buried electrodes 1511 under the gate electrode 1510 formed, all of dielectric material 1508 are surrounded. As it is in connection with the mosfet 300A from the enrichment mode of 3A has been described, the buried electrodes act 1511 as field plates and, if desired, can be biased to a potential that optimizes their charge propagation function. Since the charge propagation can be controlled by buried electrodes 1511 can be independently biased, the maximum electric field can be significantly increased. Similar to the buried electrodes in the MOSFET 300A applied, different variations of the structure are possible. For example, the depth of the trench 1502 and the size and number of buried electrodes 1511 vary depending on the application. Charge propagation electrodes may be buried within trenches that are separate from active trenches that house the transistor gate electrode, in a manner similar to that for the trench or trench structures of the MOSFET 300B in 3B is shown. An example of such an embodiment is in 16 shown. In the in 16 The example shown comprises the n-type region 1612 more heavily doped n + source regions 1603 which can be added optionally. Heavily doped source regions 1603 can be along the top of an n-type region 1612 as shown, or may be referred to as two regions adjacent the trench walls along the upper edge of the n-type region 1612 be formed (not in this figure shown). In some embodiments, the inclusion of n + regions 1603 a lowering of the doping concentration of the n-type region 1606 to ensure that the transistor turns off properly. This optionally heavily doped source region may be used in the same way in any of the accumulation transistors described herein.

24 shows yet another embodiment for a high voltage MOSFET 2400 that combines the super-junction technology with the shielded-gate structure. The MOSFET 2400 is a trench gate device with a gate electrode 2410 that before the drift area 2406 with a shielding electrode 2411 is shielded, similar to, for example, MOSFET 300A in 3A , MOSFET 2400 also includes floating areas 2426 opposite polarity in the drift area 2406 are arranged parallel to the current flow.

termination structures

Discrete devices of the various types described above have a breakdown voltage limited by the cylindrical or spherical shape of the depletion region at the edge of the chip. Since this cylindrical or spherical breakdown voltage is typically much lower than the parallel-plane breakdown voltage BV _pp in the active area of the device, the edge of the device must be terminated such that a breakdown voltage is achieved for the device close to the breakdown voltage of the active area lies. Various techniques have been developed to spread the field and voltage evenly across the edge termination width to achieve a breakdown voltage that is close to BV _pp . These include field plates, field rings, Junction Termination Extension (JTE), and various combinations of these techniques. The above mentioned US Pat. No. 6,429,481 B1 for Mo et al. FIG. 4 illustrates an example of a field termination structure that includes a deep junction (deeper than the well) with an overlying field oxide layer surrounding the active cell array. For example, in the case of an n-channel transistor, the termination structure includes a deep p + region that forms a PN junction with the n-type drift region.

In alternative embodiments, one or more annular trenches surrounding the periphery of the cell array act to reduce the electric field and increase avalanche breakdown. 25A shows a commonly used trench layout for a trench transistor. Active trenches 2502 are from an annular termination trench 2503 surround. In this structure impoverish areas 2506 shown by the dotted circles at the end of the mesas, faster than other areas, causing an increased field in this area which reduces the breakdown voltage under reverse voltage conditions. This type of layout is therefore limited to lower voltage devices (eg, <30V). The 25B to 25F show a number of alternative embodiments for termination structures with different trench layouts to accommodate the high electric field areas found in FIG 25A are shown to decrease. As can be seen by the diagrams, in some embodiments, some or all active trenches are separated from the termination trench. The gap WG between the ends of the active trenches and the termination trench functions to control the crowding effect of the electric field occurring in the 25A structure is observed to decrease. In an exemplary embodiment, WG is set at approximately half the width of the mesas between the trenches. For higher voltage devices, multiple termination trenches such as those described in U.S. Pat 25F can be applied to further increase the breakdown voltage of the device. The transferred US Pat. No. 6,683,363 B1 entitled "Trench Structure for Semiconductor Devices" by Challa describes variations of some of these embodiments in more detail.

The 26A to 26C 12 show cross-sectional views of various exemplary trench termination structures for charge-balanced trench MOSFETs. In the exemplary embodiment shown, MOSFET uses 2600A a shielded gate structure with a screen poly electrode 2611 that under the gate poly 2610 within the active trench 2602 is buried. In the in 26A The embodiment shown is the termination trench 2603a with a relatively thick layer of a dielectric (oxide) 2605a lined and with conductive material, such as poly 2607a , filled. The thickness of the oxide layer 2605a , the depth of the termination trench 2603a and the distance between the termination trench and the adjacent active trench (ie, the width of the last mesa) are determined by the reverse bias voltage of the device. In the in 26A In the embodiment shown, the trenches are wider at the surface (T-trench structure) and a metal field plate 2609A is used over the termination area. In an alternative embodiment (not shown), the field plate may be formed of polysilicon by poly 2607a within a termination trench 2603a above the surface and above the termination area (to the left of the termination trench in 26A ) is extended. There are many variations possible. For example, a p + range (not shown) under the metal contacts to silicon for better ohmic contact. A p-tub area 2604 in the last mesa adjacent to the termination trench 2603a and its respective contact can optionally be removed. There may also be one or more floating p-type region (s) to the left of the termination trench 2603a (ie outside the active area).

In another variation, instead of filling the termination trench 2603 with poly a poly electrode buried in the lower portion of the trench within an oxide-filled trench. This embodiment is in 26B showing approximately half of the termination trench 2603b with oxide 2605b is filled and the lower half of a polyelectrode 2607B which is buried within the oxide. The depth of the trench 2603b and the height of the buried polys 2607B can be varied based on the device processing. In yet another embodiment, the in 26C is shown is a termination trench 2603C essentially filled with a dielectric without buried non-conductive material. For all three in the 26A , B and C, the width of the last mesas separating the termination trench from the last active trench may be different than the width of the typical mesas formed between two active trenches, and may be set to provide optimum charge compensation is achieved in the termination area. All above in conjunction with the in 26A can be applied to those described in the structure shown in FIG 26B and 26C shown are applied. In addition, although the termination structures have been described for their shielded gate device, those skilled in the art will recognize that similar structures may be implemented as termination regions for all of the various trench-based devices described above.

For low stress devices, the corner designs for the trench termination ring may not be critical. However, in higher voltage devices, rounding of the corners of the termination ring having a larger radius of curvature may be desired. The higher the voltage requirements of the device, the larger the radius of curvature may be at the corners of the termination trench. Likewise, the number of termination rings can be increased as the device voltage increases. 27 shows an exemplary device with two termination trenches 2703-1 and 2703-2 that have a relatively larger radius of curvature. The spacing between the trenches may also be adjusted based on the voltage requirements of the device. In this embodiment, the distance S1 corresponds between termination trenches 2703-1 and 2703-2 approximately twice the distance between the first termination trench 2703-1 and the end of the active trenches.

process technologies

Heretofore, a number of different devices with trench structures having multiple buried electrodes or diodes have been described. To bias these trench electrodes, these devices allow for making electrical contact with each of the buried layers. Disclosed herein are a number of methods for forming the buried electrode trench structures and for making contact with the buried poly layers within the trenches. In one embodiment, contacts with trench poly layers are made at the edge of the chip. 30A shows an example of edge contact for a trench device 3000 with two poly layers 3010 and 3020 , 30A shows a cross-sectional view of the device along the longitudinal axis of a trench. According to this embodiment, where the trench terminates near the edge of the chip, poly layers are for contact purposes 3010 and 3020 led to the surface of the substrate. openings 3012 and 3022 in dielectric (or oxide) layers 3030 and 3040 allow metal contact to the poly layers. The 30B to 30F illustrate various processing steps involved in forming the edge contact structure of 30A are included. In 30B becomes a dielectric (eg, silicon dioxide) layer 3001 on top of an epitaxial layer 3006 structured, and the exposed surface of the substrate is etched to a trench 3002 to build. A first oxide layer 3003 is then formed over the upper surface of the substrate including the trench, as shown in FIG 30C is shown. A first layer of conductive material (polysilicon) 3010 is then on top of the oxide layer 3003 formed as it is in 30D is shown. To 30E becomes the poly layer 3010 etched away within the trench and another oxide layer 3030 becomes over the poly 3010 educated. Similar steps are performed to form the second oxide-poly-oxide sandwich, as shown in FIG 30F is shown, wherein the upper oxide layer 3040 is shown as etched to openings 3012 and 3022 for a metal contact layer to poly layers 3010 respectively. 3020 manufacture. The final steps may be repeated for additional poly layers, and poly layers may be bonded together by the overlying metal layer, if desired.

In another embodiment, contacts to multiple poly layers in one given trench in the active area of the device instead of along the edge of the chip produced. 31A shows an example of the contact structure of an active surface for multiple buried poly layers. In this example, a cross-sectional view along the longitudinal axis of the trench shows a poly layer 3110 which provides the gate terminal and poly layers 3111a and 3111b that provide two shielding layers. While three separate metal lines 3112 . 3122 and 3132 may be all connected to each other and connected to the source terminal of the device, or any other contacting combination may be used, as required by the particular application. An advantage of this structure is the planar nature of the contact compared to the one in 30A shown multilayer edge contact structure.

The 31B to 31M illustrate an example of a process flow for forming an active surface shield contact structure for a trench having two poly layers. The etching of trenches 3102 in 31B follows the formation of a Abschirmoxids 3108 in 31C , Subsequently, shielding polysilicon 3111 deposited and buried in the trenches, as is in 31D is shown. Shielding poly 3111 is additionally in 31E with the exception of locations where a Abschirmkontakt on the surface of the substrate is desired. In 31E protects a mask 3109 the poly within the middle trench before further etching. In one embodiment, this mask is applied at different locations along different trenches such that, for example, for the middle trench, the shield poly is recessed in other portions of the trench in the third dimension (not shown). In another embodiment, the shielding poly 3111 is masked within one or more selected trenches in the active area along the entire length of the trench. The shielding oxide 3108 is then etched as it is in 31F is shown, and then a thin layer of gate oxide 3108a formed over the top of the substrate after the mask 3109 has been removed, as it is in 31G is shown. This is followed by gate poly deposition and its insertion ( 31H , a p-well implantation and recovery ( 31I ) and an n + source implantation ( 31J ). The 31K . 31L and 31M each show the steps of BPSG deposition, contact etching and strong p + body implantation followed by metallization. 31N shows a cross-sectional view of an alternative embodiment for a Abschirmkontaktstruktur an active surface, wherein a shielding poly 3111 forms a relatively wide platform on top of the shielding oxide. This simplifies the contacting of the shielding polys, but introduces a topography that further complicates the manufacturing process.

A simplified top-down layout view of an exemplary trench device having a shield contact structure of an active area is shown in FIG 32A shown. A mask showing a shielding poly-well prevents ingress of the shielding polys in one location 3211C in the active area as well as in the circumferential shield trench 3213 , One modification of this technique uses a "dogbone" shape for the shielding poly well mask that covers a wide area at the intersection with each trench 3202 with contact with the shielding poly. This allows the shielding poly to be also embedded in the masked area, but up to the original surface of the mesa, thereby eliminating topography. The top-down layout view for an alternative embodiment is in FIG 32B shown, wherein trenches of an active surface are connected to the peripheral trench. In this embodiment, the shield poly recess mask prevents the interception of the shield polyline along the length of a selected trench (middle trench in the illustrated example) for contact of the shield trench of an active surface with source metal. The 32C and 32D FIG. 10 are simplified layout diagrams illustrating two different embodiments for making contact with the circumferential trench in a trench device having a trenched structure broken away. In these figures are active trenches 3202 and a circumferential trench 3213 shown by a single line for purposes of illustration. In 32C are extensions or fingers from a perimeter gate poly channel 3210 staggered with respect to perimeter screen poly-fingers to space the perimeter contacts away from the perimeter trench. A source and shield contact surface 3215 also places a contact with shield poly in the active area at locations 3211C as shown. In the 32D The illustrated embodiment eliminates the displacement between active and circumferential trenches to avoid a potential constraint arising from trench pitch requirements. In this embodiment, the active trenches are 3202 and horizontal extensions from the circumferential trench 3213 aligned and windows 3217 in the gate poly channel 3210 allow contacts with shielding poly to be made around the circumference. Contacts of an active area become in places 3211C produced as in previous embodiments.

An alternative embodiment for contacting trench-shielding poly layers in the active area is shown in FIG 33A shown. In this embodiment, instead of being recessed, the shielding poly extends vertically over one substantial part of the active trench up to the silicon surface. To 33A shares the shield poly 3311 the gate poly 3310 in two, since it is along the height of the trench 3302 extends vertically. The two gate poly segments are connected in the third dimension at a suitable location within the trench or as they leave the trench. An advantage of this embodiment is the area that is saved by making a source-poly contact within the active trench, rather than using a silicon space that would be provided for the trenched poly-contact. The 33B to 33M illustrate an example of a process flow for forming a shield contact structure of an active area from that in FIG 33A kind shown. The etching of trenches 3302 in 33B follows the formation of a Abschirmoxids 3308 in 33C , Subsequently, shielding polysilicon 3311 deposited inside the trenches, as in 33D is shown. Shielding poly 3311 is etched and embedded in the trenches as it is in 33E is shown. Subsequently, shielding oxide 3308 etched as it is in 33F wherein an exposed portion of the shield polysilicon 3311 leaving two hollows at its sides within the trench. A thin layer of gate oxide 3308a is then formed over the top of the substrate, the sidewalls of the trenches, and the hollows within the trenches, as in 33G is shown. This is followed by deposition and insertion of gate poly ( 33H ), p-well implantation and driving ( 33I ) and n + source implantation ( 33J ). The 33K . 33L and 33M show the steps of BPSG deposition, contact etching and strong p + body implantation, followed by metallization. Modifications of this process flow are possible. For example, by reordering some of the process steps, the process steps involving the gate poly 3310 form, before the steps are performed, the shielding poly 3311 form.

Specific process formulas and parameters and variations thereof for performing many of the steps in the above processes are well known. For a given application, certain process formulations, chemicals, and types of materials may be fine-tuned to improve the manufacturability and performance of the device. Improvements can be made from the starting material, ie, the substrate on which the epitaxial (epi) drift region is formed. In most power _applications , a reduction in the on-resistance R _{DSon of} the transistor is desired. The ideal on-resistance of a power transistor is a strict function of the critical field, which is defined as the maximum electric field in the device under breakdown conditions. The specific on-resistance of the transistor can be significantly reduced if the device is made of a material having a critical field higher than that of silicon, provided that reasonable mobility is maintained. Although many of the features of the power devices, including the structures and processes, have been described in the context of a silicon substrate, other embodiments using substrate material other than silicon are possible. In one embodiment, the power devices described herein are fabricated from a substrate made of wide bandgap material including, for example, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), diamond, and the like. These wide bandgap materials exhibit a critical field that is higher than the critical field for silicon and can allow a significant reduction in the on-resistance of the transistor.

Another primary contributor to the on-resistance of a transistor is the thickness and doping concentration of the drift region. The drift region is typically formed by epitaxially grown silicon. In order to reduce R _DSon , it is desirable to minimize the thickness of the epi drift region. The thickness of the epi-layer is dictated in part by the nature of the starting substrate. For example, a substrate doped with red phosphorus is a common type of starting substrate material for discrete semiconductor devices. However, one property of phosphorus atoms is that they diffuse rapidly in silicon. The thickness of the epi region formed on top of the substrate is therefore determined so as to balance the diffusion of phosphorous atoms upwardly from the underlying heavily doped substrate.

There are a number of other design and processing aspects of the power transistor and other power devices that can significantly affect their performance. The shape of the trench is an example. In order to reduce the potentially damaging electrical fields which tend to concentrate around the corners of the trench, it is desirable to avoid sharp corners and instead form trenches having rounded corners. To improve reliability, it is also desirable to have trench sidewalls with smooth surfaces. The different etch chemistries provide a balance between multiple responses, such as: silicon etch rate, selectivity to the etch mask, etch profile (sidewall angle), top corner rounding, sidewall roughness, and trench bottom curve. A chemical with fluorine, such as SF6, provides a high silicon etch rate (greater than 1.5 μm / min), rounded Trenching grounds and a straight profile. The drawback of the fluorochemical are rough sidewalls and difficulty controlling the top of the trench (may be reentrant). A chlorochemical, such as Cl ₂ , provides smoother sidewalls and better control of the etch profile and top of the trench. The balance with the chlorochemical concerns a lower silicon etch rate (less than 1.0 μm / min) and less rounding of the trench bottom.

As described above in connection with various shielded gate transistors, a layer of dielectric material isolates the shield electrode from the gate electrode. This inter-electrode dielectric layer, sometimes referred to as the inter-poly dielectric or IPD, must be formed in a robust and reliable manner so that it can withstand the potential difference that may exist between the shield electrode and the gate electrode. With renewed reference to the 31E . 31F and 31G a simplified procedure for the relevant processing steps is shown. After re-etching the shielding polys 3111 within the trench ( 31E ) becomes the shield dielectric layer 3108 etched back to the same level as the shielding poly 3111 ( 31F ). Subsequently, a gate dielectric layer is formed 3108a formed on the upper surface of the silicon as it is in 31G is shown. In this step, the IPD layer is formed. An artifact of this shield dielectric recess etch is the formation of shallow wells on the top surface of the shield dielectric that remain on both sides of the shield electrode.

A number of trench devices described above include trench sidewall doping for charge balancing purposes. For example, all in the 6 to 7 shown embodiments on any kind of trench sidewall doping structure. Sidewall doping techniques are somewhat limited due to the physical constraints of narrow, deep trenches and / or vertical sidewall of the trench. Gaseous sources or implants at an angle may be used to form the doped regions of the trench sidewall. In one embodiment, an improved trench sidewall doping technique utilizes plasma doping technology or pulsed plasma doping technology. This technology uses a pulsed voltage applied to the wafer enclosed in a plasma of dopant ions. The applied voltage accelerates the ions from the cathode screen toward and into the wafer. The applied voltage is pulsed and the duration is continued until the desired dose is reached. This technique allows implantation of many of these trench devices with adaptive doping techniques. In addition, the high throughput of this process reduces the overall cost of the manufacturing process.

Those skilled in the art will recognize that the use of plasma doping technology or pulsed plasma doping technology is not limited to trench charge balance structures, but may be applied to other structures including trench termination structures and trench drain, source or body interconnections. For example, this method can be used to dope the trench sidewalls of shielded trench structures, such as those used in conjunction with FIG 4D . 4E . 6 . 7 have been described. In addition, this technique can be used to form a uniformly doped channel region. The penetration of the depletion region into the channel region (p-well junction) when the power device is reverse biased or operated is controlled by the charge concentration on both sides of the junction. If the doping concentration in the epi-layer is high, depletion in the junction may allow punch-through to limit the breakdown voltage or require a longer channel length than is desired to keep the on-resistance low. To minimize depletion into the channel, a higher channel doping concentration may be required which may cause the threshold to increase. Since the threshold is determined by the peak concentration below the source in a trench MOSFET, a uniform doping concentration in the channel can provide a better balance between channel length and breakdown.

Other methods that may be used to obtain a more uniform channel concentration include forming the channel junction using an epitaxial growth process, using multiple energy implantation and other techniques to provide an abrupt transition. Another technique uses a starting wafer with a lightly doped capping layer. In this way, compensation is minimized and upward diffusion can be limited to provide a more uniform channel doping profile.

A trench device may benefit from the fact that the threshold is determined by the channel doping concentration along the trench sidewalls. A process that allows a high doping concentration away from the trenches while maintaining a low threshold can help reduce the punching Through mechanism to prevent. The provision of the p-well doping prior to the gate oxidation process allows segregation of p-type impurities of the well, e.g. Boron, into the trench oxide to reduce the concentration in the channel, thereby reducing the threshold. Combining this with the above techniques may result in a shorter channel length without punch through.

Some power applications require measuring the amount of current flowing through the power transistor. This is typically accomplished by isolating and measuring a portion of the total device current which is then used to extrapolate the total current flowing through the device. The isolated portion of the total device current flows through a current sensing or detection device which generates a signal indicative of the magnitude of the isolated current and which is then used to determine the total device current. This arrangement is commonly known as a current mirror. The current sensing transistor is typically fabricated monolithically with the power device, with both devices sharing a common substrate (drain) and gate. 60 is a simplified diagram of a MOSFET 6000 with a current measuring device 6002 , The current flowing through the main mosfet 6000 flows between the main transistor and the current measuring section 6002 divided proportionally to the active areas of each. The current flowing through the main mosfet 6000 is thus calculated by measuring the current through the measuring device and then multiplying it by the ratio of the active area.

Various methods of isolating the current measuring device from the main device are described in commonly assigned U.S. Patent Application NO. No. 10 / 315,719 entitled "Method of Isolating the Current Sense on Power Devices While Maintaining a Continuous Strip Cell" for Yedinak et al. , the disclosure of which is fully incorporated herein by reference. Embodiments for integrating the measurement device together with different power devices including those having charge balance structures will be described below. According to one embodiment, in a power transistor with charge compensation structures and a monolithically integrated current measuring device, the current measuring surface is preferably formed with the same continuous MOSFET structure and the charge compensation structure. Without maintaining continuity in the charge balance structure, the breakdown voltage of the device is degraded due to mismatch in the charge, resulting in that the voltage carrying region is not completely depleted. 61A shows an exemplary embodiment for a charge balance MOSFET 6100 with a planar gate structure and an isolated current measuring structure 6115 , In this embodiment, the charge balance structure comprises pillars 6126 of opposite conductivity (p-type in this example) within an (n-type) drift region 6104 are formed. The p-type columns 6126 For example, they may be formed as doped polysilicon or epi-filled trenches. As it is in 61A is shown, the charge balancing structures maintain continuity under the current sensing structure 6115 , The measuring pad metal 6113 , which is the area of the surface of the current measuring device 6115 covered, is from the source metal 6116 through the dielectric region 6117 separated. It is to be understood that current measuring devices having similar structures can be integrated with any of the other power devices described herein. For example, shows 61B an example of how a current sensing device may be integrated with a shielded gate trench MOSFET, wherein charge balance may be obtained by adjusting the depth of the trench and biasing the shielding poly within the trench.

There are a number of power applications where it is desired to integrate diodes on the same chip as the power transistor. Such applications include temperature measurement, electrostatic discharge (ESD) protection, active clamping and voltage division, among others. For temperature measurement, for example, one or more series-connected diodes are monolithically integrated with the power transistor, with the anode and cathode terminals of the diode being routed out to separate bond pads, or connected to monolithic control circuit components using conductive connections. The temperature is measured by the change in the voltage (Vf) in the forward direction of the diode (or diodes). For example, with proper connection to the gate terminal of the power transistor, as the Vf of the diode drops with temperature, the gate voltage is pulled down, reducing the current flowing through the device until the desired temperature is reached.

62A shows an exemplary embodiment for a MOSFET 6200A with series temperature measuring diodes. The MOSFET 6200A includes a diode structure 6215 in which doped polysilicon with alternating conductivity forms three series temperature measuring diodes. In this illustrative embodiment, the MOSFET portion of the device applies 6200A p-type, epi-filled charge balance trenches, the regions of opposite conductivity within an n-type epi-drift region 6204 form. As shown Preferably, the charge balance structure preferably maintains continuity below the temperature sensing diode structure 6215 , The diode structure is on top of a field dielectric (oxide) layer 6219 formed on top of the surface of the silicon. A p-type junction isolation region 6221 optionally under the dielectric layer 6219 be diffused. A device 6200B without this p-type transition is in 62B shown. To ensure that series diodes which are forward biased are obtained, a short-circuit metal is obtained 6223 used to short the P / N + transitions that are reverse biased. In one embodiment, p + is implanted and diffused across the junctions to form an N + / P / P + / N + structure, with p + among shorting metals 6223 appears to receive the ohmic contact. For the opposite polarity, N + can also be diffused across the N / P + junction to form a P + / N / N + / P + structure. Those skilled in the art will recognize again that this type of temperature sensing diode structure can be used in any of the foregoing power devices in combination with many other features described herein. 62C shows for example a MOSFET 6200C with a screened trench gate structure that allows the shielding poly to be used for charge balancing.

In another embodiment, by employing similar isolation techniques as used in apparatus 6200 for temperature sensing diodes, asymmetric ESD protection is implemented. For ESD protection purposes, one end of the diode structure is electrically connected to the source terminal and the other end to the gate terminal of the device. Alternatively, symmetric ESD protection is obtained by short-circuiting N + / P / N + junctions back to back, as shown in the 63A and 63B is shown. The in 63A shown exemplary MOSFET 6300a uses a planar gate structure and uses columns of opposite conductivity to charge balance, whereas in 63B shown exemplary MOSFET 6300B a trench gate device with a shielded gate structure. To prevent non-uniformities in charge balance, the charge balance structure continues under the gate pad metal and any other control pads.

Exemplary ESD protection circuits are in the 64A to 64D wherein the main device, the gate of which is protected by the above-described diode structures, may be any of the power devices described herein using any of the charge balance techniques or other techniques. 64A shows a simplified diagram for asymmetric isolated poly-diode ESD protection, whereas 64B shows a normal back-to-back isolated poly-diode ESD protection circuit. The in 64C shown ESD protection circuit uses an NPN transistor for a BV _cer -Snap-back. The subscript "cer" in BV _cer refers to a bipolar transistor having a reverse biased collector-emitter junction in which a connection to the base uses a resistor to drive the base current. A low resistance causes most of the emitter current to be removed by the base, preventing the emitter-base junction from turning on, that is, injecting minority carriers back into the collector. The on state can be set by the resistance value. When charge carriers are injected back into the collector, the voltage to be carried between the emitter and the collector can be reduced - a phenomenon called "snap-back". The current at which the BV _cer snap-back is triggered can be set by adjusting the value of the base-emitter resistor R _BE . 64D shows an ESD protection circuit using a silicon controlled rectifier or SCR and a diode as shown. By using a gate-to-cathode short circuit structure, the tripping current can be controlled. The diode breakdown voltage can be used to shift the voltage at which the SCR switches. The monolithic diode structure as described above can be applied to any of these and other ESD protection circuits.

In some power applications, an important performance characteristic of a power switching device is its equivalent series resistance (ESR), which is a measure of the impedance of the switching port or gate. For example, in low-speed synchronous actuators using power MOSFETs, a lower ESR helps reduce switching losses. In the case of trench gate MOSFETs, their gate ESR is largely determined by the dimensions of the polysilicon filled trenches. The length of the gate trenches may be limited, for example, by package constraints, such as the minimum size of the wire bonding pad. It is known that depositing a silicide film on polysilicon lowers the resistance of the gate. However, implementing a siliconized polys in trench MOSFETs presents a number of challenges. In typical planar, discrete MOS structures, the gate poly can be silicated after the junctions have been implanted and driven into their respective depths. For trench gate devices in which the gate poly is embedded, the application of a silicide becomes more complicated. The use of a conventional silicide limits the maximum temperature that a wafer can be subjected to post-silicide treatment to approximately less than 900 ° C. This represents a significant limitation on the stage of the manufacturing process when forming diffusion regions such as sources, drains, and wells. The most typical metal used for silicides is titanium. Other metals such as tungsten, tantalum, cobalt, and platinum may also be used, allowing post-silicide treatment with a higher heat budget, which in turn provides more processing latitude. The gate ESR can also be reduced by various layout techniques.

Various embodiments for forming charge balance and lower ESR power switching devices are described below. In an in 65 embodiment shown includes a process 6500 forming trenches with a lower electrode formed at a lower portion of the trench for shielding and / or charge balancing purposes (step 6502 ). This is followed by deposition and etching of an IPD layer (step 6504 ). The IPD layer can be formed by known processes. Alternatively, any of the above may be used in conjunction with 45 to 50 described processes for forming the IPD layer. Next, an upper electrode or a gate poly will be used, using known processes 6506 deposited and etched. This is followed by implanting and driving in the well and source regions (step 6508 ). After step 6508 silicide is going to step on the gate poly 6510 applied. This is followed by deposition and planarization of a dielectric at step 6512 , In a modification of this process will step 6512 in which the dielectric field is deposited and planarized is performed first, and then contact holes are opened to reach the source / body and the gate, after which silicide contacts are formed. Both of these embodiments are based on activating the strong body implantation area by annealing at low temperature, which is lower than the silicide film transition point.

In another embodiment, the poly gate is replaced by a metal gate. According to this embodiment, the metal gate is formed by depositing z. For example, Ti is formed using a collimated source to improve fillability in a trench structure. After the metal gate has been deposited and once the junctions have been implanted and driven in, selections for dielectrics include HDP and TEOS to isolate the gate from the source / body contacts. In alternative embodiments, a damascene or dual damascene approach with various choices of metal from aluminum to copper capping metals is used to form the gate terminal.

The layout of the gate conductor may also affect the gate ESR and the overall switching speed of the device.

Although the above is a complete description of the preferred embodiments of the invention, many alternatives, modifications, and equivalents are possible. For example, many of the charge balance techniques are described herein in the context of a MOSFET, and more particularly, a trench-gate MOSFET. Those skilled in the art will recognize that the same techniques can be applied to other types of devices including IGBTs, thyristors, diodes or planar MOSFETs, as well as lateral devices. For these and other reasons, therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims (11)

Semiconductor device ( 3300 ) with: - a drift region ( 3306 ) of a first conductivity type, - a well region (p) which extends above the drift region ( 3306 ) and having a second conductivity type opposite to the first conductivity type, - a plurality of active trenches ( 3302 ) extending through the well region (p) and into the drift region ( 3306 ) within each of the plurality of active trenches ( 3302 ) are formed: - a first conductive gate electrode ( 3310 ) disposed along and insulated from a first trench sidewall, - a second conductive gate electrode (FIG. 3310 ) disposed along and isolated from a second trench sidewall, a conductive shield electrode (Fig. 3311 ), which between the first ( 3310 ) and the second ( 3310 ) conductive gate electrode is arranged, wherein the shielding electrode ( 3311 ) compared to the first ( 3310 ) and the second ( 3310 ) Gate electrode is insulated and dig deeper into the trench ( 3302 ) extends as the first ( 3310 ) and the second ( 3310 Gate electrode, wherein the conductive shielding poly extends vertically to the silicon surface along the height of the trench, to above a height of the first and second conductive gate electrodes, source regions (n ⁺ ) of the first conductivity type, within the well region (p) and adjacent to the plurality of active trenches (p) 3302 ), and - a circumferential trench ( 2603a . 3213 ) that at least partially surrounds the plurality of active trenches ( 3302 ) so that at least some of the Trenches ( 3302 ) of the plurality of active trenches ( 3302 ) perpendicular to the circumferential trench ( 2603a . 3213 ), wherein the conductive shielding electrode ( 3311 ) is electrically conductively connected to the source metallization, wherein the circumferential trench ( 2603a . 3213 ) with a dielectric ( 2605a ) and with conductive material ( 2607a ), wherein the first conductive gate electrode ( 3310 ) and the second conductive gate electrode ( 3310 ) along a third dimension within the plurality of active trenches ( 3302 ) are connected. A semiconductor device according to claim 1, wherein the peripheral trench ( 3213 ) does not connect to the plurality of active trenches. The semiconductor device of claim 1, wherein the circumferential trench connects to the plurality of active trenches. A semiconductor device according to claim 1, wherein the peripheral trench ( 2603a ) substantially with a layer of a conductive material ( 2607a ), which is isolated from the trench sidewalls ( 2605a ). The semiconductor device of claim 1, wherein the first distance is about half the second distance. Semiconductor device according to Claim 1, having a termination trench ( 2603a ) on the outer periphery of the plurality of active trenches ( 2602 ), the termination trench ( 2603a ) substantially with a conductive material ( 2607a ), which is isolated from the trench sidewalls ( 2605a ). A semiconductor device according to claim 6, wherein a mesa formed between the termination trench and an active trench adjacent to the termination trench defines a second conductivity type region ( 2604 ) but has no source areas. A semiconductor device according to claim 1, wherein said well region ( 2604 ) is contacted via a body trench etched into a central region of a mesas between two adjacent active trenches. The semiconductor device of claim 8, wherein the body trench extends deeper into the well region than the source regions. A semiconductor device according to claim 8, wherein the body trench ( 418 ) extends deeper than the tub area. A semiconductor device according to claim 8, having a region of high dopant concentration ( 419 ) of the second conductivity type extending at least below the body trench ( 418 ) is located.

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