CN101180737A - Power semiconductor device and method of manufacture - Google Patents

Abstract

The present invention provides various embodiments of improved power devices for use in power electronics applications, methods of manufacturing the same, packages, and circuits incorporating the same. One aspect of the present invention combines a number of charge balancing techniques with other techniques for reducing parasitic capacitance to achieve different embodiments of power devices with improved voltage performance, higher switching speed, lower on-resistance. Another aspect of the present invention provides an improved termination structure for low, medium and high voltage devices. According to other aspects of the invention, improved methods of power device fabrication are provided. Improvements to specific process steps such as forming trenches, forming an intra-trench dielectric layer, forming mesas, and processes for reducing the thickness of a substrate are shown. According to yet another aspect of the invention, a charge balance power device incorporates temperature and current sensing elements, such as diodes, on the same die. Other aspects of the invention improve Equivalent Series Resistance (ESR) of the power device, incorporate additional circuitry on the same chip as the power device, and provide packaging improvements for charge balanced power devices.

Description

Power semiconductor device and manufacturing method

Cross References to Related Applications

This application is a continuation-in-part of the following commonly assigned U.S. patent application:

10/155,554 by Mo et al. (Attorney Docket No. 18865-17-2/17732-7226.001), entitled "Field Effect Transistor and Methods of its Manufacture," May 24, 2002;

Sapp's No. 10,209,110 (Attorney Docket No. 18865-98/17732-55270), entitled "Dual Trench Power MOSFET," July 30, 2002;

Kocon's No. 09/981,583 (Attorney Docket No. 18865-90/17732-51620), entitled "Semiconductor Structure with Improved Smaller Forward Loss and Higher Blocking Capability," dated October 17, 2001;

10/640,742 to Kocon et al. (Attorney Docket No. 90065.000241/17732-66550), entitled "Improved MOS Gating Method for Reduced Miller Capacitance and Switching Losses," August 14, 2003;

Marchant's No. 09/774,780 (Attorney Docket No. 18865-69/17732-26400), entitled "Field Effect Transistor Having a Lateral Depletion Structure," January 30, 2001;

10/200,056 to Sapp et al. (Attorney Docket No. 18865-97/17732-55280), entitled "Vertical Change Control Semiconductor Device with Low Output Capacitance," July 18, 2002;

10/288,982 to Kocon et al. (Attorney Docket No. 18865-117/17732-66560), entitled "Drift Region Higher Blocking Lower Forward Voltage Drop Semiconductor Structure," November 5, 2002;

Herrick's 10/442,670 (Attorney Docket No. 18865-131/17732-66850), entitled "Structure and Method for Forming a Trench MOSFET Having Self-Aligned Features," May 20, 2003;

No. 10/315,719 of Yedinak (Attorney Docket No. 90065.051802/17732-56400), entitled "Method of Isolating the CurrentSense on P1anar or Trench Stripe Power Devices while Maintaining a Continuous Stripe Cell," December 10, 2002

10/222,481 (Attorney Docket No. 18865-91-1/17732-51430) of Elbanhawy, entitled "Methods and Circuit for Reducing Losses in DC-DC Converters," August 16, 2002;

Joshi's No. 10/235,249 (Attorney Docket No. 18865-71-1/17732-26390-3), entitled "Unmolded Package for a Semiconductor device," dated September 4, 2002; and

10/607,633 by Joshi et al. (Attorney Docket No. 18865-42-1/17732-13420), entitled "Flip Chip in Leaded Molded Package and Method of Manufacturing Thereof," June 27, 2003;

And claim priority to the following provisionally filed U.S. patent application:

60/506,194 to Wilson et al. (Attorney Docket No. 18865-135/17732-66940), entitled "High Voltage Shielded Trench Gate LDMOS," September 26, 2003; and

No. 60/588,845 (Attorney Docket No. 18865-164/17732-67010), entitled "Accumulation Device with Charge Balance Structure and Method of Forming the Same," July 15, 2004.

The entire contents of the applications listed above are hereby incorporated by reference.

technical field

The present invention relates generally to semiconductor devices and, in particular, to various embodiments relating to improved power semiconductor devices (eg, transistors and diodes) and methods of manufacturing the same, including packages and circuits incorporating power semiconductor devices.

Background technique

A key component in a power semiconductor device is a solid state switch. From ignition control of battery-operated consumer electronics in automotive applications to power conversion in industrial applications, power switches that best meet specific application needs are required. Solid state electronic switches including power metal oxide semiconductor field effect transistors (power MOSFETs), insulated gate bipolar transistors (IGBTs) and various types of thyristors continue to be developed to meet this need. For example, in the case of power MOSFETs, double-diffused structures with lateral channels (DMOS) have been developed (e.g., US Patent No. 4,682,405 to Blanchard et al.), trench-gate (trenched gate) structures (e.g., U.S. Patent No. 6,429,481 to Mo et al.), and various techniques for charge balancing in the drift region of transistors (e.g., U.S. Patent No. 4,941,026 to Temple, No. 5,216,275 to Chen, and 6,081,009 to Neilson) to meet the needs of different and often competing properties.

Some of the performance characteristics used to define a power switch are its on-resistance, breakdown voltage and switching speed. Depending on the requirements of a particular application, different emphasis is placed on each of these performance criteria. For example, for power applications greater than about 300-400 volts, IGBTs exhibit inherently lower on-resistance compared to power MOSFETs, but have slower switching speeds due to their slower turn-off characteristics. Thus, for applications greater than 400 volts with low switching frequencies requiring low on-resistance, IGBTs are the preferred switch, while power MOSFETs are often the device of choice for relatively higher frequency applications.

If the frequency requirements for a given application dictate the type of switch used, then the voltage requirements determine the composition of the specific switch. For example, in the case of power MOSFETs, maintaining a low _RDSon while improving transistor voltage performance is difficult because of the proportional relationship between the drain-source on-resistance _RDSon and the breakdown voltage. Various charge-balancing structures in the drift region of transistors have been developed to address this difficulty, with varying degrees of success.

Device performance parameters are also affected by the manufacturing process and die packaging. Various efforts have been made to address some of these problems by developing various improved processes and packaging techniques.

Whether in ultra-portable consumer electronics devices or routers and hubs in communication systems, the variety of applications for power switches continues to grow as the electronics industry expands. Therefore, power switches are semiconductor devices with high development potential.

Contents of the invention

The present invention provides various embodiments of power devices, methods of manufacturing the same, packages, and circuits incorporating power devices for various power electronics applications. In summary, one aspect of the present invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to achieve various aspects of power devices with improved voltage performance, higher switching speed, and lower on-resistance. kind of embodiment. Another aspect of the present invention provides improved termination structures for low, medium and high voltage devices. According to other aspects of the invention, improved methods of power device fabrication are provided. Improvements to specific processing steps are provided by various embodiments of the present invention, for example, formation of trenches, formation of dielectric layers within trenches, formation of mesa structures, processes for reducing substrate thickness . According to another aspect of the invention, a charge balanced power device incorporates temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve the equivalent series resistance (ESR), or gate resistance, of power devices, incorporate additional circuitry on the same die as the power devices, and provide packaging improvements for charge balancing power devices.

These and other aspects of the invention will be described in detail below with reference to the accompanying drawings.

Description of drawings

Figure 1 shows a cross-sectional view of a portion of an exemplary n-type trench (trench) power MOSFET;

Figure 2A shows an exemplary embodiment of a dual trench power MOSFET;

Figure 2B shows an exemplary embodiment of a planar gate MOSFET with a source shielding trench structure;

Figure 3A shows a portion of an exemplary embodiment of a shielded gate trench power MOSFET;

3B shows an alternative embodiment of a shielded gate trench power MOSFET combining the dual trench structure of FIG. 2A and the shielded gate structure of FIG. 3A;

4A is a simplified partial diagram of an exemplary embodiment of a dual-gate trench power MOSFET;

Figure 4B shows an exemplary power MOSFET incorporating a planar double gate structure and trench electrodes for vertical charge control;

Figure 4C shows an exemplary embodiment of a power MOSFET combining dual gate and shielded gate technologies within the same trench;

4D and 4E are cross-sectional views of alternative embodiments of power MOSFETs with deep body structures;

FIG. 4F and FIG. 4G show the influence of the trench deep body structure on the potential line distribution close to the gate electrode in the power MOSFET;

5A, 5B and 5C are cross-sectional views illustrating portions of exemplary power MOSFETs with various vertical charge balance structures;

6 shows a simplified cross-sectional view of a power MOSFET incorporating an exemplary vertical charge control structure and shielded gate structure;

7 shows a simplified cross-sectional view of another power MOSFET incorporating an exemplary vertical charge control structure and a double gate structure;

Figure 8 shows an example of a shielded gate power MOSFET with vertical charge control structure and integrated Schottky diode;

9A, 9B and 9C illustrate various exemplary embodiments of power MOSFETs with integrated Schottky diodes;

9D, 9E and 9F illustrate exemplary layout variations for interspersing Schottky diode cells within an active cell array of power MOSFETs;

Figure 10 shows a simplified cross-sectional view of an exemplary trench power MOSFET with a buried diode (buried diode, also known as an embedded diode) charge balance structure;

Figures 11 and 12 illustrate exemplary embodiments of power MOSFETs combining shielded gate and double gate structures, respectively, with buried diode charge balancing;

Figure 13 is a simplified cross-sectional view of an exemplary planar power MOSFET incorporating buried diode charge balancing techniques and integrated Schottky diodes;

Figure 14 shows a simplified embodiment of an exemplary accumulation-mode power transistor with alternating conduction regions arranged in parallel with the current flow;

Figure 15 is a simplified diagram of another accumulation mode device with trench electrodes for charge expansion;

Figure 16 is a simplified diagram of an exemplary dual trench accumulation mode device;

Figures 17 and 18 illustrate other simplified embodiments of exemplary accumulation mode devices of trenches filled with dielectric material with exterior liners of opposite polarity;

Figure 19 is another simplified embodiment of an accumulation mode device using one or more buried diodes;

20 is a simplified isometric view of an exemplary accumulation mode transistor including heavily doped opposite polarity regions along the surface of silicon;

Figure 21 shows a simplified example of a super-junction (super-junction, also known as a super-junction) power MOSFET with alternating regions of opposite polarity within the voltage sustaining layer;

Figure 22 shows an exemplary embodiment of a super junction power MOSFET with non-uniformly separated islands of opposite polarity in the vertical direction within the voltage sustaining layer;

FIG. 23 and FIG. 24 illustrate exemplary embodiments of super junction power MOSFETs with double gate and shielded gate structures, respectively;

Figure 25A shows a top view of the active and terminal trench layout of a trench transistor;

25B to 25F show simplified layout diagrams of alternative embodiments of trench termination structures;

26A-26C are cross-sectional views of exemplary trench termination structures;

FIG. 27 illustrates an exemplary device having a termination trench with a large radius of curvature;

28A to 28D are cross-sectional views of termination regions with silicon pillar (silicon pillar) charge balance structures;

29A to 29C are cross-sectional views of exemplary embodiments of ultra-high voltage devices using super junction technology;

Figure 30A shows an example of edge contacting (edge contacting) of a trench device;

30B to 30F illustrate exemplary process steps in forming an edge contact structure for a trench device;

FIG. 31A is an example of an active area contact structure of multiple buried polysilicon layers (poly layer);

31B to 31M illustrate an exemplary process flow for forming an active region shielding contact structure for a trench;

Figure 31N is a cross-sectional view of an alternative embodiment of an active area shield contact structure;

32A and 32B are layout views of exemplary trench devices with active region shielding contact structures;

32C to 32D are simplified layout diagrams of two embodiments for enabling access to trench perimeters in trench devices with interrupted trench structures;

Figure 33A is an alternative embodiment of a trenched shield polysilicon layer for contacting the active region;

33B to 33M illustrate an example of a process flow for contacting an active area mask structure of the type shown in FIG. 33A;

Figure 34 shows an epi layer with a spacer or buffer (barrier) layer to reduce the thickness of the epi drift region;

Figure 35 shows an alternative embodiment of a device with a barrier layer;

Figure 36 shows the barrier layer used at the deep body-epitaxial junction in order to minimize the thickness of the epitaxial layer;

Figure 37 is a simplified example of a well-drift region junction of a transistor using a diffusion barrier layer;

38A to 38D illustrate a simplified process for an example of a self-aligned epi-well trench device with buried electrodes;

39A-39B illustrate an exemplary process flow for angled well implantation;

40A to 40E show an example of a self-aligned epitaxial well process;

40R to 40U illustrate a method of reducing the thickness of a substrate;

Figure 41 shows an example of a process flow using a chemical process as the final thinning step;

42A to 42F show an example of an improved etching process;

43A and 43B illustrate an embodiment of a trench etch process that eliminates the bird's beak problem;

Figures 44A and 44B illustrate an optional etch process;

45A to 45C illustrate a process for forming an improved inter-poly dielectric layer;

Figures 46A, 46B and 46C illustrate alternative methods of forming an IPD layer;

47A and 47B are cross-sectional views of another method of forming a high-quality interpolysilicon dielectric layer;

48 and 49A to 49D illustrate other embodiments for forming an improved IPD layer;

Figure 50A shows an anisotropic plasma etch process for IPD planarization;

Figure 50B shows an alternative IPD planarization method using a chemical mechanical process;

Figure 51 is a flowchart of an exemplary method for controlling the rate of oxidation;

Figure 52 shows an improved method for forming a thick oxide layer at the bottom of the trench using a low pressure chemical vapor deposition process;

53 is an exemplary flow diagram for forming a thick oxide layer at the bottom of a trench using a directional Tetraethoxyorthsilicate process;

Figures 54 and 55 illustrate another embodiment for forming a thick bottom oxide layer;

56 to 59 illustrate another process for forming a thick dielectric layer at the bottom of the trench;

Figure 60 is a simplified diagram of a MOSFET with a current sensing device;

Figure 61A is an example of a charge balance MOSFET with a planar gate structure and independent current sensing structure;

Figure 61B shows an example of integrating a current sensing device with a trench MOSFET;

62A to 62C show alternative embodiments of MOSFETs with series temperature sensing diodes;

Figures 63A and 63B illustrate alternative embodiments of MOSFETs with ESD protection;

64A to 64D illustrate examples of ESD protection circuits;

Figure 65 illustrates an exemplary process for forming a charge-balanced power device with low ESR;

66A and 66B illustrate layout techniques to reduce ESR;

Figure 67 shows a DC-DC converter circuit using power switches;

Figure 68 shows another DC-DC converter circuit using power switches;

Figure 69 shows an exemplary drive circuit for a dual gate MOSFET;

Figure 70A shows an alternative embodiment with separate drive gate electrodes;

Figure 70B shows a timing diagram illustrating the operation of the circuit of Figure 70A;

Figure 71 is a simplified cross-sectional view of a molded package; and

Figure 72 is a simplified cross-sectional view of an unmolded package.

Detailed ways

The power switch can be realized by any one of power MOSFET, IGBT, various types of thyristor, etc. For purposes of illustration, many of the new technologies presented in this paper are described in the context of power MOSFETs. However, it should be understood that the various embodiments of the invention described herein are not limited to MOSFETs, but may be applied to many other types of power switching technologies including, for example, IGBTs, other types of bipolar switches, various types of thyristors and diodes. Further, various embodiments of the invention are shown including specific p and n-type regions for purposes of illustration. Those skilled in the art should understand that the techniques herein can also be applied to devices in which the conductivity of each region is opposite.

Referring to FIG. 1 , a partial cross-sectional view of an exemplary n-type trench power MOSFET 100 is shown. As with other views described herein, it should be understood that the relative dimensions and sizes of the various elements and components shown in the figures do not directly reflect actual dimensions and are for illustrative purposes only. Trench MOSFET 100 includes a gate electrode formed within a trench 102 extending from the upper surface of the substrate through a p-type well or body region 104 and terminating at an n-type drift or epitaxial region 106. middle. A thin dielectric layer 108 is disposed along the trench 102, and the trench 102 is substantially filled with a conductive material 110 (eg, doped polysilicon). An n-type source region 112 is formed in the body region 104 adjacent to the trench 102 . The drain terminal of MOSFET 100 is formed on the rear side of the substrate connected to heavily doped n+ substrate region 114. The structure shown in Figure 1 is repeated many times on a common substrate made of, for example, silicon to form an array of transistors. The array can be configured in various cellular or striped configurations well known in the art. When the transistor is turned on, a conductive channel is formed between the source region 112 and the drift region 106 along the sidewalls of the gate trench 102 .

Due to its vertical gate structure, MOSFET 100 is capable of high packing density when compared to planar gate devices, and the higher packing density enables relatively low on-resistance. To improve the breakdown voltage performance of such transistors, p+ heavily doped body region 118 is formed within p-well 104 such that an abrupt junction is formed at the interface between p+ heavily doped body region 118 and p-well 104 . By controlling the depth of the p+ heavily doped body region 118 relative to the depth of the trench and the depth of the well, the electric field generated when a voltage is applied to the transistor disappears from the trench. This increases the avalanche current handling capability of the transistor. Variations on such improved structures and processes for forming transistors, particularly abrupt junctions, are described in detail in Mo et al., commonly owned US Patent No. 6,429,481, the entire contents of which are incorporated herein by reference.

Although vertical trench MOSFET 100 exhibits good on-resistance and improved durability, it has relatively high input capacitance. The input capacitance of trench MOSFET 100 includes two parts: gate-source capacitance C _gs and gate-drain capacitance C _gd . The gate-source capacitance C _gs results from the superposition between the gate conductive material 110 and the source region 112 near the top of the trench. Capacitance formed between the gate and the reverse channel in the body can also increase C _gs because in typical power switching applications the body and source electrodes of the transistor are shorted together. The gate-drain capacitance C _gd results from the superposition between the gate conductive material 110 at the bottom of each trench and the drift region 106 connected to the drain. The gate-drain capacitance C _gd , or Miller capacitance, limits the V _DS transition time of the transistor. Therefore, higher C _gs and C _gd lead to considerable switching losses. These switching losses become increasingly large as power management applications approach higher switching frequencies.

One way to reduce the gate-source capacitance C _gs is to reduce the channel length of the transistor. A shorter channel length directly reduces the gate-channel component of _Cgs . Shorter channel lengths also scale well with R _DSon and enable the same amount of device current to be obtained with fewer gate trenches. This reduces both C _gs and C _gd by reducing the gate-source and gate-drain stacks. However, the shorter channel length makes the device fragile leading to punch through when a depletion layer is formed due to the reverse biased body-drain junction deep into the body region and close to the source region. Reducing the doping concentration of the drift region maintains a wider depletion layer with the undesired effect of increasing the transistor on-resistance _RDSon .

Modifications to the transistor structure using additional "shielding" trenches laterally separated from the gate trench not only reduce the channel length, but also effectively address the aforementioned drawbacks. Referring to FIG. 2A , an exemplary embodiment of a dual trench MOSFET 200 is shown. The term "dual trench" refers to a transistor having two different types of trenches as opposed to the total number of similar trenches. In addition to common structural features with MOSFET 100 of FIG. 1 , dual trench MOSFET 200 includes shielding trenches 220 sandwiched between adjacent gate trenches 202. In the exemplary embodiment shown in FIG. 2A , shielding trench 220 extends from the surface through p+ region 218 , body region 204 into drift region 206 , well below the depth of gate trench 202 . A dielectric material 222 is disposed along the trench 220 and the trench 220 is substantially filled with a conductive material 224 such as doped polysilicon. Metal layer 216 electrically connects conductive material 224 within trench 220 to n+ source region 212 and heavily doped p+ body region 218 . Therefore, in this embodiment, trench 220 may be referred to as a source shielding trench. Examples of this type of dual trench MOSFET, its fabrication process, and its circuit applications are described in detail in commonly assigned U.S. Patent Application Serial No. 10/209,110, entitled "Dual Trench Power MOSFET," by Steven Sapp, the entire contents of which are incorporated in Here for reference.

The effect of the deeper source shielding trench 220 is to make the depletion layer formed due to the reverse biased body-drain junction deeper into the drift region 206 . Therefore, a wider depletion region may result in no increase of the electric field. This allows the drift region to be more heavily doped without lowering the breakdown voltage. A more heavily doped drift region reduces the on-resistance of the transistor. Furthermore, the reduced electric field near the body-drain junction results in a substantial reduction in the channel length, further reducing the transistor's on-resistance, and substantially reducing the gate-source capacitance C _gs . Furthermore, the dual-trench MOSFET enables the same amount of transistor current to be obtained with fewer gate trenches than the MOSFET in Figure 1. This significantly reduces gate-source and gate-drain stack capacitances. Note that in the exemplary embodiment shown in FIG. 2A, the gate trench conductive layer 210 is buried in the trench eliminating the need for an interlayer dielectric dome (IDDome) in the The upper side of trench 102 in MOSFET 100 shown in FIG. 1 . Also, the use of the source shielding trenches illustrated here is not limited to trench gate MOSFETs, and the same advantages can be obtained when the source shielding trenches are used in planar MOSFETs in which gates are formed horizontally on the upper surface of the substrate. An exemplary embodiment of a planar gate MOSFET with a source shielding trench structure is shown in FIG. 2B .

To further reduce the input capacitance, additional structural improvements can be made, focusing on reducing the gate-drain capacitance C _gd . As mentioned above, the gate-drain capacitance C _gd is generated by the overlap between the gate and the drain region at the bottom of the trench. One way to reduce this capacitance is to increase the thickness of the gate dielectric layer at the bottom of the trench. Referring back to FIG. 2A, it is shown that the gate trench 202 has a thicker dielectric layer at the bottom of the trench where there is overlap with the drift region 206 (transistor drain terminal) compared to the dielectric layer along the sidewalls of the gate trench. Electrical layer 226. This reduces the gate-drain capacitance C _gd without reducing the forward conduction of the transistor. Growing a thicker dielectric layer at the bottom of the gate trench can be achieved in a number of ways. An exemplary process for producing thicker dielectric layers is described in commonly-owned US Patent No. 6,437,386 to Hurst et al., which is hereby incorporated by reference in its entirety. Other processes for forming a thick dielectric layer at the bottom of the trench are further described below with reference to FIGS. 56 to 59 . Another approach to reducing gate-drain capacitance is a second dielectric core centrally located within the trench extending upward from the dielectric liner on the trench base. In one embodiment, the second dielectric core may extend upward from various directions to contact the dielectric layer above the trench conductive material 210 . Examples of this embodiment and modifications thereto are described in detail in Shenoy's co-owned US Patent No. 6,573,560.

Another technique for reducing the gate-drain capacitance C _gd involves shielding the gate with one or more bias electrodes. According to this embodiment, one or more electrodes are formed within the gate trench and beneath the conductive material forming the gate electrode to shield the gate from the drift region, thereby substantially reducing the gate-drain overlap capacitance. Referring to FIG. 3A , a portion of an exemplary embodiment of a shielded gate trench MOSFET 300A is shown. In this example, trench 302 in MOSFET 300A includes gate electrode 310 and two additional electrodes 311a and 311b below gate electrode 310 . Electrodes 311a and 311b shield gate electrode 310 from any substantial overlap with drift region 306, thereby virtually eliminating gate-drain stack capacitance. Shield electrodes 311a and 311b can be independently biased at an optimal potential. In one embodiment, one of the shield electrodes 311a and 311b may be biased at the same potential as the source terminal. Similar to the double-trench structure, the biasing of the shield electrode can also help to widen the depletion region formed at the body-drain junction, further reducing C _gd . It should be appreciated that the number of shield electrodes 311 may vary depending on the switching application, particularly the voltage requirements of the application. Similarly, the size of the shield electrode in a given trench can also vary. For example, shield electrode 311a may be larger than shield electrode 311b. In one embodiment, the smallest shield electrode is closest to the bottom of the trench, and the remaining shield electrodes gradually increase in size as they get closer to the gate electrode. The independently biased electrodes in the trench can also be used for vertical charge control to improve small forward voltage loss and high blocking capability. This aspect of transistor structures, which will be described further below in connection with high voltage devices, is also described in detail in Kocon's commonly assigned U.S. Patent Application Serial No. 09/981,583, entitled "Semiconductor Structure with Improved Smaller Forward Loss and Higher Blocking Capability," Its entire contents are hereby incorporated by reference.

FIG. 3B shows an alternative embodiment of a shielded gate trench MOSFET 300B combining the dual trench structure of FIG. 2A and the shielded gate structure of FIG. 3A. In the exemplary embodiment shown in FIG. 3B , gate trench 301 includes gate electrode 310 over shield electrode 311 , similar to trench 302 of MOSFET 300A. However, MOSFET 300B includes non-gate trenches 301 which may be deeper than gate trenches 302 for vertical charge control purposes. While the charge control trench 301 may have a single layer of conductive material (e.g., polysilicon) on top of the trench connected to the source metal, as shown in FIG. 2A, the embodiment in FIG. 3B uses multiple stacked independently biasable polysilicon electrode 313 . The number of electrodes 313 stacked in the trench can be changed according to application requirements, and can also be the size of the electrodes 313 shown in FIG. 3B. The electrodes can be independently biased or electrically connected together. The number of charge control trenches within the device also depends on the application.

Yet another technique for improving power MOSFET switching speed reduces the gate-drain capacitance C _gd by using a double gate structure. According to this embodiment, the gate structure inside the trench is divided into two parts: the first part is used to perform the traditional gate function of receiving the switching signal, the second part shields the first gate part from the drift (drain) region, and can be independently biased. This significantly reduces the gate-drain capacitance of the MOSFET. FIG. 4A is a simplified partial diagram of an exemplary embodiment of a dual-gate trench MOSFET 400A. As shown in FIG. 4A, the gate of MOSFET 400A has two sections G1 and G2. Unlike the shield electrodes (311a and 311b) in MOSFET 300A of FIG. 3A, the conductive material forming G2 in MOSFET 400A has a region 401 overlapping the channel and thus serves as a gate terminal. However, this secondary gate terminal G2 is biased independently of the main gate terminal G1 and does not receive the same signal that drives the switching transistor. Conversely, in one embodiment, G2 is biased at a constant potential just greater than the MOSFET threshold voltage to invert the channel in superposition region 401 . This will ensure that a continuous channel is formed when switching from the sub-gate G2 to the main gate G1. Furthermore, because the potential at G2 is higher than the source potential, C _gd is reduced, and the charge transfer from the drift region to the sub-gate G2 also contributes to the reduction of C _gd . In another embodiment, instead of a constant potential, the sub-gate G2 may be biased to a potential higher than the threshold voltage just before the switching action. In other embodiments, the potential at G2 can be varied and optimally adjusted to minimize any marginal portion of the gate-drain capacitance _Cgd . The double gate structure can be used in MOSFETs with planar gate structures and other types of trench gate power devices including IGBTs and the like. Changes to double-gate trench MOS gate devices and the process used to fabricate such devices are described in commonly assigned U.S. Patent Application Serial No. 10/640,742 to Kocon et al., entitled "Improved MOS Gating Method for Reduced Miller Capacitance and Switching Losses" is described in detail in No. 2, the entire contents of which are hereby incorporated by reference.

Another embodiment of an improved power MOSFET is shown in FIG. 4B, where an exemplary MOSFET 400B incorporates a planar gate structure and a shield electrode for vertical charge control. Primary gate terminal G1 and secondary gate terminal G2 function in a similar manner to the trenched double gate structure of FIG. 4A , with deep trenches 420 providing electrodes in the drift region to spread charge and increase the breakdown voltage of the device. In the illustrated embodiment, shield or sub-gate G2 overlies the upper portion of main gate G1 and extends over p-well 404 and drift region 406 . In an alternative embodiment, the main gate G1 extends over the shield/sub-gate G2.

The various techniques described thus far, such as gate shielding and trench electrodes for vertical charge control, can be combined to obtain power devices (including lateral and vertical MOSFETs, IGBTs, diodes, etc.) with optimized performance characteristics for a given application. For example, the trenched double gate structure shown in Figure 4A can be conveniently combined with a vertical charge control trench structure of the type shown in Figure 3B or 4B. Such a device includes an active trench with a double-gate structure as shown in FIG. 4A , and consists essentially of a single layer of conductive material (such as the trench in FIG. 4B ) or multiple stacked conductive electrodes (such as the trench in FIG. 3B ). Trench 301) fills the deeper charge control trench. For lateral devices where the drain terminal is on the same surface of the substrate as the source terminal (ie, current flows laterally), instead of being stacked in vertical trenches, the charge control electrodes are arranged laterally to form a field plate. The orientation of the charge control electrodes is generally parallel to the direction of current flow in the drift region.

In one embodiment, dual gate and shielded gate technologies are combined within the same trench to increase switching speed and blocking voltage. FIG. 4C shows MOSFET 400C in which trench 402C includes main gate G1, sub-gate G2 and shielding layer 411 stacked in a single trench as shown. Trench 402C can be made as deep as possible and include as many shielding layers 411 as the application requires. Using the same trenches for charge balancing and shielding electrodes enables higher densities because it eliminates the need for two trenches and combines them into one. It also enables more current scaling and improves the on-resistance of the device.

The devices described thus far use a combination of shielded gate, double gate, and other techniques to reduce parasitic capacitance. However, these techniques cannot fully minimize the gate-drain capacitance C _gd due to fringing effects. Referring to FIG. 4D , a partial cross-sectional view of an exemplary embodiment of a MOSFET 400D having a deep body design is shown. According to this embodiment, the body structure is formed by trenches 418, wherein the trenches 418 are etched through the center of the mesa formed between the gate trenches 402 and extend to the same level as the gate trenches 402. deep or deeper than the position of the gate trench 402 . Body trenches 418 are filled with source metal as shown. The source metal layer may comprise a thin refractory metal on a metal diffusion boundary (not shown). In this embodiment, the body structure further includes a p+ body implant junction 419 substantially surrounding the body trench 418 . The p+ injection junction 419 enables additional shielding to alter the potential distribution within the device, especially near the gate electrode. In an alternative embodiment shown in FIG. 4E , for example, body trenches 418 are substantially filled with epitaxial material using, for example, selective epitaxial growth (SEG) deposition. Optionally, body trench 418 is substantially filled with doped polysilicon. In either of these two embodiments, instead of implanting the p+ shielding junction 419, dopants are diffused from the filled body into the silicon to form the p+ shielding junction 419 in a subsequent temperature process. Many variations and formations to the trench body structure are described in commonly assigned US Patent Nos. 6,437,399 and 6,110,799 to Huang, the entire contents of which are hereby incorporated by reference.

In the embodiment shown in FIGS. 4D and 4E , the distance L between the gate trench 402 and the body trench 418 and the relative depths of the two trenches are controlled to minimize edge gate-drain capacitance. In embodiments using SEG or polysilicon filled body trenches, the spacing between the outer edge of layer 419 and the gate trench walls can be tuned by varying the doping concentration of the polysilicon within the SEG or body trenches 418 . 4F and 4G illustrate the effect of the deep body of the trench on the distribution of potential lines within the device close to the gate electrode. For illustration purposes, FIGS. 4F and 4G use a MOSFET with a shielded gate structure. Figure 4F shows the potential lines for a reverse biased shielded gate MOSFET 400F with trench deep body 418, and Figure 4G shows the potential lines for a reverse biased shielded gate MOSFET 400G with a shallow body structure. The contour lines in each device show the potential distribution within the device when reverse biased (eg, blocking off-state). The white line shows the well junction and also defines the bottom of the channel next to the gate electrode. As can be seen from the figure, there is a lower potential and a lower electric field disposed on the channel and around the gate electrode of the trench deep body MOSFET 400F of FIG. 4F. This reduced potential can reduce the channel length, thereby reducing the overall gate charge of the device. For example, the depth of the gate trenches 402 can be reduced to less than, eg, 0.5um, and can be made shallower than the body trenches 418, with a pitch L of about 0.5um or less. In an exemplary embodiment, the distance L is less than 0.3um. Other advantages of this embodiment are reduced gate-drain charge Q _gd and Miller capacitance C _gd . The lower the value of these parameters, the faster the device is able to convert. These improvements are achieved by reducing the potential that appears immediately adjacent to the gate electrode. The improved structure has a very low potential to be switched and a low induced capacitive current in the gate. This in turn enables faster gate switching.

The trench deep body structure described in conjunction with FIGS. 4D and 4E can be combined with other charge balancing techniques (eg, shielded gate or double gate structure) to further improve the switching speed, on-resistance, and blocking capability of the device.

The improvements provided by the power devices described above and modifications thereof result in strengthened switching elements for relatively lower voltage power electronics applications. The low voltage used here refers to, for example, a voltage range of about 30V-40V and below, and this range can be changed according to specific applications. Applications requiring blocking voltages generally above this range require some type of structural modification of the power transistor. In general, in order to maintain a higher voltage for the device during the blocking state, the doping concentration in the drift region of the power transistor is reduced. However, a lightly doped drift region leads to an increase in the transistor on-resistance _RDSon . Higher resistivity directly increases the power loss of the switch. With new developments in semiconductor manufacturing that further reduce the packaging density of power devices, power loss becomes even more important.

Attempts have been made to improve the on-resistance and power loss of the device while maintaining a high blocking voltage. Many of these attempts have used various vertical charge control techniques to generate large in-plane electric fields vertically in semiconductor devices. A number of device structures of this type have been proposed, including the lateral depletion device disclosed in Marchant's co-owned U.S. Patent No. 6,713,813, entitled "Field Effect Transistor Having a Lateral Depletion Structure," and Kocon's co-owned U.S. Patent Application No. 6,376,878 is described, the entire contents of which are hereby incorporated by reference.

FIG. 5A shows a partial cross-sectional view of an exemplary power MOSFET 500A having a planar gate structure. MOSFET 500A appears to have a similar structure to planar MOSFET 200B of FIG. 2B , but differs from that device in two important respects. Instead of filling the trenches 520 with a conductive material, such as a dielectric material such as silicon dioxide, the device also includes a discontinuous floating p-type region 524 separated adjacent the outer sidewalls of the trench. As described in connection with the dual-trench MOSFET of FIG. 2A, the conductive material (eg, polysilicon) within the source trench 202 helps improve the breakdown voltage of the cell by driving the depletion region deep into the drift region. Removal of conductive material from these trenches will thus result in lower breakdown voltage until other methods of reducing the electric field are used. The floating region 524 is used to reduce the electric field.

Referring to MOSFET 500A shown in FIG. 5A, since the electric field increases when the drain voltage is increased, the floating p-regions 524 acquire a corresponding potential determined by them in the space charge region. The floating potential of these p-regions 524 pushes the electric field deeper into the drift region, resulting in a more uniform field throughout the depth of the mesa region between trenches 520 . As a result, the breakdown voltage of the transistor increases. An advantage of replacing the conductive material in the trench with an insulating material is that more of the space charge region is across the insulator rather than possibly the drift region of silicon. Because the dielectric constant of the insulator is lower than that of, for example, silicon, and because the depletion region in the trench is reduced, the output capability of the device is significantly reduced. This further enhances the switching characteristics of the transistor. The depth of the trench 520 filled with dielectric material depends on the voltage requirements; the deeper the trench, the higher the blocking voltage. A further advantage of the vertical charge control technique is that it allows transistor cells to be placed laterally for thermal isolation without the need for increased capacitance. In an alternative embodiment, instead of a floating p-region, a p-type layer is provided along the outer sidewalls of the trench filled with dielectric material to achieve a similar vertical charge balance. A simplified partial cross-sectional view of this embodiment is shown in FIG. 5B , where the outer sidewall of trench 520 is covered by a p-type layer or liner 526 . In the exemplary embodiment in Figure 5B, the gate is also trenched, further improving the transconductance of the device. Other examples of improved power devices using variations of this technique are described in commonly assigned U.S. Patent Application No. 10/200,056, entitled "Vertical Change Control Semiconductor Device with Low Output Capacitance," by Sapp et al. (Attorney Docket No. 18865- 0097/17732-55280), the entire contents of which are hereby incorporated by reference.

As described above, trench MOSFET 500B of FIG. 5B exhibits reduced output capacitance and improved breakdown voltage. However, because the active trenches (gate trenches 502 ) are located between charge control trenches 520 filled with dielectric material, the channel width of MOSFET 500B cannot be as wide as that of conventional trench MOSFET structures. This may result in higher on-resistance R _DSon . Referring to FIG. 5C , an alternative embodiment of a vertical charge controlled trench MOSFET 500C with elimination of sub charge control trenches is shown. Trench 502C in MOSFET 500C includes a gate electrode 510 and a lower portion filled with a dielectric material extending deep into drift region 506 . In one embodiment, trench 502C extends to a depth that is approximately half the depth of drift region 506 . As shown, a P-shaped bushing 526C wraps around the outer wall along the lower portion of each groove. This single trench structure eliminates secondary charge control trenches for increased channel width and lower R _DSon . To reduce output capacitance and gate-drain capacitance, a major portion of the electric field is maintained in the lower portion of the deeper trench 502C where the outer walls of the trench are surrounded by a p-type liner 526C. In an alternative embodiment, a plurality of discontinuities are formed along the sides and bottom of the trench 502C p-type liner 526C. Other embodiments can be realized by combining single trench charge control with the shielded gate or double gate techniques described above to further reduce the parasitic capacitance of the device.

Referring to FIG. 6 , there is shown a simplified cross-sectional view of a power MOSFET 600 suitable for high voltage applications that also require faster switching speeds. MOSFET 600 combines a vertical charge control technique for improved breakdown voltage and a shielded gate structure for improved switching speed. As shown in FIG. 6 , the shield electrode 611 is located between the gate conductive material 610 in the gate trench 602 and the bottom of the trench. Electrode 611 shields the gate of the transistor from the underlying drain region (drift region 606 ), so that the gate-drain capacitance of the transistor is significantly reduced, thus increasing its maximum switching frequency. Dielectric-filled trenches 620 with p-doped liners 626 help generate large in-plane electric fields vertically to improve device breakdown voltage. In operation, the combination of the trench 620 filled with dielectric material and the p-type liner 626 and the shielded gate structure reduces parasitic capacitance and helps to deplete the n-drift region, concentrating the electric field at the edge of the gate electrode dispersion. This type of device can be used in RF amplifier or high frequency switching applications.

Figure 7 shows another alternative embodiment of a power MOSFET suitable for higher voltage, higher frequency applications. In the simplified example shown in Figure 7, MOSFET 700 combines vertical charge control techniques to improve breakdown voltage and a dual gate structure to improve switching speed. Similar to the device shown in FIG. 6 , vertical charge control is achieved by using a trench 720 filled with a dielectric material with a p-doped liner 726 . The reduction of parasitic capacitance is achieved by using a double gate structure, whereby the main gate electrode G1 is shielded from the drain (n-drift region 706 ) by the sub-gate electrode G2. In order to invert the channel in region 701 to ensure continuous flow of current through the continuous channel when the device is turned on, the sub-gate electrode G2 can be continuously biased or biased just before the switching action.

In another embodiment, the shielded vertical charge control MOSFET also uses doped trench sidewalls filled with dielectric material to realize an integrated Schottky diode. FIG. 8 shows an example of a shielded gate MOSFET 800 according to this embodiment. In this example, electrode 811 at the bottom of trench 802 shields gate electrode 810 from drift region 806 to reduce gate-drain parasitic capacitance. Dielectric-filled trenches 820 with p-doped liners on the outer sidewalls are used for vertical charge control. A Schottky diode 828 is formed between two trenches 820A and 820B forming a mesa structure of width W. This Schottky diode structure is spread throughout the trench MOSFET cell array to enhance the performance characteristics of the MOSFET switch. The forward voltage drop is reduced by taking advantage of the low barrier height of the Schottky structure 828 . In addition, this diode has the advantage of inherent reverse recovery speed compared to normal PN junctions of vertical power MOSFETs. By doping the sidewalls of the trench 820 filled with a dielectric material such as boron, sidewall leakage channels due to phosphorus segregation are eliminated. The characteristics of the trench process can be used to optimize the performance of the Schottky diode 828 . For example, in one embodiment, the width W is adjusted so that the loss in the drift region of the Schottky diode 828 is influenced and controlled through the adjacent PN junction, so as to increase the reverse voltage capability of the Schottky diode 828 . Examples of monolithically integrated trench MOSFETs and Schottky diodes can be found in commonly assigned US Patent No. 6,351,018 to Sapp, the entire contents of which are hereby incorporated by reference.

It should be understood that Schottky diodes formed between trenches filled with dielectric material can be integrated with various types of MOSFETs, including MOSFETs with planar gate structures, with or without thick dielectric at the bottom of the trenches. Trench-gate MOSFETs without any shield electrode, etc. An exemplary embodiment of a dual-gate trench MOSFET with an integrated Schottky diode is shown in FIG. 9A. MOSFET 900A includes a gate trench 902 in which primary gate G1 is formed over secondary gate G2 to reduce parasitic capacitance and increase switching frequency. MOSFET 900A also includes a trench 920 filled with a dielectric material, wherein the trench 920 has a p-doped liner 926 formed along its outer sidewall for vertical charge control to increase the blocking voltage of the device. For many of the embodiments described above (eg, shown in FIGS. 5B, 6, 7, 8, and 9A), one method of forming the liner is by using a plasma doping process. As shown, a Schottky diode 928A is formed between two adjacent dielectric-filled trenches 920A and 920B. In another variation, a monolithically integrated Schottky diode and trench MOSFET are formed without filling the trench with a dielectric material. Figure 9B is a cross-sectional view of an exemplary device 900B according to this embodiment.

MOSFET 900B includes active trenches 902B, each having an electrode 911 buried under a gate electrode 910. As shown, a Schottky diode 928B is formed between the two trenches 902L and 902R. The charge balance effect of the bias electrode 911 increases the doping concentration of the drift region without affecting the reverse blocking voltage. For this structure, the higher doping concentration of the drift region reduces the forward voltage drop. As with the aforementioned trench MOSFETs with buried electrodes, the depth of each trench and the number of buried electrodes can vary. In a variation example shown in FIG. 9C , as shown, the trench 902C has only one buried electrode 911 , and the gate electrode 910S in the Schottky cell 928C is connected to the source electrode. Alternatively, the gate of the Schottky diode can be connected to the gate terminal of the MOSFET. Figures 9D, 9E and 9F show modifications to the exemplary layout of Schottky diodes interspersed within an active cell array of MOSFETs. Figures 9D and 9E show the layout of single-mesa Schottky and dual-mesa Schottky, respectively, and Figure 9F shows the layout of the Schottky region perpendicular to the MOSFET trench. These and other variations of integrated Schottky diodes (including optional Schottky for multiple MOSFET regions) can be combined with any of the transistor structures described herein.

In another embodiment, the voltage blocking capability of a power device is enhanced by using one or more diode structures connected in series, buried in a trench provided with a dielectric material, and arranged in parallel with current flow in the drift region of the device . FIG. 10 provides a simplified cross-sectional view of an exemplary trench MOSFET 1000 according to this embodiment. Diode trenches 1020 are disposed on both sides of the gate trench 1002 and extend from the well into the drift region 1006 . The diode trench 1020 includes one or more diode structures composed of opposite conductivity type regions 1023 and 1025, wherein the conductivity type regions 1023 and 1025 form one or more PN junctions within the trench. In one embodiment, the trench 1020 includes a single region having an opposite polarity to the drift region such that a single PN junction is formed at the interface with the drift region. P-type and n-type doped polysilicon or silicon may be used to form regions 1023 and 1025, respectively. Other types of materials (eg, silicon carbide, gallium arsenide, silicon germanium, etc.) may also be used to form regions 1023 and 1025 . A thin dielectric layer 1021 extending along the inner sidewalls of the trench insulates the diode within the trench from the drift region 1006 . As shown, there is no dielectric layer along the bottom of the trench 1020, thus allowing the bottom region 1027 to make electrical contact with the underlying substrate. In one embodiment, similar considerations to those governing the design and fabrication of gate oxide layer 1008 apply to the design and formation of dielectric layer 1021 . For example, the thickness of the dielectric layer 1021 is determined by factors such as the voltage it needs to hold and the degree of electric field induced in the diode trench in the drift region (eg, the degree of coupling through the dielectric layer).

In operation, when MOSFET 1000 is biased in its blocking state, the PN junctions within the diode trenches are reverse biased by the peak electric field developed at each diode junction. Through the dielectric layer 1021 , the electric field in the diode trench induces a corresponding electric field in the drift region 1006 . The induced electric field appears in the drift region in the form of an up-swing spike and generally increases in the electric field bending in the drift region. This increase in the electric field results in a larger area of electric field bending, which in turn leads to a higher breakdown voltage. Variations of this embodiment are detailed in commonly assigned U.S. Patent Application Serial No. 10/288,982 (Attorney Docket No. 18865-117/17732-66560) entitled "Drift Region Higher Blocking Lower Forward Voltage Drop Semiconductor Structure" by Kocon et al. described, the entire contents of which are hereby incorporated by reference.

There may be other embodiments of power devices that combine trench diodes for charge balancing and techniques to reduce parasitic capacitance (eg, shielded gate or double gate structures). Figure 11 shows an example of a MOSFET 1100 according to one such embodiment. MOSFET 1100 uses shield electrode 1111 under gate electrode 1110 within active trench 1102 to reduce the gate-drain capacitance C _gd of the transistor associated with MOSFET 300A as in FIG. 3A . A different number of PN junctions are used in MOSFET 1100 compared to MOSFET 1000 . FIG. 12 is a cross-sectional view of a MOSFET 1200 incorporating dual gate technology and a trench diode structure. Active trench 1202 in MOSFET 1200 includes primary gate G1 and secondary gate G2 and operates in the same manner as the active trench in the dual gate MOSFET described in FIG. 4B . The diode trench 1220 provides charge balance to increase the blocking voltage of the device, and the dual-gate active trench structure improves the switching speed of the device.

FIG. 13 shows yet another embodiment combining trench diode charge balancing techniques with integrated Schottky diodes in a planar gate MOSFET 1300. Similar advantages can be obtained by integrating the Schottky diode 1328 with the MOSFET described in FIGS. 8 and 9 . In this embodiment, for the purpose of illustration, a planar gate structure is shown, and those skilled in the art should understand that the combination of Schottky diode and trench diode structure can be applied to any other type of gate structure ( In MOSFETs including trench gate, double gate, and shielded gate). As described in connection with MOSFETs 400D and 400E of FIGS. 4D and 4E , either of the composite embodiments can also be combined with trench body technology to further reduce fringe parasitic capacitance. Other variations and equivalents are also possible. For example, the number of oppositely conductive regions within a diode trench can vary with the depth of the diode trench. The polarity of the opposite conducting regions can be reversed with the polarity of the MOSFET. Furthermore, any PN regions (923, 925 or 1023, 1025, etc.) can be independently biased if desired by, for example, extending the regions along a third dimension, up to the silicon surface where electrical contact can be made to them. Further, multiple diode trenches can be used as required by the device size and voltage needs of the application, and the spacing and configuration of the diode trenches can be achieved in various stripe or grid designs.

In another embodiment, it is assumed that accumulation mode transistors use various charge balancing techniques for reducing forward voltage loss and improving blocking capability. In general accumulation mode transistors there is no blocking junction and the device is turned off by pinching the current by slightly inverting the channel region near the gate terminal. When the transistor is turned on by applying a gate bias, an accumulation layer is formed in the channel region instead of an inversion layer. Since no inversion channel is formed, the channel resistance is minimized. Additionally, the absence of a PN body diode in the accumulation mode transistor minimizes losses that would otherwise occur in certain circuit applications (eg, synchronous rectifiers). A disadvantage of conventional accumulation mode devices is that the drift region has to be lightly doped to provide reverse bias when the device is in blocking mode. A more lightly doped drift region results in a higher on-resistance. Embodiments described herein overcome this limitation by using various charge balancing techniques in accumulation mode devices.

Referring to FIG. 14 , a simplified embodiment of an exemplary accumulation mode transistor 1400 with alternating conduction regions arranged in parallel with the current flow is shown. In this embodiment, transistor 1400 is an n-channel transistor comprising: a gate terminal formed within trenches 1402, an n-type channel region 1412 formed between the trenches, columnar n-type and Drift region 1406 of p-type portions 1403 and 1405 , and n-type drain region 1414 . Unlike enhancement-mode transistors, accumulation-mode transistor 1400 does not include a body region that blocks a (p-type in this example) well or forms a channel within it. Conversely, a conductive channel is formed when the accumulation layer is formed in region 1412 . Transistor 1400 is generally turned on or off depending on the doping concentration of region 1412 and the doping type of the gate electrode. When the n-type region 1412 is fully depleted and inverted slightly, the transistor is off. Adjusting the doping concentration of the regions 1403 and 1405 of opposite polarity to maximize charge spreading enables the transistor to maintain a higher voltage. By not allowing the junction formed between remote regions 1412 and 1406 to linearly reduce the electric field, the electric field distribution is flattened with columnar opposite polarity regions parallel to the current flow. The charge spreading effect of this structure allows the use of a more heavily doped drift region which reduces the on-resistance of the transistor. The doping concentration of each region can vary, for example, n-type regions 1412 and 1403 can have the same or different doping concentration. Those skilled in the art will appreciate that improved p-channel transistors can be obtained by reversing the polarity of the various regions of the device shown in FIG. 14 . Other modifications of the columnar opposite polarity regions in the drift region will be described in detail later in connection with ultra-high voltage devices.

Figure 15 is a simplified diagram of another accumulation mode device 1500 with trench electrodes for charge spreading. All regions 1512, 1506 and 1514 are of the same conductivity type (n-type in this example). For a general off device, the gate polysilicon 1510 is made p-type. The doping concentration of region 1512 is adjusted to form a depleted blocking junction under no bias conditions. In each trench 1502 , one or more buried electrodes 1511 are formed below the gate electrode 1510 , all surrounded by a dielectric material 1508 . As described in connection with enhancement mode MOSFET 300A of FIG. 3A, buried electrode 1511 acts as a field plate and, if desired, can be biased to a potential that optimizes its charge spreading function. Since charge spreading can be controlled by independently biasing the buried electrodes 1511, the maximum electric field can be significantly increased. Similar to the buried electrodes used in MOSFET 300A, different variations of the structure can be achieved. For example, the depth of trench 1502 and the size and number of buried electrodes may vary depending on the application. In the same manner as the trench structure of MOSFET 300B shown in FIG. 3B, the charge diffusion electrode can be buried in a trench separate from the active trench covering the gate electrode of the transistor. An example of such an embodiment is shown in FIG. 16 . In the example shown in FIG. 16, the n-type region 1612 includes a heavily doped n+ source region 1603 that may optionally be added. As shown, heavily doped source region 1603 may extend along the upper edge of n-type region 1612, or may be formed as two regions adjacent to the trench wall along the upper edge of n-type region 1612 (in FIG. not shown). In some embodiments, the dopant concentration of n+ region 1603 may necessarily be lower than that of n-type region 1606 in order to ensure that the transistor can be properly turned off. This optionally heavily doped source region can be used in the same manner in any of the accumulation transistors described herein.

Another embodiment of an improved accumulation mode transistor uses a dielectric-filled trench with an outer liner of opposite polarity. FIG. 17 is a simplified cross-sectional view of an accumulation transistor 1700 according to this embodiment. A trench 1720 filled with a dielectric material extends down from the surface of the silicon well into the drift region 1706 . Trench 1720 is substantially filled with a dielectric material such as silicon dioxide. In this exemplary embodiment, transistor 1700 is an n-channel transistor with a trench gate structure. As shown, p-type region 1726 is along the outer wall of trench 1720 filled with dielectric material. Similar to enhancement mode transistors 500A, 500B, and 500C described in connection with FIGS. 5A , 5B, and 5C, respectively, trench 1720 reduces the output capacitance of the transistor, and p-type liner 1726 provides charge balancing in the drift region to increase transistor blocking ability. In an alternative embodiment shown in FIG. 18 , oppositely doped liners 1826N and 1826P are formed on opposite sides of the dielectric material-filled trench 1820 . That is, the trench 1820 filled with dielectric material has a p-type liner 1826P extending along the outer sidewall of one side, and an n-type liner 1826N extending along the outer sidewall of the other side of the same trench. Variations with accumulation transistors combined with trenches filled with dielectric material are also possible as described in connection with corresponding enhancement mode transistors. For example, this includes: a device as shown in FIG. 5A, with a planar (as opposed to a trench) gate structure and an accumulation transistor with a floating p-type region in place of the p-type liner 1726; a device as shown in FIG. 5B, An accumulation transistor with a single trench structure covering only the outer sidewall but not the bottom of the trench 1726; and a device as shown in FIG. 5C , etc.

In another embodiment, the accumulation mode transistor uses one or more diodes formed in series within the trench for charge balancing. Figure 19 shows a simplified cross-sectional view of an exemplary accumulation mode transistor 1900 according to this embodiment. Diode trenches 1920 are provided on each side of the gate trench 1902 extending from the well into the drift region 1906 . Gate trench 1902 includes one or more diode structures, wherein the diode structure consists of regions 1923 and 1925 of opposite conductivity forming one or more PN junctions within the trench. P-type and n-type doped polysilicon or silicon may be used to form regions 1923 and 1925 . A thin dielectric layer 1920 extending along the inner walls of the trench insulates the diode from the drift region 1906 within the trench. As shown, there is no dielectric layer along the bottom of trench 1920, thus allowing bottom region 1927 to make electrical contact with the underlying substrate. Other modifications of this combining accumulation transistors and trench diodes are possible as described in connection with the corresponding enhancement mode transistors shown in FIGS. 10 , 11 , 12 and 13 .

Any of the above accumulation mode transistors can use a heavily doped reverse polarity region in the top (source) region. FIG. 20 is a simplified three-dimensional diagram of an exemplary accumulation mode transistor 2000 showing this feature combined with other variations. In this embodiment, the charge balancing diodes in the accumulation mode transistor 2000 are formed in the same trench as the gate. Trench 2000 includes a gate electrode 2010 under which are n-type 2023 and p-type 2025 silicon or polysilicon layers forming a PN junction. A thin dielectric layer 2008 separates the diode structure from the gate terminal 2002 and the drift region 2006 . As shown, heavily doped p+ regions 2118 are formed in intervals along the length of the mesas formed between the trenches in source regions 2012 . The heavily doped p+ region 2118 reduces the area of the n- region 2012 and reduces leakage of the device. The p+ region 2118 also allows for a p+ contact that will improve hole current in avalanche and improve device robustness. Modifications to an exemplary vertical MOS gate accumulation transistor have been discussed to illustrate various features and advantages of such devices. Those skilled in the art will appreciate that these can also be implemented in other types of devices including lateral MOS gate transistors, diodes, bipolar transistors, and the like. The charge spreading electrode may be formed in the same trench as the gate or in a separate trench. The various exemplary accumulation mode transistors described above have trenches terminated in the drift region, but they could also be terminated in a heavily doped substrate connected to the drain. Various transistors can be formed in a stripe or mesh structure including hexagonal or square transistor cells. Other modifications and combinations are possible as described in conjunction with some of the other embodiments, some of which are further described in previously referenced U.S. Patent Application Nos. 60/506,194 and 60/588,845, the entire contents of which are hereby incorporated by reference .

Another class of power switching devices designed for ultra-high voltage applications (eg, 500V-600V and above) uses alternating vertical sections of p-doped and n-doped silicon in the epitaxial region between the substrate and the well. Referring to FIG. 21, an example of a MOSFET 2100 using this type of structure is shown. In MOSFET 2100, region 2102, sometimes referred to as a voltage sustaining or blocking region, includes alternating n-type regions 2104 and p-type regions 2106. The effect of this structure is that the depletion region diffuses horizontally to either side of regions 2104 and 2106 when a voltage is applied to the device. The entire vertical thickness of the blocking layer 2102 is depleted before the horizontal electric field is high enough to produce an avalanche breakdown because the net amount of charge in each vertical region 2104, 2106 is less than that required to produce a breakdown electric field. After the region is completely depleted horizontally, the electric field continues to build up vertically until it reaches an avalanche electric field of about 20 to 30 volts per micron. This significantly enhances the device's voltage blocking capability, extending the device's voltage range to 400 volts or more. Various modifications of this type of superjunction device are described in detail in Nielson's co-owned Patent Nos. 6,081,009 and 6,066,878, the entire contents of which are hereby incorporated by reference.

A modification to superjunction MOSFET 2100 uses floating p-type islands within the n-type blocking region. The use of floating p-type islands, as opposed to the pillar approach, reduces R _DSon by reducing the thickness of the charge balancing layer. In one embodiment, instead of separating the p-type islands uniformly, they are separated from each other so as to maintain an electric field close to the critical electric field. FIG. 22 is a simplified cross-sectional view showing a MOSFET 2200 as one example of a device according to this embodiment. In this example, the deeper floating p-region 2226 is further apart from the upper one. That is, distance L3 is greater than distance L2, and distance L2 is greater than distance L1. By manipulating the distance between the floating junctions in this way, the minority carriers enter as smaller particles. The smaller the source particles of these carriers, the lower R _Dson and higher breakdown voltage can be achieved. Those skilled in the art will appreciate that many modifications may be made. For example, the number of floating regions 2226 in the vertical direction is not limited to four as shown in the figure, and the optimum number may vary. In addition, the doping concentration of each floating region 2226 can also be changed. For example, in one embodiment, the doping concentration of each floating region 2226 gradually decreases as the region approaches the substrate 2114 .

Further, as described in conjunction with low and medium voltage devices, many techniques for reducing parasitic capacitance to increase switching speed, including shielded gate and double gate structures, can be compared to the high voltage devices and their modifications described in Figures 21 and 22 to combine. FIG. 23 is a simplified cross-sectional view of a high voltage MOSFET 2300 incorporating a modification of the superjunction structure and a dual gate structure. MOSFET 2300 has a planar double-gate structure consisting of gate terminals G1 and G2 similar to the double-gate transistor shown, for example, in FIG. 4B. The opposite polarity (p-type in this example) region 2326 is disposed vertically in the n-type drift region 2306 below the p-well 2308 . In this example, the p-type regions 2326 are sized and spaced differently such that regions 2326 disposed closer to the well 2308 are in contact with each other as shown, while regions 2326 disposed further down are floating and smaller in size. Figure 24 shows yet another embodiment for a high voltage MOSFET 2400 incorporating super junction technology and a shielded gate structure. MOSFET 2400 is a trench-gated device having gate electrode 2410 and shield electrode 2411 shielded from drift region 2406, eg, similar to MOSFET 300A in FIG. 3A. MOSFET 2400 also includes floating region 2426 of opposite polarity disposed within drift region 2406 in parallel with the current flow.

terminal structure

The various types of discrete devices described above have a breakdown voltage limited by the cylindrical or spherical shape of the depletion region at the edge of the die. Since such cylindrical or spherical breakdown voltages are generally much lower than the parallel plane breakdown voltage BV _PP in the active region of the device, it is necessary to terminate the edge of the device in order to achieve a device breakdown close to the breakdown voltage of the active region Voltage. Different techniques have been developed to amplify the electric field and voltage uniformly over the edge termination width to achieve a breakdown voltage close to BV _PP . These techniques include field plates, field rings, junction termination extension (JTE) and various combinations of these techniques. One example of a field termination structure including a deep junction (deeper than a well) with an overlying field oxide surrounding an array of active cells is described in commonly-owned US Patent No. 6,429,481 to Mo et al. For example, in the case of n-channel transistors, the termination structure includes a deep p+ region forming a PN junction with an n-type drift region.

In an alternative embodiment, one or more annular trenches surrounding the periphery of the cell array are used to attenuate the electric field and increase avalanche breakdown. Figure 25 shows a commonly used trench layout diagram for trench transistors. Active trench 2502 is surrounded by annular termination trench 2503 . In this structure, the region 2506 shown by the dashed circle at the end of the mesa is depleted faster than the other regions, causing the electric field in this region to be enhanced so that the breakdown voltage is reduced under reverse biased conditions. Therefore, this type of design is limited to lower voltage devices (eg, <30V). Figures 25B to 25F illustrate several alternative embodiments of termination structures with trench layouts different from those shown in Figure 25A to reduce high electric field regions. As can be seen from the figures, in these embodiments some or all of the active trenches are separated from the termination trenches. The gap _WG between the active trench ends and the termination trench serves to reduce the electric field pooling effect observed in the structure shown in Figure 25A. In one exemplary embodiment, _WG is made to be about half the width of the mesa between the trenches. For higher voltage devices, multiple termination trenches as shown in Figure 25F can be used to further reduce the breakdown voltage of the device. Variations on some of these embodiments are described in more detail in commonly-owned US Patent No. 6,683,363 to Challa, entitled "Trench Structure for Semiconductor Devices," which is hereby incorporated in its entirety.

26A-26C show cross-sectional views of exemplary trench termination structures for charge balance trench MOSFETs. In the exemplary embodiment shown, MOSFET 2600A uses a shielded gate structure with a shielded poly electrode 2611 buried within active trench 2602 beneath gate electrode 2610 . In the embodiment shown in FIG. 26A, a relatively thick dielectric layer (oxide layer) 2605A is provided along the termination trench 2603A, and the termination trench 2603A is filled with a conductive material such as an electrode 2607A. The thickness of the oxide layer 2605A, the depth of the termination trench 2603A, and the spacing between the termination trench and the adjacent active trench (eg, the width of the last mesa) are determined by the device reverse blocking voltage. In the embodiment shown in Figure 26A, the trench at the surface is wider (T-trench structure) and a metal field plate 2609A is used above the termination region. In an alternative embodiment (not shown), the field plate may be formed from polysilicon by extending electrode 2607A within termination trench 2603A above the surface and above the termination region (to the left end of the termination trench in FIG. 26A ). . There can be many changes. For example, a p+ region (not shown) contacting silicon can be added under the metal for better ohmic contact. The p-well region 2604 in the last mesa adjacent to the termination trench 2603A and the respective contacts between them can be selectively removed. A floating p-type region can also be added to the left of termination trench 2603A (eg, outside the active region).

In another variation, instead of filling the termination trench 2603 with polysilicon, the polysilicon electrode is buried in the lower portion of the trench within the oxide-filled trench. Figure 26B shows this embodiment where approximately half of the termination trench 2603B is filled with oxide 2605B and the bottom half has a polysilicon electrode 2607B buried within the oxide. The depth of trench 2603B and the height of buried electrode 2607B may vary based on device processing. In yet another embodiment shown in FIG. 26C, termination trench 2603C is substantially filled with dielectric material, with no conductive material buried therein. For the three embodiments shown in Figures 26A, B, and C, the width of the last mesa separating the termination trench from the last active trench can be compared to that of a typical mesa formed between two active trenches. The widths vary and can be adjusted to achieve optimal charge balance within the termination region. All modifications described above in connection with the structure shown in FIG. 26A can be applied to those shown in FIGS. 26B and 26C. Further, those skilled in the art will appreciate that when using the termination structures described herein for shielded gate devices, similar structures can be implemented with the termination regions for all of the various trench-based devices described above.

For lower voltage devices, the corner design of the trench termination ring may not be critical. However, for higher voltage devices, it may be desirable to have a larger radius of curvature for the rounding of the termination ring corners. The higher the voltage requirement of the device, the larger the radius of curvature of the termination trench corners. The number of termination rings can also increase with increasing device voltage. FIG. 27 shows an exemplary device having two trenches 2703-1 and 2703-2 with relatively large radii of curvature. The spacing between trenches can also be adjusted based on the voltage requirements of the device. In this embodiment, the distance S1 between the termination trenches 2703-1 and 2703-2 is about twice the distance between the first termination trench 2703-1 and the end of the active trench.

28A, 28B, 28C, and 28D show exemplary cross-sectional views for various termination regions with silicon pillar charge balance structures. In the embodiment shown in Figure 28A, a field plate 2809A contacts each ring of p-type pillars 2803A. This allows a wider mesa area because of the lateral losses due to the field plates. The breakdown voltage generally depends on the thickness of the field oxide, the number of rings, and the depth and spacing of the terminal pillars 2803A. There can be many different changes to this type of terminal structure. For example, Figure 28B shows an alternative embodiment where a large field plate 2809B-1 covers all posts 2803B except the last post connected to another field plate 2809B-2. By grounding the large field plate 2809B-1, the mesa region between the p-type pillars is quickly depleted, and the horizontal voltage drop will not be significant, below the breakdown voltage of the embodiment shown in Figure 28A. In another embodiment shown in Figure 28C, the termination structure has no field plate on the middle post. Since there is no field plate on the middle pillar, there is a narrow mesa area to deplete sufficiently. In one embodiment, tapering the mesa width towards the outer ring yields the best performance. The embodiment shown in Figure 28D facilitates contact to the p-type pillars by providing a wider well region 2808D and increasing the spacing between field oxide layers.

In the case of ultra-high voltage devices using various superjunction technologies of the type described above, the breakdown voltage is much higher than conventional BV _PP . For superjunction devices, charge balancing or superjunction structures (eg, opposite polarity pillars or floating regions, buried electrodes, etc.) can also be used in the termination region. Standard edge termination structures in combination with charge-balancing structures can also be used, for example, top-plane field plates at the edge of the device. In some embodiments, the standard edge structure on top can be eliminated by using fast charge reduction in the termination junction. For example, the p-type pillars in the termination region can be formed with less charge the farther away they are from the active region, where the active region creates a net n-type balanced charge.

In one embodiment, the spacing between p-type pillars within the termination region is varied as the distance the pillars move away from the active region. Figure 29A shows a highly simplified cross-sectional view of an exemplary embodiment of a device 2900A according to this embodiment. In the active region of device 2900A, opposite conductivity pillars 2926A, eg, made of a plurality of connected p-type spheres, are formed under p-type well 2908A in n-type drift region 2904A. At the edge of the device, under the termination region, p-type termination pillars TP1, TP2 to TPn are formed as shown. Instead of having a uniform spacing within the active area, the center-to-center spacing between the terminal posts TP1 to TPn increases as the distance from the interface of the moving post to the active area increases. That is, the distance D1 between TP2 and TP3 is smaller than the distance D2 between TP3 and TP4, and the distance D2 is smaller than the distance D3 between TP4 and TP5, and so on.

Many variations can be made to this superjunction termination structure. For example, instead of forming p-type terminal pillars TP1 to TPn at different distances within voltage sustaining layer 2904A, the center-to-center spacing can be kept uniform, but the width of each terminal pillar can be varied. Fig. 29B shows a simplified example of a terminal structure according to this embodiment. In this example, terminal post TP1 has a width W1 that is greater than width W2 of terminal post TP2 , which in turn is greater than width W3 of terminal post TP3 , and so on. The resulting structure in device 2900B is similar to that in device 2900A in terms of spacing between opposite polarity charge balancing regions within the termination region, although the center-to-center spacing between trench posts may be the same in device 2900B. In another exemplary embodiment shown in the simplified cross-sectional view of FIG. 29C, the width of each opposite polarity pillar 2926C within the active region decreases from the top plane to the substrate, while the width of the terminal pillars TP1 and TP2 remains unanimous. In this way, the desired breakdown voltage is achieved with less area. Those skilled in the art should understand that the various terminal structures described above can be combined in any desired manner, for example, the center-to-center spacing and/or overall width of the terminal post comprising device 2900C shown in FIG. 29C can be combined with that of FIG. 29A and the embodiment shown in 29B to change.

Technology

A number of different devices having trench structures with multiple buried electrodes or transistors have been described so far. These devices require electrical contact with each buried layer in order to bias the trench electrodes. Methods for forming trench structures with buried electrodes and for making contact with buried polysilicon layers within the trenches are disclosed herein. In one embodiment, contact is made to the trench polysilicon layer at the edge of the die. FIG. 30A shows an example of an edge contact for a trench device 3000 having two polysilicon layers 3010 and 3020 . Figure 30A shows a cross-sectional view of the device along the longitudinal axis of the trench. According to this embodiment, the trenches terminate close to the edge of the die and the polysilicon layers 3010 and 3020 are raised to the surface of the substrate for contact purposes. Openings 3012 and 3022 in dielectric (oxide) layers 3030 and 3040 allow metal contact to the polysilicon layer. 30B to 30F illustrate various processing steps involved in forming the edge contact structure of FIG. 30A. In FIG. 30B , a dielectric (eg, silicon dioxide) layer 3001 is patterned on top of epitaxial layer 3006 and the exposed surface of the substrate is etched to form trenches 3002 . Then, as shown in FIG. 30C, a first oxide layer 3003 is formed across the upper surface of the substrate including the trench. Then, as shown in FIG. 30D , a first conductive material (eg, polysilicon) 3010 is formed on top of the oxide layer 3003 . Referring to FIG. 30E , the polysilicon layer 3010 is etched within the trench, and another oxide layer 3030 is formed on the polysilicon layer 3010 . Similar steps are performed to form a second oxide-polysilicon layer-oxide sandwich as shown in FIG. 30F, etching the top oxide layer 3040 as shown to form metal contacts for the polysilicon layers 3010 and 3020, respectively. The openings 3012 and 3022. The final steps can be repeated to form additional polysilicon layers and, if desired, the polysilicon layers can be connected together by overlying metal layers.

In another embodiment, contact to multiple polysilicon layers within a given trench is made within the active area of the device rather than along the edge of the die. Figure 31A shows an example of an active area contact structure for multiple buried polysilicon layers. In this example, the cross-sectional view along the longitudinal axis of the trench shows the polysilicon layer 3110 providing the gate terminal and the polysilicon layers 3111a and 3111b providing the two shielding layers. When the three separate metal lines 3112, 3122 and 3132 are shown making contact with the polysilicon layer, they may be connected together and connected to the source terminal of the device, or any other combination of contacts may be used as required by the particular application. An advantage of this structure over the multilayer edge contact structure shown in Figure 30A is the planar nature of the contact.

31B to 31M illustrate one example of a process flow for forming an active region shield contact structure for a trench with two polysilicon layers. Following the etching of the trench 3102 in FIG. 31B is the formation of a screen oxide layer 3108 in FIG. 31C. Then, as shown in FIG. 31D, a shielding polysilicon 3111 is deposited and recessed into the trench. In FIG. 31E , the shield electrode 3111 is again recessed inwards, except where a shield contact is desired at the substrate surface. In FIG. 31E, mask 3109 protects the polysilicon in the middle trench from further etching. In one embodiment, the mask is applied at different locations along the different trenches, such as the middle trench, masking polysilicon recesses in the third dimension (not shown) to other portions of the trenches. In another embodiment, the shielding polysilicon 3111 in one or more selected trenches in the active region is masked along the full length of the trenches. Then, as shown in FIG. 31F, the shield oxide 3108 is etched, and then, as shown in FIG. 31G, a thin layer of gate oxide 3108a is formed over the top of the substrate after removal of the mask 3109. This is followed by deposition and recessing of the gate electrode (FIG. 31H), implantation and drive of the p-well (FIG. 31I), and n+ source implantation (FIG. 31J). Figures 31K, 31L and 31M respectively show the steps of BPSG deposition, contact etch and p+ heavily doped body implant followed by metallization. FIG. 31N shows a cross-sectional view of an alternative embodiment of an active area shield contact structure in which shield polysilicon 3111 forms a relatively wide mesa on top of the shield oxide. This facilitates contacting the shield electrode, but introduces topography that may further complicate the manufacturing process.

A simplified top-down layout view of an exemplary trench device with an active region shielding contact structure is shown in FIG. 32A. The mask defining the shield electrode recess prevents recessing of the shield electrode at location 3211C within the active region and the periphery of shield trench 3213 . A modification of this technique uses a "dogbone" shape for the shield poly recess mask, providing a wider area at the junction with each trench 3202 for contacting the shield poly. This allows the shield polysilicon in the masked area to be recessed as well, but to the start of the mesa, thus eliminating the topography. A top-down layout view of an alternative embodiment is shown in FIG. 32B where the active area trenches are connected to the peripheral trenches. In this embodiment, the shield poly recess mask prevents the shield poly from being recessed along the length of the selected trench (intermediate trench shown in this example) for active area shield trench contact with the source metal. 32C and 32D are simplified layout diagrams illustrating two different embodiments for making contact with peripheral trenches within a trench device with an open trench structure. In these figures, the active trench 3202 and the peripheral trench 3213 are represented by a single line for illustrative purposes. In FIG. 32C, extensions or fingers of the peripheral gate polysilicon standoff 3210 are interleaved with respect to the peripheral shield polysilicon fingers to separate the peripheral contacts from the peripheral trenches. Source and shield contact region 3215 also makes contact with the shield polysilicon in the active region at location 3211C as shown. The embodiment shown in Figure 32D eliminates the offset between the active and peripheral trenches to avoid possible limitations caused by trench slope requirements. In this embodiment, aligned with the horizontal extensions of the active trench 3202 and the peripheral trench 3213, the window 3217 in the gate polysilicon standoff 3210 is used for contact to be made to the shielding polysilicon around the peripheral trench. Active area contacts are made at location 3211C as in previous embodiments.

An alternative embodiment for contacting the trench shield polysilicon in the active area is shown in FIG. 33A. In this embodiment, instead of recessing the shield polysilicon, it extends vertically from above the physical portion of the active trench to the silicon surface. Referring to FIG. 33A , the gate polysilicon 3310 is divided into two parts as the shield polysilicon 3311 extends vertically along the height of the trench 3302 . The two gate polysilicon portions are connected together in place in the trench in the third dimension or as they enter the trench. One advantage of this embodiment is that instead of using the silicon space for the trench poly contact, the use of a region through which the source poly contact is made within the active trench. 33B to 33M illustrate one example of a process flow for forming an active shield contact structure of the type shown in FIG. 33A. In FIG. 33B, trenches 3302 are etched, followed by the formation of a shield oxide layer 3308 shown in FIG. 33C. Then, as shown in FIG. 33D, shielding polysilicon 3311 is deposited within the trenches. As shown in Figure 33E, the masking polysilicon 3311 is etched and recessed into the trench. Then, as shown in FIG. 33F, the shield oxide layer 3308 is etched, leaving exposed portions of the shield polysilicon 3311 forming two trenches on the sides of the shield polysilicon 3311 within the trench. Then, as shown in FIG. 33G, a thin gate oxide layer 3308a is formed across the top of the substrate, the sidewalls of the trench, and the grooves within the trench. This is followed by deposition and recessing of gate polysilicon (FIG. 33H), p-well implantation and drive (FIG. 33I), and n+ source implantation (FIG. 33J). Figures 33K, 33L and 33M respectively show the steps of BPSG deposition, contact etch and p+ heavily doped body implant followed by metallization. Changes to this process flow are possible. For example, the process step of forming gate polysilicon 3310 may precede the step of forming shield polysilicon 3311 by rearranging some process steps.

The specific processing methods and parameters and modifications thereof for carrying out the many steps of the above-described process flow are well known. For a given application, specific process methods, chemistries, and material types can be well tuned to enhance device manufacturability and performance. Improvements can be made starting from the raw material, that is, the substrate on which the epitaxial drift region is formed. In most power applications, it is desirable to reduce the on-resistance R _DSon of a transistor. The ideal on-resistance of a power transistor is a strong function of the critical field, where the critical field is defined as the maximum electric field in the device under breakdown conditions. Assuming reasonable mobility is maintained, the on-resistance of a transistor can be significantly reduced if the device is fabricated from a material with a critical field higher than that of silicon. Since many of the power device characteristics (including structures and processes) described thus far have been described in the context of silicon substrates, other embodiments of substrate materials other than silicon may be used. According to one embodiment, the power devices described herein are constructed of wide bandgap materials including, for example, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), diamond, etc. ) made of substrates. These wide bandgap materials exhibit critical fields greater than that of silicon and can be used to significantly reduce the on-resistance of transistors.

Another major contributor to reducing the on-resistance of a transistor is the thickness and doping concentration of the drift region. The drift region is typically formed from epitaxially grown silicon. In order to reduce _RDSon , it is desirable to minimize the thickness of the epitaxial drift region. The thickness of the epitaxial layer is controlled in part by the type of initial substrate. For example, for discrete semiconductor devices, a substrate doped with red phosphorus is a common type of material for the initial substrate. However, a characteristic of phosphorus atoms is that they diffuse rapidly in silicon. Therefore, the thickness of the epitaxial region formed on top of the substrate is determined to accommodate the upward diffusion of phosphorus atoms from the underlying heavily doped substrate.

In order to minimize the thickness of the epitaxial layer, according to one embodiment shown in FIG. 3415. The combined phosphorus-doped substrate and arsenic-doped buffer layer provide the basis for the subsequent formation of epitaxial drift region 3406 . The arsenic doping concentration of layer 3415 is determined by the breakdown voltage requirement of the device, and the thickness of the arsenic epitaxial layer 3415 is determined by a specific thermal budget. A uniform epitaxial layer 3406 may then be deposited on top of the arsenic epitaxial layer to a thickness determined by device requirements. The very low diffusivity of arsenic allows reducing the overall thickness of the epitaxial drift region, which reduces the on-resistance of the transistor.

In an alternative embodiment, to calculate the upward diffusion of dopant species from the heavily doped substrate to the epitaxial layer, a diffusion barrier layer is used between the two layers. According to an exemplary embodiment shown in FIG. 35 , a barrier layer 3515 composed of eg silicon carbide Si _x C _1-x is epitaxially deposited on a boron or phosphorous substrate 3514 . An epitaxial layer 3506 is then deposited on top of the barrier layer 3515 . Thickness and carbon compound can be varied according to the thermal budget of the process technology. Optionally, carbon dopant can be implanted into the substrate 3514 first, followed by heat treatment to activate the carbon atoms to form _{SixC1 -x} compounds on the surface of the substrate 3514 .

Another aspect of certain trench transistor technologies that limits the ability to reduce the thickness of the epitaxial layer is the junction formed between the deep body and the epitaxial layer, which is sometimes used in the active region and sometimes in the termination region. Formation of this deep body region typically involves an implantation step early in the process. The junction between the deep body and the drift region is of great extent due to the subsequent thermal budget required by the formation of the field oxide and gate oxide. To avoid premature breakdown at the edge of the die, a very thick drift region is required, which results in a higher on-resistance. In order to minimize the thickness of the required epitaxial layers, the use of diffusion barrier layers can also be used at deep body-epitaxial junctions. According to the exemplary embodiment shown in FIG. 36, the carbon dopant is implanted through the deep body window before performing the deep body implant. A subsequent thermal process activates the carbon atoms to form Si _x C _1-x compounds 3615 at the boundaries of the deep body region 3630 . The silicon carbide layer 3615 acts as a diffusion barrier layer against boron diffusion. The resulting deep body junction is a shallow layer that allows the thickness of the epitaxial layer 3606 to be reduced. Yet another junction in a typical trench transistor that benefits from a barrier layer is the well-drift region junction. A simplified example of an embodiment using such a barrier layer is shown in FIG. 37 . In the exemplary process flow for the structure of Figure 31M, a p-well is formed between the two steps shown in Figures 31H and 31I. Carbon is first implanted before implanting the well dopant (p-type in this exemplary n-channel embodiment). A subsequent thermal process activates the carbon atoms to form a Si _x C _1-x layer 3715 at the p-well epitaxial junction. Layer 3715 acts as a diffusion barrier layer to prevent boron diffusion so that the depth of p-well 3704 can be maintained. This helps reduce the channel length of the transistor without increasing the punch-through potential. Punchthrough occurs when the advancing loss boundary reaches the source junction with increasing drain-source voltage. Layer 3715 can also prevent punch through by acting as a diffusion barrier layer.

As mentioned above, it is desirable to reduce the channel length of transistors because it results in a reduction in on-resistance. In another embodiment, the transistor channel length is minimized by using epitaxially grown silicon to form the well region. That is, instead of the conventional method of forming a well with respect to the implanted drift epitaxial layer before the diffusion step, a well region is formed on top of the epitaxial drift layer. Besides the shorter channel length that can be obtained from the epitaxial-well formation, there are other advantages. For example, in a shielded gate trench transistor, the distance the gate electrode extends at the bottom of the well contacting the trench (gate to drain overlap) is important in determining the gate charge _Qgd . The gate charge Q _gd directly affects the switching speed of the transistor. Therefore, it is desirable to be able to precisely minimize and control this distance. However, it is difficult to control this distance, for example, in the fabrication process of well implantation and diffusion into the epitaxial layer shown in FIG. 31I described above.

In order to better control the gate-to-drain overlay at the corners of the wells, various methods have been proposed for forming trench devices with self-aligned wells. In one embodiment, the deposition process flow involving the epitaxial layer-well enables self-alignment of the bottom of the body junction with the bottom of the gate. Referring to Figures 38A to 38D, a simplified process flow for one example of a self-aligned epi-well trench device with buried electrodes (or shielded gates) is shown. Trenches 3802 are etched into first epitaxial layer 3806 formed on top of substrate 3814 . For n-channel transistors, substrate 3814 and first epitaxial layer 3806 are n-type material.

FIG. 38A shows a shielding dielectric layer 3808S grown on top of the epitaxial layer 3806 including the inner trench 3802 . Then, as shown in FIG. 38B , a conductive material 3811 (eg, polysilicon) is deposited in the trench 3802 and etched back under the epitaxial mesas. Additional dielectric material 3809S is deposited to cover the shielding polysilicon 3811. After etching back the dielectric layer to clean the mesas, a second epitaxial layer 3804 is selectively grown on top of the first epitaxial layer 3806, as shown in FIG. 38C. The mesas formed by the epitaxial layer 3804 create a trench upper portion above the original trench 3802 as shown. This second epitaxial layer 3804 has a dopant of opposite polarity (eg, p-type) to that of the first epitaxial layer 3806 . The doping concentration of the second epitaxial layer 3804 is set to a desired level for the well region of the transistor. After the selective epitaxial growth (SEG) step to form layer 3804, a gate dielectric layer 3808G is formed on the top surface and along the trench sidewalls. Then, as shown in Figure 38D, a gate conductive material is deposited, filling the remainder of the trench 3802, and then planarization is performed. For example, the process flow shown in Figures 31J to 31M is continued to complete the transistor structure.

This process forms gate polysilicon 3810 self-aligned with well epitaxial layer 3804 as shown in FIG. 38D . To lower the bottom of the gate polysilicon 3810 below the epitaxial well 3804, the upper surface of the interpoly dielectric layer 3809S shown in FIG. 38C may be slightly etched into the desired location within the trench 3802. Thus, the process provides precise control over the distance between the gate electrode and the corner of the well. Those skilled in the art will understand that the SEG well formation process is not limited to shielded gate trench transistors, but can be used in many other trench gate transistor structures, many of which have been described herein. Other methods of forming SEG mesas are described in commonly assigned US Patent Nos. 6,391,699 to Madson et al. and 6,373,098 to Brush et al., the entire contents of which are hereby incorporated by reference.

An alternative method for controlling the corners of self-aligned wells does not rely on the formation of SEG wells, but instead uses a process involving angled well implants. An exemplary process flow for this embodiment is shown in Figures 39A and 39B. In this embodiment, instead of forming the well after trench filling the gate polysilicon shown (eg, in FIGS. A first well implant is performed 3905 in a given portion prior to the remainder of the trench. A second but angled well implant is then performed through the sidewalls of trench 3902, as shown in FIG. 39B. Then, a drive cycle is completed to obtain the desired profile of the well-to-drift epitaxial interface at the trench corners. Depending on the structural requirements of the device, details of the implant does, energy, and drive cycle will vary. This technique can be used in many different device types. In an alternative embodiment, the trench tilt and angle implant are adjusted so that when the angle implant diffuses, it merges with regions of adjacent cells to form a continuous well, eliminating the need for a first well implant.

Another embodiment of a self-aligned epitaxial well process for forming trench devices is described with reference to Figures 40A through 40E. As mentioned above, in order to reduce the gate-drain capacitance, some trench-gated transistors use a gate dielectric layer, wherein the gate dielectric layer is thicker at the bottom of the trench under the gate polysilicon than along the inner vertical The thickness of the dielectric layer on the sidewall. According to the exemplary process embodiment shown in FIGS. 40A to 40E , a dielectric layer 4008B is first formed on top of the epitaxial drift layer 4006 as shown in FIG. 40A . The dielectric layer 4008B is formed to have a desired thickness, and then, as shown in FIG. 40B , the dielectric layer 4008B is etched such that a dielectric pillar remains with the same width as the subsequently formed trench. Next, in FIG. 40C, a selective epitaxial growth step is performed to form a second epitaxial drift layer 4006-1 around the dielectric pillar 4008B. The second epitaxial drift layer 4006-1 has the same conductivity type as the first epitaxial drift layer 4006 and may be the same material. Optionally, other types of materials may also be used for the second epitaxial drift layer 4006-1. In one exemplary embodiment, the second epitaxial drift layer 4006-1 is formed by a SEG step using a silicon germanium ( _{SixGe1 -x} ) alloy. The SiGe alloy improves carrier mobility in the accumulation region near the bottom of the trench. This improves the switching speed of the transistor and reduces R _DSon . Other compounds such as GaAs or GaN may also be used.

As shown in FIGS. 40D and 40E respectively, a covering epitaxial well layer 4004 is formed on the upper surface, and then, the epitaxial well layer 4004 is etched to form trenches 4002 . This is followed by formation of a gate oxide layer and deposition of gate polysilicon (not shown). The final structure is a trench gate with self-aligned epitaxial wells. The remaining process steps can be accomplished using conventional processing techniques. Those skilled in the art will appreciate that modifications can be made. For example, instead of forming an overlying epitaxial well layer 4004 and then etching the trench 4002, the epitaxial well 4004 can be selectively grown only on top of the second drift epitaxial layer 4006-1, forming the trench 4002 as it grows.

The various processing techniques described above enhance device performance by focusing on well formation to reduce channel length and R _DSon . Similar performance enhancements can also be achieved by improving other aspects of the process flow. For example, by reducing the substrate thickness, the impedance of the device can be further reduced. Therefore, in order to reduce the thickness of the substrate, a wafer thinning process is commonly performed. Wafer thinning is typically performed by mechanical grinding and tape processes. Grinding and tape handling apply mechanical forces to the wafer, causing damage to the wafer surface, which leads to manufacturing difficulties.

In one embodiment described below, an improved wafer thinning process significantly reduces substrate resistance. One method for reducing the thickness of the substrate is shown in Figures 40R, 40S, 40T and 40U. After completion of the desired circuitry on the wafer, the top of the wafer on which the circuitry is fabricated is temporarily adhered to the carrier. FIG. 40R shows the completed wafer 4001 adhered to a carrier 4005 by an adhesive material 4003 . The backside of the finished wafer is then polished to the desired thickness using processes such as grinding, chemical etching, and the like. FIG. 40S shows a sandwich structure similar to that shown in FIG. 40R , with a thinned wafer 4001 . After polishing the backside of the wafer 4001, the backside of the wafer is adhered to a low impedance (eg, metal) wafer 4009 as shown in FIG. 40T. These steps can be accomplished using conventional methods such as adhering the metal wafer 4009 to the thinned wafer 4001 using a thin coating of solder 4007 under temperature and pressure. The carrier 4005 is then removed and the upper surface of the thinned wafer 4001 is cleaned before further processing. The highly conductive metal substrate 4009 helps dissipate heat, reduce impedance and provide mechanical strength to the thinned wafer.

By using chemical processing to perform the final thinning process, alternative embodiments achieve thinner wafers without the disadvantages of traditional mechanical processing. According to this embodiment, active devices are formed on a silicon layer of a silicon-on-thick-glass (SOTG) substrate. During the grinding stage, the wafer can be thinned by chemically etching away the glass on the backside of the SOTG substrate. FIG. 41 shows an exemplary process flow according to this embodiment. Starting from the silicon substrate, first in step 4110 dopants such as He or _H2 are implanted into the silicon substrate. Then, at 4112, the silicon substrate is adhered to the glass substrate. Different adhesion treatments can be used. In one example, a silicon wafer and a glass wafer are sandwiched and heated to approximately 400°C to bond the two substrates. The glass may be silicon dioxide or the like, and may have a thickness of, for example, about 600um. Next, in step 4114, a silicon substrate is optionally attached and a silicon-on-thick-glass SOGT substrate is formed. To protect the substrate from stress during processing and subsequent handling, the bonding process may be repeated to form a SOGT substrate on the other side of the substrate (step 4116). Next, an epitaxial layer is deposited on the silicon surface of the substrate (step 4118). In addition to the front side, it can also be performed on the back side. Preferably, the doping concentration of the backside of the epitaxial layer is similar to that of the backside silicon, while the doping concentration of the frontside epitaxial layer follows the concentration required by the device. The substrate then undergoes various steps of the fabrication process for forming active devices on the front side silicon layer.

In one embodiment, to further enhance the substrate's strength against stresses introduced by the front-side processing steps, the backside substrate can be patterned to approximate the reverse structure of the front-side die frame. In this way, the glass substrate is etched into the mesh grid to help the thin substrate support the stress in the wafer. After grinding, the silicon layer is first removed from the rear side by a conventional grinding process (step 4120). Another grinding step 4122 follows, removing a portion (eg, half) of the glass substrate. Then, the remaining portion of the glass substrate is removed by a chemical etching process using, for example, hydrofluoric acid. Etching of the rear glass substrate can be performed without risk of corroding the active silicon layer or causing mechanical damage. This eliminates the need to tape wafers, the need for tape and re-tape equipment and the process risk associated with each operation. Therefore, such a process enables further minimization of substrate thickness to enhance device performance. It should be understood that there are many variations of this which improve the wafer thinning process. For example, depending on the desired thickness of the final substrate, the thinning step may or may not involve grinding, since chemical etching is sufficient. In addition, the improved wafer thinning process is not limited to the processing of discrete devices, but can also be applied in the processing of other types of devices. Other wafer thinning processes are described in commonly assigned US Patent No. 6,500,764 to Pritchett, which is incorporated herein in its entirety.

There are other structural and processing aspects of many power transistors and other active devices that can significantly affect their performance. The shape of the trench is an example. To reduce potentially damaging electric fields that tend to concentrate around the corners of trenches, it is desirable to avoid sharp corners and instead form trenches with rounded corners. To improve reliability, it is also desirable to achieve trench sidewalls with smooth surfaces. Different etch chemistries have different results (e.g., silicon etch rate, mask layer selectivity, etch profile (sidewall angle), top corner fillet, sidewall roughness, and trench bottom fillet) provides balance. Fluoride (eg, SF ₆ ) provides high silicon etch rates (greater than 1.5um/min), rounded trench bottoms, and straight sides. Fluoride disadvantages are rough sidewalls and difficulty in trench top control (can be recessed). Chloride (eg, _Cl2 ) provides smoother sidewalls, and better control of the etch profile and trench top. Chloride has the disadvantage of having a lower silicon etch rate (less than 1.0um/min), and less fillet at the bottom of the trench.

Additional gases may be added to the etch chemistry to help passivate the sidewalls during etching. Sidewall passivation is used to minimize side etch to the desired trench depth. Additional processing steps may be used to smooth the trench sidewalls and to achieve rounding of the trench top corners and bottom. The surface quality of the trench sidewalls is important because it affects the quality of the oxide layer that can grow on the trench sidewalls. Regardless of the chemistry used, a breakthrough step is typically used prior to the main etch step. The purpose of the breakthrough step is to remove any native oxide on the silicon surface that could mask the silicon etch during the main etch step. Typical through etch chemistries are _CF4 or _Cl2 .

One embodiment for the improved etch process shown in Figure 42A uses a chlorine based main silicon trench etch followed by a fluorine based etch step. One example of such a process uses a _Cl2 /HBr main etch step followed by a _SF6 etch step. The chlorination step is used to etch portions of the main trench to the desired depth. This produces trench sides that are somewhat tapered and have smooth sidewalls. A subsequent fluorination step is used to etch the remainder of the trench depth, round the trench bottom, and provide further smoothing of any suspended silicon bonds adhering to the trench sidewalls. Preferably, the fluoride etch step is performed under conditions of relatively low fluorine flow, low pressure, and low power to control smoothing and rounding. Due to the difference in etch rates between the two etch chemistries, the timing of the two steps can be balanced to achieve a more reliable and manufacturable process with acceptable total etch times while maintaining desired trench sides, sidewalls roughness, and groove bottom rounding.

In another embodiment shown in FIG. 42B, an improved method for silicon etching includes a main fluorine-based etch step followed by a second chlorine-based etch step. One example of this process uses a SF ₆ /O ₂ main etch step followed by a Cl ₂ etch step. The fluorination step is used to etch most of the depth in the main trench. This step produces trenches with straight sidewalls and rounded trench bottoms. Optionally, oxygen can be added to this step to provide sidewall passivation and to help maintain straight sidewalls by reducing side etch. A subsequent chlorination step rounds the top corners of the trenches and reduces sidewall roughness. The high silicon etch rate of the fluorination step increases the manufacturability of the process by increasing the overall throughput of the etch system.

In yet another embodiment shown in Figure 42C, an improved silicon etch process is obtained by adding argon to the fluorine-based chemistry. An example of a chemistry for the main etch step according to this embodiment is SF ₆ /O ₂ /Ar. The addition of argon to the etching step increases the ion bombardment, thus making the etching more physical. This helps control the top of the trench and eliminates the tendency for the top of the trench to recede. The additional argon also increases the fillet of the bottom of the trench. An additional etch process can be used to smooth the sidewalls.

As shown in Figure 42D, an alternative embodiment for an improved silicon etch process uses fluorine based chemistry to remove oxygen from the main etch step. One example of this process uses a SF ₆ step followed by a SF ₆ /O ₂ step. In the first stage of etching, sidewall passivation is lacking due to the absence of _O2 . The consequence of this is an increase in the amount of side etch at the top of the trench. Then, the second etch step, SF ₆ /O ₂ , continues to etch the remaining trench depth, resulting in straight sides and a rounded trench bottom. This results in a wider top in a trench structure, sometimes called a T-trench. An example of a device using a T-trench structure is found in commonly assigned U.S. Patent Application No. 10/442,670, entitled "Structure and Method for Forming a Trench MOSFET Having Self-Aligned Features," by Herrick (Attorney Docket No. 18865-131/17732-66850 ) are described in detail, the entire contents of which are hereby incorporated by reference. The period for the two main etch steps can be adjusted to achieve the desired thickness of each part of the T-trench (top T part, bottom smooth sidewall part). Additional processing may be used to round the top corners of the T-groove and smooth the trench sidewalls. These additional treatments may include, for example: (1) a fluorine-based step at the end of the trench etch process, or (2) a separate fluoride-based etch in a separate etch system, or (3) a sacrificial oxide, or any other combination. A chemical mechanical planarization (CMP) step may be used to remove the top re-indentation of the trench sides. An _H2 anneal can also be used to aid in rounding and to create favorable sloped trench sides.

For high voltage applications where trenches tend to be deeper, there are additional considerations. For example, silicon etch rate is important to produce a manufacturable process due to deeper trenches. Etch chemistries used for this application are typically fluorinated chemistries because chlorinated etch chemistries react too slowly. Straight to tapered trench profiles with smooth sidewalls are also desirable. Due to the depth of the trenches, the etch process also needs to be very selective to the mask layer. If the selectivity is poor, then a thicker mask layer is required, which increases the overall aspect ratio. Sidewall passivation is also very critical and requires a precise balance. Too much sidewall passivation will narrow the bottom of the trench to the point where it closes, too little sidewall passivation will result in increased side etch.

In one embodiment, a deep trench etch process that optimally balances all of these requirements is provided. According to this embodiment, shown in Figure 42E, the etch process includes a fluorine-based chemistry with ramped _O2 , ramped power, and/or ramped pressure. One exemplary embodiment uses the SF ₆ /O ₂ etch step in a manner that maintains the etch profile and silicon etch rate through the etch. By grading _O2 , the amount of sidewall passivation through the etch can be controlled to avoid increased side etch (in the case of too little passivation) or pinch-off of the trench bottom (in the case of too much passivation). An example of using fluorine-based etching with graded oxygen flow is described in detail in Grebs et al., US Patent No. 6,680,232, entitled "Integrated Circuit Trench Etch with Incremental Oxygen Flow," which is incorporated herein by reference. Grading of power and pressure helps to control ion flux density and maintain silicon etch rate. If the silicon etch rate decreases significantly during etching as the trenches are etched deeper, the total etch time will increase. This results in low wafer throughput of the etcher. Additionally, graded _O2 can help control the choice of mask material. An example process according to this embodiment for trenches deeper than, say, 10um may have an _O2 flow rate of 3 to 5 sccm per minute, a power level of 10-20 watts per minute, and a pressure level of 2-3 mT per minute .

An alternative embodiment of the deep trench etch process uses a more aggressive fluorine-based chemistry (eg, _NF3 ). Since NF ₃ is more reactive than SF ₆ for silicon etching, increased silicon etch rates can be achieved with the NF ₃ process. Additional gas needs to be added for sidewall passivation and profile control.

In another embodiment, the NF ₃ etch step is followed by a SF ₆ /O ₂ treatment. According to this embodiment, the NF ₃ step is used to etch most of the trench depth at a high silicon etch rate. Then, a SF ₆ /O ₂ etch step is used to passivate the existing trench sidewalls and etch the remainder of the trench depth. In a modification of this embodiment shown in Figure 42F, the NF ₃ and SF ₆ /O ₂ etch steps are performed in an alternating fashion. This results in a process with a higher silicon etch rate than the direct SF ₆ /O ₂ process. This achieves a balance between a fast etch rate step (NF ₃ ) and a step that creates sidewall passivation for profile control (SF ₆ /O ₂ ). The balance of steps controls the roughness of the sidewalls. For the etched SF ₆ /O ₂ portion, graded O ₂ , power, and pressure are also required to maintain the silicon etch rate and create sufficient sidewall passivation to help control the etch profile. Those skilled in the art should understand that the various process steps described in connection with the above embodiments can be combined in different ways to achieve an optimal trench etching process. It should be understood that these trench etch processes may be used for any trench in any of the power devices described herein, as well as any other type of trench used in other types of integrated circuits.

Prior to the trench etch process, a trench etch mask is formed on the silicon surface and patterned to expose regions to be trenched. As shown in FIG. 43A, in a typical device, trench etching first etches through a nitride layer 4305 and a thin pad oxide layer 4303 before etching the silicon substrate. The pad oxide layer 4303 may also grow at the edge of the trench lifting the stacked nitride layer after the trench is formed during formation of the oxide in the trench. This creates a structure 4307 commonly referred to as a "bird's beak", ie, the pad oxide layer grows locally close to the edge of the trench under the nitride layer 4305. The source region that will subsequently be formed at the edge of the trench immediately under the pad oxide with the bird's beak structure will be shallow near the trench. This is highly undesirable. To eliminate the bird's beak effect, in one embodiment, shown in FIG. 43B , a layer 4309 of non-oxidizing material (eg, polysilicon) is sandwiched between the nitride layer 4305 and the pad oxide layer 4303 . Polysilicon layer 4309 protects pad oxide layer 4303 from further oxidation during subsequent trench oxide formation. In another embodiment, shown in FIG. 44A, after etching through the nitride layer 4405 and pad oxide layer 4403 defining the trench opening, a thin layer of non-oxidizing material such as nitride is formed on the substrate structure. 4405-1. Then, as shown in FIG. 44B, the protective layer 4405-1 is removed from the horizontal surfaces, leaving an isolation layer along the vertical edges of the nitride-pad oxide structure. The nitride isolation layer protects the pad oxide layer 4403 from being further oxidized in subsequent steps, reducing the bird's beak effect. In alternative embodiments, to reduce the extent of any beak formation, the embodiments shown in Figures 43B and 44B may be combined. That is, in addition to the spacer layer created from the process described in connection with Figures 44A and 44B, a polysilicon layer may also be sandwiched between the pad oxide layer and the overlying nitride layer. Other modifications are possible, such as adding another layer (eg, an oxide layer) on top of the nitride layer to aid in nitride selectivity when etching silicon trenches.

As described above in connection with various transistors having a shielded gate structure, the layer of dielectric material insulates the shield electrode from the gate electrode. This inter-electrode dielectric, sometimes referred to as an inter-polysilicon dielectric or IPD, must be formed in a robust and reliable manner such that it can withstand the potential difference that exists between the shield electrode and the gate electrode. Referring back to Figures 31E, 31F and 31G, simplified flows for the relevant process steps are shown. After etching back the shielding polysilicon 3111 in the trench (FIG. 31E), the shielding dielectric layer 3108 is etched back to the same extent as the shielding polysilicon 3111 (FIG. 31F). Then, as shown in FIG. 31G, a gate dielectric layer 3108a is formed on the upper surface of the silicon. It is the step of forming the IPD layer. The artefact of the shield dielectric recess etch is the formation of shallow trenches on the upper surface of the remaining shield dielectric layer on either side of the shield electrode. This is shown in Figure 45A. Structures that end up with uneven topography can cause consistency issues, especially with subsequent filling steps. In order to eliminate such problems, various improved methods for forming IPDs have been proposed.

According to one embodiment, after the shield dielectric recess etch, a polysilicon liner 4508P is deposited using, for example, a low pressure chemical vapor deposition (LPCVD) process, as shown in Figure 45B. Alternatively, the polysilicon liner 4508P may be formed only over the shielding polysilicon and shielding dielectric layer by using a selective growth process of polysilicon or aligned polysilicon sputtering such that the trench sidewalls are substantially free of polysilicon. The polysilicon liner 4508P is then oxidized and converted to silicon dioxide. This can be performed by conventional thermal oxidation treatment. In embodiments where no polysilicon is formed on the trench sidewalls, this oxidation process also forms gate dielectric layer 4508G. In addition, as shown in FIG. 45C , after etching polysilicon oxide from the trench sidewalls, a thin gate dielectric layer 4508G is formed, and the remaining trench cavity fills the gate electrode 4510 . The advantage of this process is that the polysilicon is deposited in a very conformal manner. This minimizes voids and other defects, and creates a more planar surface once the polysilicon is deposited on top of the shield dielectric and shield electrodes. The result is an improved IPD layer that is more robust and reliable. By placing the polysilicon along the trench sidewalls and adjacent silicon surface regions prior to oxidation, the subsequent oxidation step will result in less mesa loss and minimize unwanted trench widening.

In an alternative embodiment, shown in simplified cross-sectional view in FIGS. 46A, 46B and 46C, the cavity created by the shield polysilicon recess etch within the trench is filled with a dielectric fill material 4608F, wherein the dielectric fill material 4608F has the same etch rate as shielding dielectric layer 4608S. This step can be performed using any of high-density plasma (HDP) oxide deposition, chemical vapor deposition (CVD), or spin-on-glass (SOG) processing, followed by a planarization step to obtain a planar surface at the top of the trench . Then, as shown in FIG. 46B , dielectric fill material 4608F and shield dielectric material 4608S are collectively etched back such that a layer of insulating material having the necessary thickness remains on shield electrode 4611 . Then, as shown in FIG. 46C , after disposing the gate dielectric material along the trench sidewalls, the remaining trench cavity is filled with the gate electrode. The result is a highly conformal IPD layer that avoids conformational inconsistencies.

An exemplary embodiment of another method for forming a high quality IPD is shown in simplified cross-sectional view in FIGS. 47A and 47B . After forming the shielding dielectric layer 4708S in the trench and filling the cavity with the shielding polysilicon, a shielding polysilicon etch back step is performed to recess the shielding polysilicon in the trench. In this embodiment, the shield poly recess etch leaves more poly within the trench such that the upper surface of the recessed shield poly is higher than the final target depth. The thickness of the extra polysilicon on the upper surface of the shield polysilicon is designed to be about the same thickness as the target IPD. Then, the upper part of the shield electrode is physically or chemically altered to further enhance its oxidation rate. The method of chemically or physically altering the electrodes may be performed by ion-implanting impurities (eg, fluorine or argon ions) into the polysilicon to enhance the oxidation rate of the shield electrodes, respectively. Preferably, as shown in Figure 47A, this implant is performed at zero degrees, ie, perpendicular to the shield electrode, so as not to physically or chemically alter the trench sidewalls. Next, the shielding dielectric layer 4708S is etched to remove the dielectric layer from the trench sidewalls. This shield dielectric recess etch creates a slight indentation in the remaining shield dielectric layer adjacent to shield electrode 4711 (similar to that shown in FIG. 45A ). A conventional oxidation step follows, whereby the upper portion of the shield electrode 4711 change is oxidized at a faster rate than the trench sidewalls. This results in the formation of a sufficiently thick insulating layer 4708T over the shield electrode rather than along the sidewalls of the trench silicon surface. The thicker insulating layer 4708T over the shield electrode forms the IPD. The modified lateral oxidation of the polysilicon compensates for some of the trenches formed on the upper surface of the shielding dielectric layer due to the shielding dielectric recess etch. Conventional steps are then performed to form gate electrodes in the trenches, resulting in the structure shown in Figure 47B. In one embodiment, the shield electrode is varied to obtain an IPD to gate oxide thickness ratio ranging from 2:1 to 5:1. For example, if a 4:1 ratio is selected, for approximately 2000 angstroms of IPD formed on the shield electrode, approximately 500 angstroms of gate oxide will be formed along the trench sidewalls.

In alternative embodiments, a physical or chemical altering step is performed after the shield dielectric recess etch. That is, the shield oxide layer 4708S is etched to remove the oxide from the trench sidewalls. This discloses a method in which the above-mentioned upper portion of the shield electrode and the silicon are physically or chemically altered. Since the trench sidewalls are exposed, the modification step is limited to the horizontal surfaces, ie only the silicon mesas and shield electrodes. The modification method (eg, ion implantation of dopants) is to be performed at zero degrees (perpendicular to the shield electrode) so as not to physically or chemically modify the trench sidewalls. Then, conventional methods are performed to form the gate electrode in the trench, thus creating a thicker dielectric layer over the shield electrode.

Yet another method for forming an improved IPD layer is shown in FIG. 48 . According to this embodiment, a thick insulating layer 4808T made of, for example, oxide is formed over the recessed shield oxide layer 4808S and the shield electrode 4811 . Thick insulating layer 4808T is preferably formed using a directional deposition technique such as high density plasma (HDP) deposition or enhanced plasma chemical vapor deposition (PECVD) (ie, "bottm up fill"). As shown in Figure 48, the deposition is oriented such that a sufficiently thick insulating layer is formed along the horizontal plane (ie, above the shield electrode and shield oxide), rather than along the vertical plane (ie, along the trench sidewalls). . An etch step is then performed to remove oxide from the sidewalls while leaving sufficient oxide on the shield polysilicon. Then, conventional steps are performed to form a gate electrode in the trench. In addition to obtaining a conformal IPD, this embodiment has the advantage of preventing mesa loss and trench widening because the IPD is formed by a deposition process rather than an oxidation process. Another advantage of this technique is the rounding of the upper corners of the grooves.

In another embodiment, a thin masking oxide layer 4908P is grown in the trenches after the masking dielectric layer or masking polysilicon is recessed. Then, as shown in Figure 49A, a silicon nitride layer 4903 is deposited overlying the masking oxide layer 4908P. The silicon nitride layer 4903 is then non-uniformly etched away from the bottom of the trench (ie, above the shield electrode) and not from the sidewalls of the trench. The final structure is shown in Figure 49B. Then, as shown in Figure 49C, the wafer is exposed to an oxidizing environment such that a thick oxide layer 4908T is formed on the shielded polysilicon surface. Since the nitride layer 4903 cannot be oxidized, no significant oxide growth occurs along the trench sidewalls. Then, the nitride layer 4903 is removed by wet etching using, for example, strong phosphoric acid. As shown in FIG. 49D, conventional process steps follow to form a gate oxide layer and a gate dielectric layer.

In some embodiments, the formation of the IPD layer involves an etching process. For example, for embodiments where the IPD film is deposited over topography, a thin layer that is much thicker than the desired final IPD thickness may be deposited first. Doing so enables to obtain planar thin layers to minimize the notching of the initial layer into the trenches. Etching can then completely fill the trench and the thicker thin layer extending over the silicon surface to reduce its thickness to the target IPD layer thickness. According to one embodiment, this IPD etch process is performed with a minimum of two etch steps. The first step is to planarize the thin layer onto the silicon surface. In this step, the uniformity of etching is very important. The second step is to recess the IPD layer to the desired depth (and thickness) within the trench. In this second step, the etch selectivity of the IPD layer to silicon is important. The silicon mesas are exposed during the recess etch step, and the silicon trench sidewalls are recessed into the trench as is the IPD layer. Any losses on the mesa will affect the actual trench depth and, if included, the T-trench depth.

In one exemplary embodiment shown in Figure 50A, an anisotropic plasma etch step 5002 is used to planarize the IPD layer down to the silicon surface. An exemplary etch rate for plasma etching may be 5000 A/min. An isotropic wet etch step 5004 follows to recess the IPD into the trench. Preferably, the etch back is performed using a controllably silicon selective solution so as not to corrode the silicon sidewalls when exposed, and to provide repeatable etching to obtain precise groove depths. An exemplary chemistry for wet etching may be a 6:1 buffered oxide etch (BOE), resulting in an etch rate of approximately 1100 A/min at 25°C. Details for exemplary plasma and wet etch methods suitable for this process are provided in commonly assigned US Patent No. 6,465,325 to Rodney Risley, the entire contents of which are hereby incorporated by reference. The first plasma etch step for planarization has fewer grooves for the IPD layer above the trenches than wet etch. The second wet etch step for the recess etch results in better silicon selectivity and less damage to the silicon than plasma etch. In an alternative embodiment shown in Figure 50B, a chemical mechanical planarization (CMP) process is used to planarize the thin layer of IPD down to the silicon surface. This is followed by a wet etch to recess the IPD into the trench. The CMP process results in less grooves in the IPD layer above the trenches. The wet etch step for the recess etch results in better silicon selectivity and less damage to the silicon than CMP. Other combinations of these treatments are also possible.

In addition to IPD, it is desirable to form high-quality insulating layers in the structure, including trench and planar gate dielectric layers, interlayer dielectric layers, and the like. The most commonly used dielectric material is silicon dioxide. There are several parameters that define a high quality oxide film. Mainly uniform thickness, good integrity (low interface trap density), high electric field breakdown strength, and low drain level. One factor affecting many of these properties is the rate of oxide growth. It is desirable to be able to precisely control the growth rate of the oxide. During thermal oxidation, charged particles on the wafer surface generate a gas phase reaction. In one embodiment, the method for controlling the rate of oxidation is accomplished by influencing charged particles, typically silicon and oxygen, to reduce or increase the rate of oxidation by applying an external voltage to the wafer. This differs from plasma-enhanced oxidation in that no plasma (with active species) is formed over the wafer. Furthermore, according to this embodiment, the gas is not accelerated towards the surface, it is merely prevented from reacting with the surface. In an exemplary embodiment, a reactive ion etching (RIE) chamber with high temperature capability may be used to adjust the desired energy level. The RIE chamber is not used for etching, but for applying a DC bias to control the energy required to slow and stop oxidation. Figure 51 is a flowchart for an exemplary method according to this embodiment. First, the RIE chamber is used to DC bias the wafer under test conditions (5100). After determining the potential energy required to inhibit the surface reaction (5110), an external bias voltage large enough to prevent oxidation is applied (5120). Then, by controlling the external bias voltage (eg, pulsing or other methods), the rate of oxidation at an average very high temperature can be controlled (5130). This approach enables the advantages of high temperature oxidation (better oxide flow, lower stress, elimination of differential growth of various crystal orientations, etc.) without the disadvantages of fast and non-uniform growth.

While techniques such as those described above in connection with FIG. 51 can improve the quality of the resulting oxide layer, reliability issues with the oxide remain, especially in trench gate devices. One of the main degradation problems is due to the high electric field at the trench corners, where the electric field is generated by the local thinning of the gate oxide at these points. This results in high gate leakage current and low gate oxide breakdown voltage. This effect becomes more dramatic with further proportional reductions in on-resistance in trench devices, and with reduced gate voltage requirements, resulting in thinner gate oxides.

In one embodiment, gate oxide reliability issues are addressed by using a dielectric material with a greater dielectric constant than silicon dioxide (high-K dielectric). This allows equal threshold voltage and transconductance with very thick dielectrics. According to this embodiment, the high-K dielectric reduces gate leakage current and increases the breakdown voltage of the gate dielectric without reducing the on-resistance or drain breakdown voltage of the device. High-K materials (including Al ₂ O ₃ , HfO ₂ , Al _x HfyO _z , TiO ₂ , ZrO _{2 ,} etc.) that exhibit the required thermal stability and suitable density of interfacial states will be integrated within trench gates and other power devices .

As mentioned above, in order to improve the switching speed of trench-gate power MOSFETs, it is desirable to minimize the transistor gate-drain capacitance _Cgd . Using a thicker dielectric layer at the bottom of the trench compared to the sidewalls of the trench is one of several methods mentioned above for reducing _Cgd . One method for forming a thick bottom oxide layer involves forming a thin layer of masking oxide along the sidewalls and bottom of the trench. The thin oxide layer is then covered by a layer of oxidation inhibiting material (eg, nitride). The nitride layer is then anisotropically etched such that all of the nitride is removed from the horizontal floor of the trench, but the trench sidewalls remain coated with the nitride layer. After removing the nitride from the bottom of the trench, an oxide layer with a desired thickness is formed on the bottom of the trench. Thereafter, a thinner channel oxide layer is formed after removal of the nitride layer and masking oxide from the trench sidewalls. This method for forming a thick bottom oxide layer and modifications thereto are described in more detail in commonly assigned US Patent No. 6,437,386 to Hurst et al., which is incorporated herein in its entirety. Other methods involving selective oxide deposition for forming thick oxide layers at the bottom of trenches are described in commonly assigned US Patent No. 6,444,528 to Murphy, which is incorporated herein in its entirety.

In one embodiment, an improved method of forming a thick oxide layer at the bottom of the trench uses a low pressure chemical vapor deposition (SACVD) process. According to the method, an exemplary flow chart shown in FIG. 52, after etching the trenches (5210), SACVD is used to deposit a highly conformal oxide layer (5220), for example using tetraethyl orthosilicate (TEOS) on A filled trench with no voids in the oxide. The SACVD step may be performed under conditions of low gas pressure ranging from 100 Torr to 700 Torr, and an exemplary temperature range from about 450°C to about 600°C. For example, the ratio of TEOS (in mg/min) to Ozone (in cm ³ /min) can be set in the range of 2 to 3, preferably about 2.4. Using this process, an oxide layer can be formed with a thickness between approximately 2000 Angstroms and 10,000 Angstroms. It should be understood that these data are for illustrative purposes only and may vary depending on specific process requirements and other factors (eg, air pressure at the manufacturing facility location). The optimum temperature can be obtained by balancing the deposition rate and the quality of the oxide layer formed. At higher temperatures, the deposition rate slows down, which reduces the shrinkage of the thin layer. Such thin layer shrinkage can cause a gap to form in the oxide layer in the center of the trench along the crack.

After depositing the oxide layer, etch back from the silicon surface and within the trench to form a relatively flat oxide layer of desired thickness at the bottom of the trench (5240). This etching may be performed by a wet etching process, or a combination of wet and dry etching, for example using dilute HF. Since the oxide formed by SACVD is permeable, it absorbs the surrounding moisture after deposition. In a preferred embodiment, a densification step 5250 is performed following etch back to improve this effect. For example, the densification step may be performed by temperature treatment at, for example, 1000° C. for about 20 minutes.

Another advantage of this method is the ability to mask the termination trenches (step 5230 ) during the etch back step of the SACVD oxidation, leaving the termination trenches filled with oxide. That is, for the various embodiments of the termination structures described above (including trenches filled with dielectric material), the same SACVD step can be used to fill the termination trenches with oxide. Furthermore, by masking the field termination region during the etch back, the same SACVD process step can result in the formation of a field oxide layer in the termination region, eliminating the additional process steps required to form a thermal field oxide layer. Furthermore, this process provides additional flexibility as it allows for termination dielectric and thick bottom oxide in case of overetching due to silicon not being lost by thermal oxidation process but set in two places during SAVCD deposition complete reprocessing.

In another embodiment, another method for forming a thick oxide layer at the bottom of the trench uses a directional TEOS process. According to this embodiment, an exemplary flow chart is shown in FIG. 53, the conformal properties of TEOS are combined with the directional properties of plasma enhanced chemical vapor deposition (PECVD) to selectively deposit oxide (5310). This combination enables higher deposition rates on horizontal surfaces than on vertical surfaces. For example, an oxide layer deposited using this process may have a thickness of 2500 angstroms at the bottom of the trench and an average thickness of about 800 angstroms on the sidewalls of the trench. The oxide is then isotropically etched until all of the oxide is removed from the sidewalls, leaving an oxide layer at the bottom of the trench. The etch process may include a dry top oxide etch step 5320 followed by a wet buffered oxide etch (BOE) step 5340 . For the exemplary embodiments described herein, after etching, an oxide layer with a thickness of, for example, 1250 angstroms remains at the bottom of the trench, while all sidewall oxide is removed.

In certain embodiments, a dry top oxide etch is used focusing on the upper surface of the structure, etching the oxide in the top region at an accelerated rate and etching the oxide at the bottom of the trench at a much reduced rate. This type of etch, referred to herein as "fog etch," involves careful balancing of etch conditions and etch chemistries to produce the desired selectivity. In one example, this etching process is performed using a plasma etcher (eg, LAM 4400) with a top power supply at relatively low power and pressure. Example values for power and pressure may range between 200-500 Watts and 250-500 mTorr, respectively. Different etch chemistries can be used. In one embodiment, combining fluoride (eg, C2F6) and chlorine, mixed at an optimal ratio, eg, about 5:1 (eg, 190 seem for C2F6 and 40 seem for Cl), produces the desired selectivity. The use of chlorine as a partial oxidation etch chemical is uncommon because chlorine is more commonly used to etch metal or polysilicon, and it generally inhibits the etch of oxides. However, for the purpose of this type of selective etching, this combination works well because C2F6 etches very strongly the oxide close to the top surface, the higher energy allows C2F6 to overcome the influence of chlorine while being close to the bottom of the trench , chlorine slows down the etch rate. After this main dry etch step 5320, the BOE etch 5340 is preceded by a clean etch 5330. It should be appreciated that, according to this embodiment, optimal selectivity is achieved by minor adjustments in pressure, energy, and etch chemistry that may vary from plasma etcher to plasma etcher.

The PECVD/etch process according to this embodiment may be repeated one or more times if desired to obtain a bottom oxide layer with a target thickness. The process also results in the formation of a thick oxide layer on the horizontal lands between the trenches. The oxide layer may be etched after polysilicon is deposited in the trench and etched back on the surface, so that the oxide at the bottom of the trench is protected from subsequent etching steps.

There may be other methods for selectively forming a thick oxide layer at the bottom of the trench. 54 shows a flowchart of an exemplary method using high density plasma (HDP) deposition to prevent formation of an oxide layer on trench sidewalls (5410). A characteristic of HDP deposition is that it etches as it is deposited, forming less oxide on the trench sidewalls relative to the trench bottom compared to the directional TEOS approach. A wet etch is then used (step 5420) to remove some or clear the oxide from the sidewalls, leaving a thick oxide layer on the bottom of the trench. As shown in Figure 55, the advantage of this process is that the side slopes 5510 at the top of the trench are away from the trench 5500, making it easier to achieve non-porous polysilicon fill. The "mist etch" described above (step 5430) can be used to etch some oxide off the top before the polysilicon fill (step 5440), so that less oxide needs to be etched off the top after the polysilicon etch. The HDP deposition process can also be used to deposit oxide between two polysilicon layers in trenches with buried electrodes (eg, trench MOSFETs with shielded gate structures).

According to yet another approach shown in FIG. 56, a selective SACVD process is used to form a thick oxide layer on the bottom of the trench. This method exploits the ability of SACVD to become selective at lower TEOS:Ozone ratios. Oxide has a very slow deposition rate in silicon nitride, but can be deposited rapidly in silicon. The lower the ratio of TEOS to Ozone, the more selective the deposition becomes. According to the method, after etching the trenches (5610), a pad oxide layer is grown (5620) on the silicon surface of the trench array. Then, a thin layer of nitride is deposited on the pad oxide layer (5630). This is followed by an anisotropic etch to remove the nitride layer from the horizontal plane and leave the nitride layer on the trench sidewalls (5640). A selected SACVD oxide is then deposited (5650) on the level including the bottom of the trench, eg, at a TEOS:Ozone ratio of about 0.6, at about 405°C. The SACVD oxide is then optionally densified (5660) by temperature treatment. An oxide-nitride-oxide etch is then performed to remove nitride and oxide on the trench sidewalls (5670).

As mentioned above, one reason for using a thicker oxide layer at the bottom of the gate trench compared to the sidewalls of the trench is to reduce _Qgd or gate-drain charge which improves switching speed. The same reason specifies that the depth of the trench is about the same as the depth of the well junction, to minimize trench superposition into the drift region. In one embodiment, the method for forming the thick dielectric layer at the bottom of the trench extends the thick dielectric layer to the sides of the trench. This makes the thickness of the bottom oxide independent of the trench depth and well junction depth, and allows the polysilicon in the trench and trench to be deeper than the well junction without increasing Q _gd .

57 to 59 illustrate exemplary embodiments of forming a thick bottom dielectric layer according to this method. Figure 57A shows a simplified and partial cross-sectional view of a thin liner oxide layer 5710 and a nitride layer 5720 disposed along the trench after it has been etched to cover only the trench sidewalls. As shown in Figure 57B, this enables etching of the pad oxide layer 5710 to expose the silicon at the bottom of the trench and the upper surface of the die. This is followed by anisotropic etching of the exposed silicon, resulting in a structure as shown in Figure 58A, in which both the top silicon and the silicon at the bottom of the trench have been removed to the desired depth. In an alternative embodiment, the silicon of the upper surface may be masked such that during the silicon etch only the bottom of the trench is etched. Next, an oxidation step is performed to grow a thick oxide layer 5730 in locations not covered by the nitride layer 5720, resulting in the structure shown in Figure 58B. For example, the thickness of the oxide layer may be about 1200 angstroms to 2000 angstroms. Then, the nitride layer 5720 is removed, and the pad oxide layer 5710 is etched away. Etching of the pad oxide will cause some thinning of the thick oxide 5730. The remaining processes can use standard flows to form the gate electrode, well, and source junctions, resulting in the exemplary structure shown in FIG. 59 .

As shown in FIG. 59 , the final gate oxide includes a bottom thick layer 5730 extending along the sidewalls of the trench over the well junction in region 5740 . In some embodiments, where the channel doping in the well region next to the trench has less dopant near the drain side 5740, this region generally has a lower dopant than the region near the source. threshold voltage. Extending a thicker oxide layer along the trench sides of the trench superimposed into region 5740 will not increase the threshold voltage of the device. That is, this embodiment makes it possible to optimize well junction depth and sidewall oxide to minimize Q _gd without affecting the on-resistance of the device. Those skilled in the art should understand that the method of forming a thick oxide layer at the bottom of the trench can be applied to various devices described above, including shielded gates, double gates combined with various charge balance structures, and other trench gate devices.

Those skilled in the art will also appreciate that any of the processes described above for forming the thick oxide layer at the bottom of the trench and for the IPD can be used in the process for forming any of the trench-gate transistors described herein. Other modifications to these processes can be made. For example, chemical or physical changes to silicon can enhance its oxidation rate, as in the processes described in connection with Figures 47A and 47B. According to one such embodiment, halide ion species (eg, fluorine, bromine, etc.) are implanted into the silicon at the bottom of the trench at zero degrees. The implant may occur at an exemplary energy of about 15 KeV or less, an exemplary amount greater than 1E ¹⁴ (eg, 1E ¹⁵ to 5E ¹⁷ ), and an exemplary temperature between 900°C and 1150°C. In the halogen implanted region at the bottom of the trench, the oxide layer grows at an accelerated rate compared to the trench sidewalls.

The multiple trench devices described above include trench sidewall doping for charge balancing purposes. For example, all of the embodiments shown in FIGS. 5B and 5C , and FIGS. 6 through 9A have trench sidewall doping structures. Sidewall doping techniques have limitations due to physical constraints, deep trenches and/or vertical sidewalls of the trenches. Source gas or angled implants can be used to form trench sidewall doped regions. In one embodiment, the improved trench sidewall doping technique uses plasma doping or pulsed plasma doping technique. This technique utilizes a pulsed voltage applied to a wafer contained in a plasma doped with ions. The applied voltage accelerates the rate at which ions are implanted into the wafer from the cathode casing. The applied voltage is pulsed and continued until the desired result is achieved. This technique enables conformal doping techniques for many of these trench devices. Furthermore, the high throughput of the process reduces the overall cost of the manufacturing process.

Those skilled in the art should understand that plasma doping or pulsed plasma doping techniques are not limited to trench charge balance structures, but can also be applied to other structures, including trench termination structures and trench drain, source or body connections. For example, the method can be used to dope trench sidewalls of shielded trench structures such as those described in connection with FIGS. 4D, 4E, 5B, 5C, 6, 7, 8, and 9A. Additionally, this technique can be used to form uniformly doped channel regions. The penetration of the depletion region into the channel region (p-well junction) when the power device is reverse biased is controlled by charge concentration on both sides of the junction. Penetration into this junction can allow punch-through when the doping concentration of the epitaxial layer is high, limiting the breakdown voltage or requiring a channel longer than desired to maintain low on-resistance. To minimize channel penetration, a higher channel doping concentration may be required, which may result in a reduced threshold. Since this threshold is determined by the peak concentration below the source in a trench MOSFET, a uniform doping concentration in the channel can provide a better balance between channel length and breakdown voltage.

More uniform channel concentrations can be achieved using other methods, including using epitaxial processes to form channel junctions, using multiple energy implants, and other techniques for forming raised junctions. Another technique uses a starting wafer with a lightly doped protective layer. In this way, compensation is minimized and up-diffusion can be used to form a more uniform channel doping profile.

Trench devices can take advantage of the fact that the threshold is set by the channel doping concentration along the sidewalls of the trench. Processes that allow high doping concentrations away from the trench while keeping the threshold low can help prevent punch-through mechanisms. Providing p-well doping prior to the gate oxidation process separates well p-type impurities (eg, boron) into the trench oxide to reduce the concentration in the channel, thus reducing the threshold. Combining this process with the techniques described above can provide shorter channels without punch through.

Some power applications require measuring the amount of current flowing through a power transistor. This is typically done by isolating and measuring a fraction of the total device current, which is then used to infer the total current flowing through the device. The total device current in the isolated section flows through a current sensing or sensing device, generating a signal representing the magnitude of the isolated current, which is then used to determine the total device current. Such an arrangement is known as a mirror current source. Current sense transistors are usually monolithically fabricated as power devices where the two devices share a common substrate (drain) and gate. FIG. 60 is a simplified diagram of a MOSFET 6000 with a current sensing device 6002. The current flowing through the main MOSFET 6000 is divided between the main transistor and the current sensing section 6002 in proportion to each other's active area. Therefore, the current flowing through the main MOSFET 6000 is calculated by measuring the current flowing through the sensing device and then multiplying the sensed current by the ratio of the active area.

Various methods for isolating a current sensing device from a master device are described in commonly-owned U.S. Patent Application Serial No. 10/315,719 to Yedinak et al., entitled "Method of Isolating the Current Sense on Planar or Trench Stripe Power Devices while Maintaining a Continuous Stripe Cell" described, the entire contents of which are hereby incorporated by reference. Embodiments for integrating inductive devices with various power devices, including those with charge balancing structures, will be described below. According to one embodiment, in a power transistor having a charge balancing structure and an integrally integrated current sensing device, preferably, the current sensing region is formed with the same continuous MOSFET structure and charge balancing structure. Failure to maintain continuity in the charge balance structure will result in a lower breakdown voltage due to charge mismatch, causing the voltage supply region to not be completely depleted. FIG. 61A shows an exemplary embodiment of a charge balance MOSFET 6100 with a planar gate structure and isolated current sensing structure 6115. In this embodiment, the charge balancing structure includes opposite conductivity (p-type in this example) pillars 6126 formed within the drift region (n-type) 6104 . For example, p-type pillars 6126 may be formed in doped polysilicon or epitaxially filled trenches. As shown in FIG. 61A, the charge balancing structure maintains continuity under the current sensing structure 6115. The sensing pad metal 6113 covering the surface area of the current reactive device 6115 is electronically separated from the source metal 6116 by a dielectric region 6117 . It should be understood that a current sensing device having a similar structure can be integrated with any of the other power devices described herein. For example, Figure 61B shows an example of how a current sensing device can be integrated with a trench MOSFET with a shielded gate, charge balance can be achieved by adjusting the trench depth and biasing the shielded polysilicon within the trench.

There are many power applications where it is desirable to integrate diodes on the same die as power transistors. Such applications include temperature sensing, electrostatic discharge (ESD) protection, source clamping, and voltage division among others. For example, for temperature sensing, one or more series-connected diodes are integrally integrated with the power transistor, whereby the anode and cathode terminals of the diode are used to separate the bond pads, or are connected to the overall control circuit components using conductive interconnects . Temperature is sensed by a change in the forward voltage (Vf) of the diode. For example, with an appropriate interconnection to the gate terminal of the power transistor, since the Vf of the diode decreases with temperature, the gate voltage is pulled down to reduce the current through the device until the desired temperature is reached.

FIG. 62A shows an exemplary embodiment of a MOSFET 6200A with a temperature sensing diode in series. MOSFET 6200A includes a diode structure 6215 in which doped polysilicon with alternating conductivity forms three temperature sensing diodes in series. In this exemplary embodiment, the MOSFET portion of device 6200A uses p-type epitaxially filled charge-balancing trenches forming regions of opposite conductivity within n-type epitaxial drift region 6204 . Preferably, the charge balancing structure remains continuous underneath the temperature sensing diode structure 6215, as shown. Diode structures are formed on top of the field dielectric (oxide) layer 6219 atop the silicon surface. The P-type junction isolation region 6221 can optionally be diffused under the dielectric layer 6219 . A device 6200B without such a p-type junction is shown in Figure 62B. To confirm that a forward biased diode is obtained in series, a shorting metal 6223 is used to short the reverse biased P/N+ junction. In one embodiment, p+ implantation and diffusion are performed through the junction to form a N+/P/P+/N+ structure, where p+ occurs under the shorting metal 6223 for improved ohmic contact. For the opposite polarity N+ that can also diffuse across the N/P+ junction to form a P+/N/N+/P+ structure. Also, those skilled in the art will appreciate that this type of temperature sensing diode can be used in any of a variety of power devices in combination with many of the other features described herein. For example, Figure 62C shows a MOSFET 6200C with a shielded trench gate structure, where the shield electrode can be used for charge balancing.

In another embodiment, asymmetric ESD protection is achieved by using isolation techniques similar to those shown for device 6200 for temperature sensing diodes. For ESD protection purposes, one end of the diode structure is electrically connected to the source terminal and the other end is connected to the gate terminal of the device. Optionally, symmetrical ESD protection is obtained by not shorting any back N+/P/N+ junctions as shown in Figures 63A and 63B. The exemplary MOSFET 6300A shown in FIG. 63A uses a planar gate structure and uses columns of opposite conductivity for charge balancing, and the exemplary MOSFET 6300B shown in FIG. 63B is a trench gate device with a shielded gate structure. In order to prevent inhomogeneities in the charge balance, a charge balance structure extends under the gate bond pad metal and any other control element bond pads.

Figures 64A to 64D illustrate exemplary ESD protection circuits in which the main device is protected by the diode structure described above, and the gate can be any of the power devices described herein using any of the charge balancing or other techniques. Figure 64A shows a simplified diagram of symmetrically isolated polysilicon diode ESD protection, and Figure 64B shows a standard back-tie isolated polysilicon diode ESD protection circuit. The ESD protection circuit shown in FIG. 64C uses NPN transistors for BV _cer fast recovery. The subscript "cer" in BV _cer denotes a reverse biased collector-emitter bipolar transistor junction, where the connection to the base uses a resistor to control the base current. The low impedance allows most of the emitter current to migrate through the base, preventing the emitter-base junction from conducting, that is, injecting a small number of carriers back to the collector. The turn-on condition can be set by the resistor value. When the carriers are injected back to the collector, the holding voltage between the emitter and collector decreases - a phenomenon known as "snap recovery". The current at which BV _cer fast recovery is triggered can be set by adjusting the value of the base-collector resistance _RBE . Figure 64D shows an ESD protection circuit using silicon controlled rectifiers or SCRs and diodes as shown. By using a gate-to-cathode short circuit structure, the trigger current can be controlled. The diode breakdown voltage can be used to bias the SCR latch voltage. The integral diode structure described above can be used in any of these or other ESD protection circuits.

In some power applications, an important performance characteristic of a power switching device is its equivalent series resistance, or ESR, which measures the switch terminal or gate impedance. For example, in a synchronous buck converter using power MOSFETs, lower ESR helps reduce switching losses. In the case of trench-gate MOSFETs, the gate ESR is largely determined by the dimensions of the polysilicon-filled trench. For example, the length of the gate trench may be defined by packaging constraints (eg, minimum wire bond bond pad size). It is well known that the application of silicide films to polysilicon can reduce gate resistance. However, the use of silicide films in trench MOSFETs presents many problems. In a typical planar discrete MOS structure, the gate polysilicon can be silicided after the junctions have been implanted and driven to their respective depths. For trench-gate devices where the gate polysilicon is recessed, applying silicide becomes more complex. The use of traditional silicides limits the maximum temperature, and wafers can withstand rapid silicidation processes of less than about 900°C. This places significant constraints on the fabrication process when forming diffusion regions (eg, sources, drains, and wells). The most typical metal used for silicidation is titanium. Other metals such as tungsten, tantalum, cobalt, and platinum can also be used for fast silicidation processes with higher thermal budgets, providing greater processing latitude. Gate ESR can also be reduced through various design techniques.

Various embodiments for forming charge balancing power switching devices with lower ESR are described below. In one embodiment shown in FIG. 65, process 6500 includes forming a trench with a lower electrode formed in a lower portion of the trench for shielding and/or charge balancing purposes (step 6502). Next is deposition and etching of the IPD layer (step 6504). The IPD layer can be formed by a known process. Alternatively, any of the processes described above in connection with FIGS. 45 to 50 can be used to form the IPD layer. Next, in step 6506, the upper electrode or gate polysilicon is deposited and etched using known processes. This is followed by implanting and driving the well and source regions (step 6508). In step 6510 following step 6508, suicide is applied to the gate polysilicon. Then, in step 6512, a dielectric layer is deposited and planarized. In a modification of the process, the step 6512 of depositing and planarizing a dielectric layer is performed first, and then after the silicide contacts are formed, contact holes are opened to reach the source/body and gate. These two embodiments rely on heavily doped body implant regions activated by a low temperature anneal below the transition point of the silicide film.

In another embodiment, the polysilicon gates are replaced by metal gates. According to this embodiment, the metal gate is formed by using an aligned source deposition, such as Ti, to improve fillability in the trench structure. After the metal gate is applied, once the junction has been implanted and driven, dielectric options include HDP and TEOS to isolate the gate from the source/body contacts. In alternative embodiments, damascene and dual damascene methods with various metal selections from aluminum to copper are used to form the gate terminals.

The layout of the gate conductor can also affect the gate ESR and the overall switching speed of the device. In another embodiment shown in FIGS. 66A and 66B , the layout technique combines vertical silicided surface poly stripes and recessed trench polysilicon to reduce gate ESR. Referring to FIG. 66A , a highly simplified device structure 6600 is shown in which suicide-coated polysilicon lines 6604 extend along the silicon surface perpendicular to trench strips 6602 . Figure 66B shows a simplified cross-sectional view of device 6600 along the AA' axis. A suicided polysilicon line 6604 contacts the gate polysilicon at the intersection with the trench. A plurality of suicided poly lines 6604 may extend on top of the silicon surface to reduce the resistivity of the gate electrode. For example, this and other layout techniques made possible by processing with two or more interconnect layers can be used to improve gate ESR in any of the trench-gate devices described herein.

circuit application

For example, the chip area occupied by power devices may be reduced due to the significant reduction in device on-resistance provided by the various device and process technologies described herein. As a result, the overall integration of these high-voltage devices with low-voltage logic and control circuitry becomes more feasible. In typical circuit applications, various types of functions that can be integrated on the same die as power devices include power control, sensing, protection, and interface circuits. An important issue in the overall integration of power devices with other circuits are techniques for electrically isolating high voltage power devices from low voltage logic or control circuits. There are many known methods to achieve this, including junction isolation, dielectric isolation, silicon-on-insulator, and others.

In the following, many current applications for power switching will be described, where various current components can be integrated on the same chip. Figure 67 shows a synchronous buck converter (DC-DC converter) requiring lower voltage devices. In this circuit, n-channel MOSFET Q1 (often referred to as the "high-side switch") is designed to have moderately low on-resistance but fast switching speed to minimize power loss. MOSFET Q2 (often referred to as the "low-side switch") is designed to have very low on-resistance and moderately high switching speed. Figure 68 shows another DC-DC converter more suitable for medium to high voltage devices. In this circuit, the main switching device Qa exhibits fast switching speed and high blocking voltage. Because this circuit uses a transformer, less current flows through the transistor Qa, allowing it to have an appropriate on-resistance. For the synchronous rectifier Qs, MOSFETs with very low on-resistance, fast switching speed, very low reverse recovery charge, and low inter-electrode capacitance can be used. Other embodiments and improvements to such DC-DC converters are described in commonly assigned U.S. Patent Application No. 10/222,481 to Elbanhawy, entitled "Methods and Circuit for Reducing Losses in DC-DC Converters" (Attorney Docket No. 18865-91 -1/17732-51430), the entire contents of which are incorporated herein by reference.

Any of the various power devices described above can be used for the MOSFETs in the converter circuits of FIGS. 67 and 68 . For example, the dual-gate MOSFET type shown in FIG. 4A is one type that offers particular advantages when used to implement a synchronous buck converter. In one embodiment, a special drive setup takes advantage of all the features offered by the dual gate MOSFET. An example of this embodiment is shown in FIG. 69, in which the potential of the first gate terminal G2 of the high-side MOSFET Q1 is determined by a circuit consisting of a diode D1, resistors R1 and R2, and a capacitor C1. The fixed potential at the gate terminal G2 of Q1 can be adjusted to best Q _gd to optimize the switching time of the transistor. A second gate terminal G1 of the high-side MOSFET Q1 receives a common gate drive signal from a pulse width modulation (PWM) controller/driver (not shown). As shown, both gate electrodes of low-side switching transistor Q2 are driven similarly.

In an alternative embodiment, an example of which is shown in Figure 70A, the two gate electrodes of the high-side switch are driven separately to further optimize circuit performance. According to this embodiment, different waveforms drive the gate terminals G1 and G2 of the high-side switch Q1 to achieve the best switching speed during the transition and the best on-resistance of the device during the remaining period. In one example shown, a voltage of about 5 volts delivers a very low _Qgd to the gate of the high-side switch Q1 during the transition, resulting in a high switching speed, but before and after the transition periods td1 and td2, R _DSon not at its lowest value. However, since R _DSon is not a significant loss party during switching, this does not adversely affect the operation of the circuit. In order to ensure the lowest R _DSon during the remaining duration of the pulse, the potential V _g2 at the gate terminal G2 is raised to the second voltage Vb, wherein the second voltage Vb is high during the time _tp shown in the timing diagram of FIG. 70B in Va. This drive design achieves optimum efficiency. Modifications to this driver design are described in more detail in commonly registered U.S. Patent Application Serial No. 10/686,859 (Attorney Docket No. 17732-66930), entitled "Driver for Dual Gate MOSFETs," by Elbanhawy, the entirety of which incorporated herein by reference.

packaging technology

An important issue for all power semiconductor devices is the housing or packaging used to connect the device to the circuit. The semiconductor die is typically attached to the metal pads using a metal bonding layer (eg, solder) or a metal-filled epoxy adhesive. The wires are typically adhered to the top of the chip, and then that bump is passed through the molded body. Then, the assembly is mounted on the circuit board. The housing provides the electrical and thermal connection between the semiconductor chip and the electronic system and its surroundings. Low parasitic resistance, capacitance, and inductance are desirable electrical characteristics for a housing that enables better connection to the chip.

Improvements in packaging technology that have been proposed have mainly focused on reducing the resistance and inductance in the package. In certain packaging techniques, solder balls or copper buttons are distributed on the relatively thin (eg, 2-5 μm) metal surface of the chip. By distributing the metal connections over a large area of the metal surface, the current paths in the metal are made shorter and the metal resistance is reduced. If the raised side of the chip is connected to a copper lead frame or to a copper trace on a printed circuit board, the resistance of the power device is reduced compared to the wire bonding method.

Figures 71 and 72 show simplified cross-sectional views of molded and moldless packages, respectively, using solder balls or copper buttons connecting the lead frame to the metal surface of the chip. The molded package 7100 as shown in FIG. 71 includes a leadframe 7106 connected to a first side of the die 7102 by solder balls or copper buttons 7104 . A second side of the die 7102 away from the leadframe 7106 is exposed through the molding material. In a typical vertical power transistor, the second side of the die forms the drain terminal. The second side of the die can form a direct electrical connection to the pads on the circuit board, thus providing a low impedance thermal and electrical path for the die. This type of packaging and modifications thereof are described in commonly assigned U.S. Patent Application No. 10/607,633, entitled "Flip Chip in Leaded Molded Package and Method of Manufacturing Thereof," by Joshi et al. (Attorney Docket No. 18865-42-1/17732 -1342), the entire contents of which are hereby incorporated by reference.

FIG. 72 shows a non-molded embodiment of package 7200. In the exemplary embodiment shown in FIG. 72 , a package 7200 has a multilayer substrate 7212 that includes a base layer 7220 (eg, composed of metal) and a metal layer 7221 separated by a dielectric layer 7222 . Solder structures 7213 (eg, solder balls) are connected to the substrate 7212 . A die 7211 is attached to a substrate 7212, and a bonding structure 7213 is provided around the die. Die 7211 may be attached to substrate 7212 by a die attach material (eg, solder 7230). After forming the package as shown, it is inverted and mounted on a circuit board (not shown) or other circuit substrate. In the embodiment where the vertical power transistor is fabricated on the die 7211, the solder balls 7230 form the drain terminal connection, and the chip surface forms the source terminal. Reversed connections can also be achieved by reversing the connection of the die 7211 to the substrate 7212. As shown, package 7200 is thin and non-molded, so no molding material is required. Moldless packaging for this type is described in commonly assigned U.S. Patent Application No. 10/235,249 (Attorney Docket No. 18865-007110/17732-26390.003) entitled "Unmolded Package for a Semiconductor device" by Joshi A more detailed description, the entire contents of which are incorporated herein.

Alternative methods have been proposed where the upper surface of the chip is directly connected to the copper by solder or conductive epoxy. Because the stress induced between the copper and silicon die increases with the die area, direct attach methods may be limited because the solder or epoxy interface is only stressed to that extent before failure. Bump pads, on the other hand, enable more replacements before failure and have been shown to work with very large chips.

Another important issue in package design is heat dissipation. Improvements in the performance of power semiconductors generally result in smaller chip areas. The concentration of thermal energy on a smaller area can generate higher temperatures and reliably drop if the power loss in the chip does not increase. Methods to increase the rate of heat transfer outside the package include reducing the number of thermal interfaces, using materials with higher thermal conductivity, and reducing the thickness of layers (e.g., silicon, solder, die attach, and die attach pad) . Rajeev Joshi's commonly-assigned US Patent No. 6,566,749, entitled "Semiconductor Die Package With Improved Thermal and Electrical Performance," discusses solutions to thermal problems, particularly with respect to dies including vertical power MOSFETs for RF applications. Other techniques for improving overall packaging performance are described in commonly assigned U.S. Patent Nos. 6,133,634 and 6,469,384 to Rajeev Joshi, and U.S. Patent Application No. 6,469,384 to Joshi et al. Details are contained in 10/271,654 (Attorney Docket No. 18865-99-1/17732.53440). It should be understood that any of the various power devices described herein may be housed in any of the packages described herein or any other suitable package.

Using more case area for heat dissipation also increases the case's ability to maintain cooler temperatures, eg, the thermal interface at the top and bottom of the case. The increased surface area combined with the airflow around these surfaces increases the rate of heat dissipation. The case design also enables easy connection to an external heat sink. Since heat conduction and infrared radiation techniques are common methods, the application of alternate cooling methods is possible. For example, as described in commonly assigned U.S. Patent Application Serial No. 10/408,471 (Attorney Docket No. 17732-6672) to Reno Rossetti, entitled "Power Circuitry With A Thermionic Cooling System," thermionic emission can be used to cool power devices. A method of dissipating heat, the entire contents of which are incorporated herein by reference.

The integration of logic circuits including power output and control functions in a single package poses other problems. For one, the housing requires more pins to interface with other electronic functions. Packaging should take into account high current power interconnects and low current signal interconnects in the package. Various packaging techniques that can address these issues include: chip-to-chip wire bonding to eliminate special connection pads; chip-on-chip to save space inside the housing; and multi-chip modules, which allow different silicon technologies to be combined into a single electronic function. Various embodiments of multi-chip packaging technology are described in commonly assigned U.S. Patent Application No. 09/730,932 (Attorney Docket No. 18865-50/17732-19450) entitled "Stacked Package Using Flip in Leaded Molded Package Technology" by Rajeev Joshi, and described in Ser. No. 10/330,741 (Attorney Docket No. 18865-121/17732-66650.08) entitled "Multichip Module Including Substrate with an Array of Interconnect Structures," also by Rajeev Joshi, the entire contents of which are incorporated herein by reference.

While the above provides a complete description of the preferred embodiment of the invention, many alternatives, modifications and equivalents are possible. For example, in this paper, many charge balancing techniques are described in the context of MOSFETs, especially trench-gate MOSFETs.

Those skilled in the art will appreciate that the same techniques can be applied to other types of devices including IGBTs, thyristors, diodes and planar MOSFETs, as well as lateral devices. Accordingly, for these and other reasons, the above description is not intended to limit the scope of the invention, which is defined by the appended claims.

Claims (203)

1. semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove, pass described well region extension and extend into described drift region, sidewall and bottom along described active groove are provided with dielectric material, and described active groove is filled with first screening conductive layer and the grid conducting layer basically, the described first screening conductive layer is arranged under the described grid conducting layer, and separates with described grid conducting layer by dielectric material between electrode;

Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove; And

Electric charge control groove more in depth extends in the described drift region than described active groove, and is filled with the material that is used in the vertical electric charge control of described drift region basically.

2. semiconductor device according to claim 1 wherein, along described electric charge control groove dielectric materials layer is set, and described electric charge control groove is filled with electric conducting material basically.

3. semiconductor device according to claim 2, wherein, described source electrode is electrically connected to described source area with the described electric conducting material in the described electric charge control groove.

4. semiconductor device according to claim 1 wherein, is provided with a plurality of conductive layers in described electric charge control groove, described a plurality of conductive layer vertical stackings are also separated from one another and separate with described trenched side-wall by dielectric material.

5. semiconductor device according to claim 4 wherein, is electrically biased at the described a plurality of conductive layers in the described electric charge control groove, so that the vertical electric charge balance to be provided in described drift region.

6. semiconductor device according to claim 5, wherein, the described a plurality of conductive layers in described electric charge control groove are configured to independent biasing.

7. semiconductor device according to claim 4, wherein, the thickness difference of the described a plurality of conductive layers in described electric charge control groove.

8. semiconductor device according to claim 1, wherein, the thickness of more deep described first conductive layer is less than the thickness that is arranged on second conductive layer on described first conductive layer in described electric charge control groove.

9. semiconductor device according to claim 1, wherein, the described first screening conductive layer in the described active groove is configured to electrical bias to the expectation current potential.

10. semiconductor device according to claim 1, wherein, described first screening conductive layer and described source area are electrically connected to essentially identical current potential.

11. semiconductor device according to claim 1, wherein, described active groove also comprises the secondary shielding conductive layer that is arranged under the described first screening conductive layer.

12. semiconductor device according to claim 11, wherein, the described first screening conductive layer is different with the thickness of secondary shielding conductive layer.

13. semiconductor device according to claim 11, wherein, described first screening conductive layer and secondary shielding conductive layer are configured to independent biasing.

14. semiconductor device according to claim 1, wherein, described electric charge control groove is filled with dielectric material basically.

15. semiconductor device according to claim 14 also comprises the lining of second electric conducting material that extends along the lateral wall of described electric charge control groove.

16. semiconductor device according to claim 1 also comprises Schottky junction structure, it is formed between the described electric charge control groove and the second adjacent electric charge control groove.

17. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove, pass described well region extension and extend into described drift region, in described active groove, form the main grid utmost point of making by electric conducting material and the inferior grid of making by electric conducting material, and it is separated from one another and separate with described trenched side-wall by dielectric materials layer, the described main grid utmost point is on described grid, described active groove also has first bucking electrode of being made by electric conducting material, and it is arranged under described grid and by dielectric material and separates with described grid; And

Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove.

18. semiconductor device according to claim 17, wherein, the described main grid utmost point and described grid are configured to independent electrical bias.

19. semiconductor device according to claim 18, wherein, described grid is in the biasing of the constant potential place of the threshold voltage that is approximately described semiconductor device.

20. semiconductor device according to claim 18, wherein, described time grid is being setovered greater than the current potential place that is applied to described source area current potential.

21. semiconductor device according to claim 18, wherein, described grid was connected to the current potential of the described threshold voltage that is approximately described semiconductor device before switch motion.

22. semiconductor device according to claim 17, wherein, described first bucking electrode is configured to independently be biased to the expectation current potential.

23. semiconductor device according to claim 17, wherein, described active groove also comprises one or more bucking electrodes except that described first bucking electrode, and it is stacked under described first bucking electrode.

24. semiconductor device according to claim 23, wherein, described first bucking electrode is different with the size of described one or more additional mask electrodes.

25. semiconductor device according to claim 17 also comprises electric charge control groove, it extends into described drift region and is filled with basically and is used for the described material of controlling at the vertical electric charge of drift region.

26. semiconductor device according to claim 25, wherein, the source electrode is electrically connected to described source area with the described electric conducting material in the described electric charge control groove.

27. semiconductor device according to claim 25 wherein, is provided with a plurality of conductive layers in described electric charge control groove, described a plurality of conductive layer vertical stackings are separated from one another and separate with described trenched side-wall by dielectric material.

28. semiconductor device according to claim 27, wherein, the described a plurality of conductive layers in the described electric charge control of the electrical bias groove are to provide the vertical electric charge balance in substrate.

29. semiconductor device according to claim 28, wherein, the described a plurality of conductive layers in the described electric charge control groove are configured to independent biasing.

30. semiconductor device according to claim 27, wherein, the size difference of the described a plurality of conductive layers in the described electric charge control groove.

31. semiconductor device according to claim 30, wherein, the size that is deep into first conductive layer in the described electric charge control groove more is less than the size that is arranged on second conductive layer on described first conductive layer.

32. semiconductor device according to claim 17 also is included in the Schottky junction structure that forms between two adjacent trenches.

33. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove, pass described well region extension and extend into described drift region, in described active groove, form the main grid utmost point of making by electric conducting material and the inferior grid of making by electric conducting material, separated from one another and separate with the bottom with described trenched side-wall by dielectric materials layer, the described main grid utmost point is on described grid;

Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove; And

Electric charge control groove more in depth extends in the described drift region than described active groove, and is filled with the material that is used in the vertical electric charge control of described drift region basically.

34. semiconductor device according to claim 33, wherein, the described main grid utmost point and described grid are configured to independent electrical bias.

35. semiconductor device according to claim 34, wherein, described grid is in the biasing of the constant potential place of the threshold voltage that is approximately described semiconductor device.

36. semiconductor device according to claim 34, wherein, described grid is in the current potential place biasing bigger than the current potential that is applied to described source area.

37. semiconductor device according to claim 34, wherein, described grid was connected to the current potential of the described threshold voltage that is approximately described semiconductor device before switch motion.

38. semiconductor device according to claim 33 wherein, along described electric charge control groove dielectric material is set, and described electric charge control groove is filled with electric conducting material basically.

39. according to the described semiconductor device of claim 38, wherein, the source electrode is connected to described source area with the described electric conducting material in the described electric charge control groove.

40. semiconductor device according to claim 33 wherein, is provided with a plurality of conductive layers in described electric charge control groove, described a plurality of conductive layer vertical stackings are separated from one another and separate with described trenched side-wall by dielectric material.

41. according to the described semiconductor device of claim 40, wherein, the described a plurality of conductive layers in the described electric charge control of the electrical bias groove are to provide the vertical electric charge balance in substrate.

42. according to the described semiconductor device of claim 41, wherein, the described a plurality of conductive layers in the described electric charge control groove are configured to independent biasing.

43. according to the described semiconductor device of claim 40, wherein, the described a plurality of conductive layer size differences in the described electric charge control groove.

44. according to the described semiconductor device of claim 43, wherein, the size of first conductive layer that is deep into described electric charge control groove more is less than the size that is arranged on second conductive layer on described first conductive layer.

45. semiconductor device according to claim 33, wherein, described electric charge control groove is filled with dielectric material basically.

46. according to the described semiconductor device of claim 45, also comprise the lining of second electric conducting material, its lateral wall along described electric charge control groove extends.

47. semiconductor device according to claim 33 also comprises Schottky junction structure, it is formed between the described electric charge control groove and the second adjacent electric charge control groove.

48. a semiconductor device comprises:

The substrate of first conduction type;

First well region and second well region, described first well region and second well region each other every

Open, and have second conduction type with described first conductivity type opposite, and extend to first degree of depth of described substrate;

First source area and second source area, have described first conduction type and be respectively formed in described first well region and second well region, the outward flange of each source area and its interval between outward flange of well region separately form separately first channel region and second channel region;

The main grid utmost point, it forms on described substrate, superposes with described first source area and the described first channel region level, and separates with described first channel region with described first source area by thin dielectric layer;

Inferior grid, part are formed on that described main grid is extremely gone up and partly are formed on described first channel region, and separate with described first channel region with the described main grid utmost point by thin dielectric layer; And

First electric charge control groove and second electric charge control groove pass the extension of described first well region and second well region respectively and extend into described substrate, and are filled with the material that is used in the vertical electric charge control of described substrate basically.

49., wherein, along each electric charge control groove dielectric materials layer is set, and described electric charge control groove is filled with electric conducting material basically according to the described semiconductor device of claim 48.

50. according to the described semiconductor device of claim 49, wherein, the source electrode that forms on the surface of described substrate is electrically connected to described source area with the described electric conducting material in the described electric charge control groove.

51. according to the described semiconductor device of claim 48, wherein, in each electric charge control groove, a plurality of conductive layers are set, described a plurality of conductive layer vertical stackings, separated from one another and separate by dielectric material with described trenched side-wall.

52. according to the described semiconductor device of claim 51, wherein, the described a plurality of conductive layers in each electric charge control groove of electrical bias are to provide the vertical electric charge balance in described substrate.。

53. according to the described semiconductor device of claim 52, wherein, the described a plurality of conductive layers in each electric charge control groove are configured to independent biasing.

54. according to the described semiconductor device of claim 51, wherein, the described a plurality of conductive layer size differences in each electric charge control groove.

55. according to the described semiconductor device of claim 54, wherein, the size of going deep into first conductive layer in each electric charge control groove more is less than the size that is arranged on second conductive layer on described first conductive layer.

56. according to the described semiconductor device of claim 48, wherein, the described main grid utmost point and described grid are configured to independent electrical bias.

57. according to the described semiconductor device of claim 56, wherein, described grid is in the biasing of the constant potential place of the threshold voltage that is approximately described semiconductor device.

58. according to the described semiconductor device of claim 56, wherein, described grid is in the current potential place biasing bigger than the current potential that is applied to described source area.

59. according to the described semiconductor device of claim 56, wherein, described grid was connected to the current potential of the described threshold voltage that is approximately described semiconductor device before switch motion.

60. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove extends in the described drift region that is deeper than described well region, along the sidewall and the bottom of described active groove dielectric material is set, and described active groove is filled with grid conducting layer basically;

Source area has described first conduction type, is formed in the described well region adjacent with described active groove;

The main body groove, it is deeper than described well region extension, forms described main body groove adjacent to described trap and source area thereof, and described main body groove is filled with electric conducting material basically; And

Layer has described second conduction type that concentration increases, and is looped around substantially around the described body groove.

61. according to the described semiconductor device of claim 60, wherein, described main body groove is filled with the epitaxial material that is electrically connected to described source area basically.

62. according to the described semiconductor device of claim 60, wherein, described main body groove is filled with the doped polycrystalline silicon that is electrically connected to described source area basically.

63., wherein, form the layer that described concentration increases by injection technology according to the described semiconductor device of claim 60.

64. according to the described semiconductor device of claim 60, wherein, the alloy that diffuses out by the described electric conducting material in described main body groove forms the layer that described concentration increases.

65., wherein, regulate the distance L between the sidewall of the sidewall of described active groove and described adjacent main body groove, so that edge gate-to-drain electric capacity is minimized according to the described semiconductor device of claim 60.

66. according to the described semiconductor device of claim 65, wherein, L is approximately equal to or less than 0.3um greatly.

67., wherein, regulate the distance between the described sidewall of the outward flange of the layer that described concentration increases and described adjacent body groove, so that edge gate-to-drain electric capacity is minimized according to the described semiconductor device of claim 60.

68. according to the described semiconductor device of claim 60, wherein, described main body groove is deeper than described active groove.

69. according to the described semiconductor device of claim 68, wherein, described interval L is approximately equal to or less than 0.5um greatly.

70. according to the described semiconductor device of claim 60, wherein, described active groove also comprises first bucking electrode of being made by electric conducting material, it forms under described grid conducting layer, and described bucking electrode is by dielectric materials layer and described grid conducting layer and described trenched side-wall and bottom insulation.

71. according to the described semiconductor device of claim 70, wherein, described first bucking electrode in the described active groove is configured to electrical bias to the expectation current potential.

72. according to the described semiconductor device of claim 70, wherein, described first bucking electrode and described source area are electrically connected to essentially identical current potential.

73. according to the described semiconductor device of claim 70, wherein, described active groove also comprises the secondary shielding electrode of being made by electric conducting material, it is arranged under described first bucking electrode.

74. according to the described semiconductor device of claim 73, wherein, described first bucking electrode is different with the size of secondary shielding electrode.

75. according to the described semiconductor device of claim 73, wherein, described first screening conductive layer and secondary shielding conductive layer can be by independent biasings.

76. according to the described semiconductor device of claim 60, also comprise electric charge control groove, extend into the material that also is filled with the vertical electric charge balance that is used for described substrate in the described substrate basically.

77., wherein, along described electric charge control groove dielectric materials layer is set, and described electric charge control groove is filled with electric conducting material basically according to the described semiconductor device of claim 76.

78. according to the described semiconductor device of claim 77, wherein, the source electrode is electrically connected to described source area with the described electric conducting material in the described electric charge control groove.

79. according to the described semiconductor device of claim 76, wherein, in described electric charge control groove, a plurality of conductive layers are set, described a plurality of conductive layer vertical stackings, separated from one another and separate by dielectric material with described trenched side-wall.

80. according to the described semiconductor device of claim 79, wherein, the described a plurality of conductive layers in the described electric charge control of the electrical bias groove are to provide the vertical electric charge balance in described substrate.

81. 0 described semiconductor device according to Claim 8, wherein, the described a plurality of conductive layers in the described electric charge control groove are configured to independent biasing.

82. according to the described semiconductor device of claim 79, wherein, the size difference of the described a plurality of conductive layers in the described electric charge control groove.

83. 2 described semiconductor device wherein, are deep into described electric charge more and control the size of first conductive layer in the groove less than the size that is arranged on second conductive layer on described first conductive layer according to Claim 8.

84., also be included in the Schottky junction structure that forms between two adjacent trenches according to the described semiconductor device of claim 60.

85. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove extends in the described drift region that is deeper than described well region, forms the main grid utmost point of being made by electric conducting material in described active groove, and the described main grid utmost point separates with the bottom with trenched side-wall by dielectric material; And

Source area has described first conduction type, is formed in the described well region adjacent with described active groove,

Wherein, the bottom that described active groove is filled with dielectric material deeply extends in the described drift region, described bottom by the lining of second electric conducting material institute around, so that vertical electric charge control to be provided.

86. 5 described semiconductor device according to Claim 8 also comprise a plurality of locus of discontinuities of second conduction type, form described a plurality of locus of discontinuity adjacent to the lateral wall of the described active groove in the described drift region.

87. 5 described semiconductor device according to Claim 8, wherein, described active groove also comprises the inferior grid of being made by electric conducting material, and described time grid forms under the described main grid utmost point, and by dielectric layer and the insulation of the described main grid utmost point.

88. 7 described semiconductor device according to Claim 8, wherein, described time grid is configured to independent electrical bias.

89. 8 described semiconductor device according to Claim 8, wherein, described grid is in the biasing of the constant potential place of the threshold voltage that is approximately described semiconductor device.

90. 8 described semiconductor device according to Claim 8, wherein, described grid is in the current potential place biasing bigger than the current potential that is applied to described source area.

91. 8 described semiconductor device according to Claim 8, wherein, described grid was connected to the current potential of the described threshold voltage that is approximately described semiconductor device before switch motion.

92. 5 described semiconductor device according to Claim 8, wherein, described active groove also comprises first bucking electrode of being made by electric conducting material, and described first bucking electrode forms under the described main grid utmost point, and by dielectric layer and the insulation of described first bucking electrode.

93. according to the described semiconductor device of claim 92, wherein, described first bucking electrode is configured to be biased to separately the expectation current potential.

94. according to the described semiconductor device of claim 92, wherein, described active groove also comprises one or more bucking electrodes of being made by electric conducting material except that described first bucking electrode, described one or more bucking electrodes pile up under described first bucking electrode.

95. according to the described semiconductor device of claim 94, wherein, described first bucking electrode is different with the size of described one or more additional mask electrodes.

96. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove, pass described well region extension and extend into described drift region, sidewall and bottom along described active groove are provided with dielectric material, and described active groove is filled with first conductive layer and first grid conductive layer basically, described first conductive layer is arranged under the described first grid conductive layer, and by dielectric material and described first grid conductive layers apart between electrode;

Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove; And

First Schottky junction structure, it is formed on first table top between two adjacent trenches.

97. according to the described semiconductor device of claim 96, wherein, described first conductive layer is configured to bucking electrode.

98. according to the described semiconductor device of claim 96, wherein, described first conductive layer is configured to second gate electrode.

99. according to the described semiconductor device of claim 96, wherein, described active groove also comprises second conductive layer, is arranged under described first conductive layer that is configured to bucking electrode.

100. according to the described semiconductor device of claim 99, wherein, described first conductive layer is configured to electrical bias to a current potential, and described second conductive layer is configured to electrical bias to a current potential.

101. according to the described semiconductor device of claim 96, also comprise second Schottky junction structure, it is formed on second table top adjacent to described first table top.

102., wherein, form described first Schottky junction structure in mode perpendicular to the longitudinal axis of described two adjacent trenches according to the described semiconductor device of claim 96.

103. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove, pass described well region extension and extend into described drift region, sidewall and bottom along described active groove are provided with dielectric material, and described active groove is filled with first conductive layer that forms top electrode and second conductive layer that forms bottom electrode basically, and described top electrode is arranged on the described bottom electrode and by dielectric material between electrode and separates with described bottom electrode;

Source area has described first conduction type, is formed in the described well region adjacent with described active groove; And

Electric charge control groove, the sidewall of controlling groove along described electric charge is provided with dielectric material, and portion forms one or more diode structures within it.

104. according to the described semiconductor device of claim 103, wherein, described one or more diode structures comprise a plurality of opposite polarity conductive layers, and described a plurality of conductive layers alternately pile up in described electric charge control groove, wherein, one of bottommost electrically contacts with described drift region.

105. according to the described semiconductor device of claim 104, wherein, described top electrode is configured to the main grid electrode.

106. according to the described semiconductor device of claim 105, wherein, described bottom electrode is configured to time gate electrode.

107. according to the described semiconductor device of claim 106, wherein, described active groove also comprises the 3rd conductive layer that is arranged under described second conductive layer, described the 3rd conductive layer is configured to bucking electrode.

108. according to the described semiconductor device of claim 105, wherein, described bottom electrode is configured to first bucking electrode.

109. according to the described semiconductor device of claim 108, wherein, described active groove also comprises the 3rd conductive layer, is arranged under described second conductive layer, described the 3rd conductive layer is configured to the secondary shielding electrode.

110. according to the described semiconductor device of claim 103, wherein, described first and second electrodes can electrical bias.

111. according to the described semiconductor device of claim 103, also comprise Schottky junction structure, it is formed on two table tops between the adjacent electric charge control groove.

112. a semiconductor device comprises:

The substrate of first conduction type;

First well region and second well region, described first well region and second well region separate each other, and have second conduction type with described first conductivity type opposite, and extend to first degree of depth of described substrate;

First source area and second source area, have described first conduction type and be respectively formed in described first well region and second well region, the outward flange of each source area and its interval between outward flange of well region separately form separately first channel region and second channel region;

Gate electrode, it is formed on the described substrate that superposes with described first channel region and second channel region, and separates with described substrate by thin dielectric layer; And

First electric charge control groove and second electric charge control groove, pass the extension of described first well region and second well region respectively and extend into described substrate, sidewall along each electric charge control groove is provided with dielectric material, forms one or more diode structures in described electric charge control groove.

113. according to the described semiconductor device of claim 112, wherein, described one or more diode structure comprises a plurality of opposite conductivities layers, and described a plurality of opposite conductivities layers alternately pile up in described electric charge control groove, and of bottommost electrically contacts with described drift region.

114., also be included in the Schottky junction structure that forms on two table tops between the adjacent electric charge control groove according to the described semiconductor device of claim 112.

115. a semiconductor device comprises:

The drift region of first conduction type;

A plurality of well regions have second conduction type with described first conductivity type opposite, and described well region extends on described drift region;

Source area has described first conduction type, is formed in each well region in described a plurality of well region, and limits channel region;

Grid structure, it forms adjacent to described channel region; And

A plurality of floating regions have second conduction type, are arranged on substantially in the described drift region under each of described a plurality of well regions,

Wherein, the interval between a plurality of Cmaxs of the described floating region under each well region is along with described floating region and they increase of distance and increasing between the well region separately.

116. according to the described semiconductor device of claim 115, wherein, described grid structure is the conductive layer on basic plane, it is formed on the described channel region.

117. according to the described semiconductor device of claim 115, wherein, described grid structure is formed on the described channel region, and comprise the described channel region that superposes first the main grid utmost point and form on described main grid utmost point top and the inferior grid of the second portion of the described channel region that superposes.

118. according to the described semiconductor device of claim 115, wherein, described grid structure comprises and passes the groove that well region extends and extend into described drift region, along the sidewall and the bottom of described groove dielectric material is set, and described groove is filled with electric conducting material basically.

119. according to the described semiconductor device of claim 115, wherein, the described electric conducting material that is filled with described groove basically comprises the top that forms the main grid electrode and forms the bottom of absolute electrode with described upper isolation.

120. according to the described semiconductor device of claim 119, wherein, described absolute electrode is configured to time gate electrode.

121. according to the described semiconductor device of claim 119, wherein, described absolute electrode is configured to bucking electrode.

122. according to the described semiconductor device of claim 115, wherein, the size of a plurality of floating regions under each well region is along with described floating region and they increase of distance and reducing between the well region separately.

123. according to the described semiconductor device of claim 115, wherein, the Cmax of each is along with described floating region and they increase of distance and reducing between the well region separately in the described a plurality of floating regions under each well region.

124. according to the described semiconductor device of claim 115, wherein, under well region, contact each other, and under described well region, be effective floating regions from described well region those floating regions farthest from those nearest floating regions of described well region.

125. a semiconductor device comprises:

The drift region of first conduction type;

Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;

Active groove, pass described well region extension and extend into described drift region, sidewall and bottom along described active groove are provided with dielectric material, and described active groove is filled with first conductive layer that forms top electrode and second conductive layer that forms bottom electrode basically, described top electrode is arranged on the described bottom electrode, and separates with described bottom electrode by dielectric material between electrode;

Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove; And

First terminal trenches is extended under described well region, and is arranged on the outer edge of the active area of described device.

126. according to the described semiconductor device of claim 125, wherein, be provided with than the thick dielectric materials layer of described dielectric material along described first terminal trenches, and described first terminal trenches is filled with electric conducting material basically along the described sidewall of described active groove.

127. according to the described semiconductor device of claim 126, wherein, the described electric conducting material in described first terminal trenches is electrically connected to source metal.

128. according to the described semiconductor device of claim 126, wherein, the described electric conducting material in described first terminal trenches is buried under the dielectric material in the bottom of described terminal trenches.

129. according to the described semiconductor device of claim 125, wherein, described first terminal trenches is filled with dielectric material basically.

130. according to the described semiconductor device of claim 125, wherein, the width of the table top that forms between described first terminal trenches and adjacent active groove is different with the width of the table top that forms between two active grooves.

131. according to the described semiconductor device of claim 125, wherein, described first terminal trenches with annular ring around the active area of described device.

132. according to the described semiconductor device of claim 131, also comprise second terminal trenches, it is looped around around the described active area of the outer described device of described first terminal trenches.

133., wherein, be approximately twice between the end of described first terminal trenches and described active groove apart from S1 between described first terminal trenches and second terminal trenches apart from S2 according to the described semiconductor device of claim 132.

134. terminal structure in the outer edge of semiconductor device, described terminal structure comprises a plurality of concentric annulated column with first conduction type, it is formed in the termination environment that has with second conduction type of described first conductivity type opposite, and be looped around around the active area of described device, wherein, each post is connected respectively to conductive field plate.

135. according to the described terminal structure of claim 134, wherein, the big field plate of making by electric conducting material cover a plurality of posts subclass and with the subclass electric insulation of a plurality of posts, different conductive field plate is connected in described a plurality of post remaining one.

136. according to the described terminal structure of claim 135, wherein, described big field plate is connected to ground.

137. according to the described terminal structure of claim 134, wherein, the subclass of described post is not covered by any conductive field plate.

138. according to the described terminal structure of claim 134, wherein, the Center Gap between described a plurality of posts is along with the distance at described active edge and change.

139. according to the described terminal structure of claim 138, wherein, the Center Gap between described a plurality of posts is along with the distance at described active edge and increase.

140. according to the described terminal structure of claim 134, wherein, the width of each post is along with the distance at the edge of described active area and change.

141. according to the described terminal structure of claim 140, wherein, the width of each post is along with the distance at the edge of described active area and reduce.

142. according to the described terminal structure of claim 134, wherein, it is basic identical that the width of the described a plurality of posts in described terminal structure keeps, and the width of the post of the opposite polarity under the well region in described active area is along with reducing with the distance of described well region.

143. form the method for buried conductive layer in the groove that is used on being formed on semiconductor substrate, described method comprises:

On the upper surface of described semiconductor substrate and described groove, form first dielectric materials layer;

On described first dielectric materials layer, form first conductive material layer;

Described first dielectric materials layer of one patterned and described first conductive material layer to be forming first conductive electrode, and described first conductive electrode is included in the described groove along first that the longitudinal axis of described groove extends and the second portion that extends on the top of the described substrate of first end of described groove;

On described first conductive material layer, form second dielectric materials layer;

On described second conductive material layer, form second dielectric materials layer; And

Described second dielectric materials layer of one patterned and described second conductive material layer to be forming second conductive electrode, and described second conductive electrode has in described groove and along first that the longitudinal axis of described groove extends and the second portion that extends on the top of the described second portion of described first conductive electrode.

144., also comprise according to the described method of claim 143:

Contact described first conductive layer by the opening in described first dielectric layer in the described second portion of described first conductive electrode; And

Contact described second conductive layer by the opening in described second dielectric layer in the described second portion of described second conductive electrode.

145. form the method for buried conductive layer in the groove that is used on being formed on semiconductor substrate, described method comprises:

On the upper surface of described semiconductor substrate and described groove, form first dielectric materials layer;

On described first dielectric materials layer, form first conductive material layer;

Described first dielectric materials layer of one patterned and described first conductive material layer to be forming first conductive electrode, and described first conductive electrode has in described groove first basic horizontal part of extending along the longitudinal axis of described groove and the second basic vertical component that extends to the described upper surface of described substrate;

On described first conductive material layer, form second dielectric materials layer;

On described second conductive material layer, form second dielectric materials layer; And

Described second dielectric materials layer of one patterned and described second conductive material layer to be forming second conductive electrode, and described second conductive electrode has in described groove along first that the longitudinal axis of described groove extends and the second portion that extends substantially vertically the described upper surface of described substrate.

146. according to the described method of claim 145, the surface that also is included in described substrate contacts the described second portion of described first conductive electrode and second conductive electrode.

147. have each the groove (tom) in a plurality of grooves of first dielectric materials layer;

Described a plurality of grooves are filled with first conductive material layer basically;

In described a plurality of grooves, apply mask layer on the selected groove;

Will be recessed at described first conductive material layer and described first dielectric materials layer in remaining a plurality of grooves;

Remove described mask layer;

On the described upper surface of the described substrate of described upper surface that comprises described remaining a plurality of grooves and sidewall, form second dielectric materials layer;

The top of described remaining a plurality of grooves is filled with second conductive material layer basically; And

Cover described second conductive material layer with the 3rd dielectric materials layer.

148. a method that is used for forming the buried conductive layer in a plurality of grooves of semiconductor substrate comprises:

The sidewall and the bottom of each in described a plurality of grooves are provided with first dielectric materials layer;

Described a plurality of grooves are filled with first conductive material layer basically;

In each exposes the groove of a part of first conductive material layer, described first dielectric materials layer is removed to first degree of depth from the upper surface of described substrate and the described sidewall of described a plurality of grooves, and the part that described first conductive material layer is exposed forms two grooves in each groove;

Use the described surface of the described exposed portions serve of the described sidewall of described upper surface that second dielectric materials layer covers described substrate, each groove and described first conductive material layer;

Described two grooves in each groove are filled with second conductive material layer basically; And

Cover described second conductive material layer with the 3rd dielectric materials layer.

149. a method that is used to control the thickness of epitaxially grown semi-conducting material comprises:

The semiconductor substrate that is mixed by first kind alloy is provided;

Form resilient coating on described semiconductor substrate, with the alloy of described undoped buffer layer second type, the diffusivity of the alloy of described second type is littler than the diffusivity of described first kind alloy; And

On described resilient coating, form the described epitaxially grown layer of expectation thickness.

150. according to the described method of claim 149, wherein, described undoped buffer layer arsenic.

151. a method that is used to control the thickness of epitaxially grown semi-conducting material comprises:

The semiconductor substrate that is mixed by first kind alloy is provided;

Form barrier layer on described semiconductor substrate, described barrier layer has the mixture that comprises carbon; And

On described resilient coating, form the epitaxially grown layer of expectation thickness,

Wherein, described barrier layer is used for stoping the described alloy of the described first kind upwards to be diffused into described epitaxially grown layer from described substrate.

152. according to the described method of claim 151, wherein, the described step that forms described barrier layer comprises the growing silicon carbide layer.

153. according to the described method of claim 151, wherein, the described step that forms described barrier layer comprises the carbon alloy is injected in the surface of described semiconductor substrate.

154. a method that is used to control the thickness of epitaxially grown semi-conducting material comprises:

The semiconductor substrate that is mixed by first kind alloy is provided;

On described semiconductor substrate, form the epitaxially grown layer of expectation thickness;

Form well region in described epitaxially grown layer, described well region has the alloy with second type of the described alloy opposite conductivities of the described first kind; And

Knot place between described epitaxially grown layer and described well region forms diffusion barrier layer,

Wherein, described barrier layer is used to prevent the diffusion of alloy between described well region and the described epitaxially grown layer.

155. according to the described method of claim 154, wherein, the described step that forms described diffusion barrier layer comprises that the window by limiting described well region injects carbon atom.

156. a method that is used to form trench gate type transistor comprises:

The substrate of first conduction type is provided;

On described substrate, form the drift region of described first conduction type;

In described drift region, form groove;

Sidewall and bottom along described groove are provided with first dielectric materials layer;

Under-filled first conductive material layer with described groove;

Cover described first conductive material layer with interlayer dielectric material;

The epitaxial loayer of growth and second conduction type of described first conductivity type opposite optionally is to form well region and to form groove on the described interlayer dielectric material on the upper surface of described drift region;

On the upper surface of described epitaxial loayer and sidewall, form second dielectric materials layer; And

The described groove of going up is filled with second conductive material layer basically.

157. a method that is used for forming at semiconductor device well region comprises:

The substrate of first conduction type is provided;

On described substrate, form the drift region of first conduction type;

In described drift region, form groove;

The buried electrodes that is sealed by dielectric material is formed at the bottom at described groove, exposes the sidewall on the top of described groove;

Inject to carry out first trap, be injected in the upper surface of described drift region with the alloy of second conduction type of described first conductivity type opposite; And

Carry out the injection of the second angle trap by the sidewall that expose on the described top of described groove with the alloy of second conduction type.

158. a method that is used for forming at semiconductor device well region comprises:

The substrate of first conduction type is provided;

On described substrate, form first drift region of first conduction type;

Form the dielectric material cylinder on described drift region, the width of each cylinder equals the width of the groove that will form substantially in later step;

On described first drift region and around the described dielectric material cylinder, form second drift region of described first conduction type;

The epitaxial loayer of growth and second conduction type of described first conductivity type opposite optionally is with in described second drift region be respectively formed on the upper surface of the groove on the dielectric material cylinder and form well region.

159. a method that is used for the attenuate wafers of semiconductor material comprises:

Finish the manufacturing of device in the top side of described wafer;

By first adhesion process described top side of described wafer is adhered to carrier temporarily;

The dorsal part of described wafer is thinned to expectation thickness;

By second adhesion process described dorsal part of the described wafer that is thinned is adhered to the Low ESR substrate; And

Remove described carrier and clear up the described top side of described wafer.

160. according to the described method of claim 159, wherein, described attenuate step comprises grinding technics.

161. according to the described method of claim 159, wherein, described attenuate step comprises chemical treatment.

162. a method that is used for the attenuate silicon substrate comprises:

The rear side of described silicon substrate is adhered to glass substrate;

(cleave) described silicon substrate forms heavy sheet glass silicon (SOTG) substrate by adhering optically;

On the silicon face of described SOGT substrate, form epitaxial loayer;

On the described silicon face of described SOGT substrate, make active device;

By grinding technics the part of described glass substrate is removed from the dorsal part of described silicon substrate; And

By the chemical etching processing remainder of described glass substrate is removed from the described dorsal part of described silicon substrate.

163. a method that is used at the semiconductor substrate etched trench comprises:

Carry out main first degree of depth that etches into, the chemicals based on chlorine are used in described main etching, and groove has taper and level and smooth sidewall in the middle of making; And

Carry out the inferior ultimate depth that etches into, the chemicals based on fluorine are used in described etching,

Wherein, described based on fluorine inferior etching the further level and smooth of the fillet of described channel bottom and trenched side-wall is provided.

164. according to the described method of claim 163, wherein, described main etch chemistries comprises Cl ₂/ HBr, and described etch chemistries comprises SF ₆

165. a method that is used at the semiconductor substrate etched trench comprises:

Carry out main first degree of depth that etches into, the chemicals based on fluorine are used in described main etching, and groove has straight substantially sidewall and circular bottom in the middle of making; And

Carry out the inferior ultimate depth that etches into, the chemicals based on chlorine are used in described etching,

Wherein, described inferior etching based on fluorine provides the further level and smooth of the fillet of described groove top corner and trenched side-wall.

166. according to the described method of claim 165, wherein, described main etch chemistries comprises CF ₆/ O2, and described etch chemistries comprises Cl ₂

167. a method that is used at the semiconductor substrate etched trench comprises:

Use has the chemicals based on fluorine that add argon and carries out main etching, to increase ion bombardment and to prevent the recessed again tendency in described top of described groove; And

Carry out time etching, with the sidewall of level and smooth described groove.

168. according to the described method of claim 167, wherein, described main etch chemistries comprises SF ₆/ O ₂/ Ar.

169. a method that is used at the semiconductor substrate etched trench comprises:

Use the chemicals based on fluorine of anaerobic to carry out main etching; And

Use the chemicals based on fluorine of oxidation to carry out time etching,

Wherein, described main etching makes the side etching at place, described groove top increase, and described etching makes the remainder of described groove produce straight substantially sidewall and circular bottom.

170. according to the described method of claim 169, wherein, described main etch chemistries comprises SF ₆, and described etching comprises SF ₆/ O ₂

171. a method that is used at semiconductor substrate etching deep groove comprises:

Use the chemicals based on fluorine of oxidation, wherein, introduce oxygen, with the control side wall passivation with gradual manner; And

Gradual change power and pressure are with the control ion current density and keep substantially invariable etch-rate.

172. a method that is used at semiconductor substrate etching deep groove comprises: use the bigger chemicals of nitrogenous activity to carry out main etching, then use active less chemicals SF based on fluorine based on fluorine ₆Carry out time etching.

173. according to the described method of claim 172, described main etching comprises NF ₃, and described etching comprises SF ₆/ O ₂

174., also comprise in the mode that replaces and repeat described main etching and described etched step according to the described method of claim 173.

175. a method that is used at the semiconductor substrate etched trench comprises:

The pad oxide thin layer is formed on the top at described substrate;

On described cushion oxide layer, form non-oxide material layer;

On conductive material layer, form silicon nitride layer;

The described cushion oxide layer of one patterned, non-oxide material layer and silicon nitride layer are to be defined for the opening that forms described groove; And

By the described groove of described opening etching,

Wherein, the described non-oxide material layer between described pad oxide layer and the described silicon nitride layer prevents during treatment step subsequently the growth in the pad oxide at described slot wedge place.

176. a method that is used at the semiconductor substrate etched trench comprises:

The pad oxide thin layer is formed on the top at described substrate;

On described cushion oxide layer, form silicon nitride layer;

Described cushion oxide layer of one patterned and silicon nitride layer are to be defined for the opening that forms described groove;

On the surface texture of described substrate, form non-oxide material thin-layer;

Remove described non-oxide material thin-layer from the horizontal surface of described surface texture, stay along the non-oxide material separator of the vertical edge of described nitration case-liner oxidation structure; And

By the described groove of described opening etching,

Wherein, described non-oxide material separator prevents during with post-processing step the growth in the pad oxide at described slot wedge place.

177. a method that is used for forming dielectric layer between electrode in groove comprises:

Sidewall and bottom along described groove are provided with first dielectric materials layer;

Described groove is filled with first conductive material layer basically to form first electrode;

Make described first dielectric materials layer and described first conductive material layer be recessed into the first interior degree of depth of described groove;

Form polysilicon material layer on the described dielectric material in described groove and the upper surface of conductive material layer;

The described polysilicon material layer of oxidation, thus be converted into silicon dioxide layer; And

Form second electrode of making by electric conducting material in the groove on described silicon dioxide layer, and separate with trenched side-wall by second dielectric layer.

178. a method that is used for forming dielectric layer between electrode in groove comprises:

Sidewall and bottom along described groove are provided with first dielectric materials layer;

Described groove is filled with first conductive material layer basically to form first electrode;

Make described first conductive material layer be recessed into first degree of depth in described groove;

The remainder of described groove is filled dielectric fill material substantially;

Make described first dielectric materials layer and described dielectric fill material layer be recessed into second degree of depth to form dielectric layer between electrode; And

Form second electrode of making by electric conducting material in the described groove between described electrode on the dielectric layer, and separate with trenched side-wall by second dielectric layer.

179. a method that is used for forming dielectric layer between electrode in groove comprises:

Sidewall and bottom along described groove are provided with first dielectric materials layer;

Described groove is filled with first conductive material layer basically, to form first electrode;

Described first conductive material layer is recessed into first degree of depth in the described groove, makes the top of described recessed conductive material layer be higher than the final goal degree of depth by desired depth;

By changing the characteristic of described first conductive material layer, increase the oxidation rate on the described top of described recessed first conductive material layer;

Remove described first dielectric materials layer from remaining trenched side-wall;

Carry out oxidation step, the top that described first conductive material layer changes is oxidized with the speed faster than described trenched side-wall, forms than dielectric layer between the thick electrode of lateral wall insulation lining; And

Form second electrode of making by electric conducting material in the described groove between described electrode on the dielectric layer, and separate with the channel insulation lining by described sidewall.

180. according to the described method of claim 179, wherein, the described step of oxidation rate that improves the described top of described recessed first conductive material layer comprises chemistry or physically changes described top.

181. according to the described method of claim 179, wherein, the described step of oxidation rate that improves the described top of described recessed first conductive material layer comprises and the upper surface of described first conductive material layer implanted dopant substantially vertically.

182. according to the described method of claim 181, wherein, described impurity is a kind of in argon or the fluorine.

183. a method that is used for forming dielectric layer between electrode in groove comprises:

Sidewall and bottom along described groove are provided with first dielectric materials layer;

Described groove is filled with first conductive material layer basically to form first electrode;

Make described first conductive material layer be recessed into the first interior degree of depth of described groove;

Be preferably formed second dielectric layer, thereby form dielectric layer between thicker relatively electrode on the horizontal surface structure in described groove, and the dielectric layer that forms relative thin along the sidewall of described groove;

Removal is along the dielectric layer of the described relative thin of described trenched side-wall; And

Form second electrode of making by electric conducting material in the described groove between described electrode on the dielectric layer, and separate with trenched side-wall by the sidewall dielectric liner.

184. according to the described method of claim 183, wherein, the described step that is preferably formed second dielectric layer comprises the orientated deposition processing.

185. according to the described method of claim 184, wherein, described orientated deposition is handled and is comprised plasma enhanced chemical vapour phase accumulation.

186. a method that is used for forming dielectric layer between electrode in groove comprises:

Sidewall and bottom along described groove are provided with first dielectric materials layer;

Described groove is filled with first conductive material layer basically to form first electrode;

Make described first dielectric materials layer and described first conductive material layer be recessed into the first interior degree of depth of described groove;

Vertical and horizontal surface formation masking oxide thin layer in the described groove;

Form the silicon nitride layer that covers described masking oxide thin layer;

Remove described silicon nitride layer from the described bottom of described groove, exposing described horizontal masking oxide thin layer, but stay the described vertical masking oxide thin layer that covers by described silicon nitride layer;

Described groove is exposed to oxidation environment, to form dielectric layer between thicker relatively electrode on the horizontal bottom surface of described groove;

Remove described silicon nitride layer from described trenched side-wall; And

Form second electrode of making by electric conducting material in the described groove between described electrode on the dielectric layer, and separate with trenched side-wall by the lateral wall insulation lining.

187. a method that is used for forming dielectric layer between electrode in the groove that semiconductor substrate forms comprises:

First electrode of being made by electric conducting material is formed at the bottom at described groove, and separates with the bottom with trenched side-wall by first dielectric liner;

Form the thick dielectric materials layer of filling described groove and on described semiconductor substrate, extending;

Described thick dielectric layer is planarized to fully the upper surface of described semiconductor substrate; And

Carry out isotropically wet etching process, make the remainder of described thick dielectric materials layer in described groove, be recessed into target depth.

188. according to the described method of claim 187, wherein, the step of described abundant complanation comprises carries out anisotropic plasma etching process processes.

189. according to the described method of claim 187, wherein, the step of described abundant complanation comprises that carrying out chemical-mechanical planarization handles.

190. a method that is used for forming oxide layer on semiconductor wafer comprises:

Under test environment, apply the DC bias voltage to described semiconductor wafer;

Under the condition that the surface reaction with oxide is suppressed substantially, determine the DC bias condition;

Between the heat of oxidation, apply external bias to described semiconductor wafer; And

Utilize described external bias to come the optimization oxidation rate.

191. a channel bottom that is used for forming at semiconductor substrate forms the method for thick oxide layer, comprising:

Handle to form conformal oxide-film by the low pressure chemical vapour phase accumulation of filling described groove and covering the upper surface of described substrate; And

In the described upper surface of described substrate and described groove, etch away described oxide-film, to stay the oxide layer of substantially flat at the place, described bottom of described groove with target thickness.

192., also comprise and carry out Temperature Treatment with described oxide-film densification according to the described method of claim 191.

193. a channel bottom that is used for forming at semiconductor substrate forms the method for thick oxide layer, comprising:

Handle deposited oxide film by directed tetraethoxysilane (TEOS), wherein, described TEOS handles on the horizontal surface of the described bottom that comprises described groove rather than comprising on the vertical surface of trenched side-wall and form thicker oxide-film; And

Isotropically the described oxide-film of etching until all oxide-films of removing on the trenched side-wall, and stays oxide layer in the described bottom of the described groove with target thickness.

194. according to the described method of claim 193, wherein, described etching step comprises dried top oxide etching, then is wet buffer oxide etch.

195. according to the described method of claim 194, wherein, described dried top oxide etching comprises the mist etch processes, and described mist etch processes is to compare the oxide of the speed etching of acceleration near the described top of described groove with the oxide of locating in the described bottom of approaching described groove.

196. a channel bottom that is used for forming at semiconductor substrate forms the method for thick oxide layer, comprising:

Come deposited oxide film by the high-density plasma deposition processes, wherein, the oxide layer that described high-density plasma deposition processes forms at described channel bottom is than the oxidation bed thickness that forms on trenched side-wall; And

Remove oxide layer by wet etching process from trenched side-wall,

Thereby the section of described groove is outward-dipping near the top of described groove from groove.

197. a channel bottom that is used for forming at semiconductor substrate forms the method for thick oxide layer, comprising:

On described substrate, form cushion oxide layer;

Cvd nitride silicon thin layer on described cushion oxide layer;

Carry out anisotropic etching, getting on except that the nitrogenize silicon layer, and stay silicon nitride layer on the trenched side-wall from horizontal plane;

Use low pressure chemical vapour phase accumulation to handle and comprising deposited oxide layer on the horizontal surface of described channel bottom; And

Remove interlayer between oxide layer-nitride layer-oxide layer by etch processes from trenched side-wall.

198. a channel bottom that is used for forming at semiconductor substrate forms the method for thick oxide layer, comprising:

On the substrate that comprises described trenched side-wall and bottom, form the liner oxidation thin layer;

Form nitride layer at the top of described liner oxidation thin layer, and etch away the nitride layer on the horizontal surface, and stay on the trenched side-wall nitration case adjacent to cushion oxide layer;

Remove described cushion oxide layer from horizontal surface, expose the upper surface and the trench bottom surfaces of described substrate;

The horizontal surface that exposed is carried out anisotropic etching, removing the degree of depth of semi-conducting material, thereby form the groove bottom to expectation from the described bottom of described groove;

In the position growth oxide layer that the nitration case that is not comprised described groove bottom covers; And

Remove described nitride layer and cushion oxide layer,

Thereby thick bottom oxidization layer is extended along the described sidewall of described groove.

199. a power device that forms on single semiconductor substrate comprises:

Power transistor has charge balance structure, and it is formed in the groove;

The induction by current device, it forms adjacent to described power transistor, and separates with described power transistor by insulation layer; And

One or more charge balance grooves are formed under the described induction by current device,

Wherein, pass the continuity that described semiconductor substrate keeps charge balance.

200. a power device that forms on single semiconductor substrate comprises:

Power transistor has charge balance structure, and it is formed in the groove;

One or more diode structures, it forms adjacent to described power transistor, and separates with described power transistor by insulation layer; And

One or more charge balance grooves are formed under described one or more diode structure,

Wherein, pass the continuity that described semiconductor substrate keeps charge balance.

201. one kind is used to form the method for improving power device, comprises:

Semiconductor substrate with first conduction type is provided;

Formation extends into the groove of described substrate, and wherein, the bottom electrode that forms in the bottom of described groove separates with the bottom with trenched side-wall by first dielectric liner;

Forming dielectric layer between electrode on the described bottom electrode;

Form top electrode on the dielectric layer between the described electrode in the top of described groove, it separates with trenched side-wall by second insulating bushing;

Form the well region that has with second conduction type of described first conductivity type opposite adjacent to described groove;

In described well region, form source area with first conduction type; And after forming described well region and source area, silicon is applied to the upper surface of described top electrode,

Wherein, described top electrode comprises the gate terminal of described power device, and described silicide has reduced the equivalent series resistance of described device.

202. a method that is used to form the power device with lower equivalent series resistance comprises:

In a plurality of parallel grooves, form grid structure; And

Form the suicide material superficial layer, it is basically perpendicular to described a plurality of groove extension, is contacting with the intersection of described a plurality of parallel grooves.

203. a DC-DC converter circuit comprises:

High-side switch is made by the bigrid power transistor with the first grid electrode and second gate electrode, source electrode and drain electrode;

Low side switch is by having the first grid electrode and second gate electrode, being connected to the source electrode of described source electrode of described high-side switch and the bigrid power transistor of drain electrode is made;

First drive circuit is connected to the described first grid electrode of described high-side switch; And

Second drive circuit is connected to the described first grid electrode of described low side switch,

Wherein, connect described second gate electrode of described high-side switch and described low side switch to receive first drive signal and second drive signal respectively, so that each transistorized switching speed optimization.

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