TWI891309B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a first well region having a first conductivity type and disposed in a substrate. A first doped region has a second conductivity type and is buried in the first well region. The first doped region includes a middle portion and a peripheral portion, and the first well region includes a continuous region located directly above the middle portion. A second doped region having the second conductivity type is disposed in the first well region and located directly above the peripheral portion of the first doped region. A third doped region having the first conductivity type is disposed in the first well region. A first isolation structure is disposed in the first well region and located between the second doped region and the third doped region. An anode electrode is disposed above the substrate and electrically connected to the continuous region of the first well region. A cathode electrode is disposed above the substrate and electrically connected to the third doped region.

Description

semiconductor devices

This disclosure relates to semiconductor devices, and more particularly to semiconductor devices for use in Schottky diodes.

A Schottky barrier diode (SBD) is a semiconductor device that exploits the Schottky barrier properties of a metal-semiconductor junction. When the Schottky diode is forward biased (positive voltage applied to the anode and negative voltage applied to the cathode), carriers conduct. However, when the Schottky diode is reverse biased (negative voltage applied to the anode and positive voltage applied to the cathode), carriers are less likely to conduct. Therefore, the Schottky diode has a unidirectional rectifying effect. Because the Schönbahn energy barrier is lower than the junction energy barrier of P-type and N-type semiconductors, the forward bias voltage and voltage drop of Schönbahn diodes are lower than those of PN junction diodes. Furthermore, Schönbahn diodes have very fast switching speeds, making them suitable for low-power, high-current, and high-speed switching applications.

However, Schork diodes have a low withstand voltage under reverse bias and a high leakage current under reverse bias. Therefore, current Schork diodes still cannot fully meet all requirements.

In light of this, the present disclosure proposes a semiconductor device for a Schork diode. By increasing the area and proportion of the N-type semiconductor region by arranging the P-type semiconductor region at the anode end, the device can increase the on-state current of the Schork diode under forward bias. Furthermore, the device can suppress leakage current under reverse bias, keeping the off-state leakage current within an acceptable range. Furthermore, the device can increase the breakdown voltage under reverse bias, thereby improving the electrical performance of the Schork diode.

According to one embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a first well region, a first doped region, a second doped region, a third doped region, a first isolation structure, an anode electrode, and a cathode electrode. The first well region has a first conductivity type and is disposed in the substrate. The first doped region has a second conductivity type and is buried in the first well region. The first doped region includes a central portion and a peripheral portion, and the first well region includes a continuous block directly above the central portion. The second doped region has the second conductivity type and is disposed in the first well region and directly above the peripheral portion of the first doped region. The third doped region has the first conductivity type and is disposed in the first well region. The first isolation structure is disposed in the first well region and is located between the second doped region and the third doped region. An anode electrode is disposed on the substrate and electrically connected to the continuous block of the first well region. A cathode electrode is disposed on the substrate and electrically connected to the third doped region.

To make the features of this disclosure more clearly understood, the following examples are given below, along with accompanying drawings, for a detailed description.

100: Semiconductor devices

101: Base

101A: Semiconductor substrate

101B: Epitaxial layer

103: Buried Layer

105: First Well Area

105C: Continuous Block

107: Third Mixed Area

109: First doping area

110: First mixed area

110C: Middle part

110C-1, 110C-2, 110C-3: Long strips

110P: Peripheral area

112: Second mixed area

114-1: First Isolation Structure

114-2: Second Isolation Structure

114-3: Third Isolation Structure

115: Second Well Area

117: Second mixed area

120:Conductive structure

121: Dielectric layer

123: Gap

130: Anode electrode

131, 141, 151: Metal layer

132, 134, 142, 152: Contact plugs

136: Metal silicide

140: Cathode electrode

150: Interlayer dielectric layer

A-A: Section tangent line

E: Framed area

S101, S103, S105, S107, S109, S111, S113, S115: Steps

To facilitate understanding of the following, this disclosure may be read in conjunction with the accompanying drawings and detailed descriptions. The specific embodiments herein are described in detail with reference to the corresponding drawings, and the working principles of the specific embodiments of this disclosure are illustrated. Furthermore, for the sake of clarity, the features in the drawings may not be drawn to scale, and the sizes of some features in some drawings may be intentionally exaggerated or reduced.

Figure 1 is a schematic top view of a semiconductor device according to one embodiment of the present disclosure.

FIG2 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure, drawn along the cross-sectional line A-A in FIG1.

Figure 3 is a schematic top view of a semiconductor device according to another embodiment of the present disclosure.

Figure 4 is a schematic top view of a semiconductor device according to yet another embodiment of the present disclosure.

Figure 5 is a graph showing the forward current-forward voltage characteristic curves of a semiconductor device according to an embodiment of the present disclosure and a comparative example in the on-state, as well as an enlarged view of the framed area E.

Figure 6 is a graph showing the reverse current-reverse voltage characteristic curves of a semiconductor device in an embodiment and a comparative example in the off-state.

Figures 7, 8, 9, and 10 are schematic cross-sectional views illustrating certain stages of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

This disclosure provides several different embodiments that can be used to implement various features of the disclosure. For simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, a statement below regarding "a first feature formed on or above a second feature" may mean "the first feature and the second feature are directly in contact" or "an additional feature exists between the first and second features," such that the first and second features are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and/or textual notations. This repetition is for simplicity and clarity and is not intended to indicate a relationship between different embodiments and/or configurations.

Furthermore, when spatially relative terms such as "below," "lower," "down," "above," "upper," "top," "bottom," and similar terms are used in this disclosure to describe the relative relationship of one element or feature to another (or multiple) elements or features in the drawings, for ease of description. In addition to the orientations shown in the drawings, these spatially relative terms are also used to describe possible orientations of the semiconductor device during use and operation. Depending on the orientation of the semiconductor device (rotated 90 degrees or other orientations), the spatially relative terms used to describe its orientation should be interpreted in a similar manner.

Although this disclosure uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and do not in themselves imply or represent any prior number of the elements, nor do they represent the order in which one element is arranged relative to another, or the order in which one element is manufactured. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, meaning that even without the specific wording "about" or "substantially," the meaning of "about" or "substantially" may be implied.

The terms "couple," "coupled," and "electrically connected" mentioned in this disclosure include any direct and indirect electrical connection methods. For example, if a first component is described as being coupled to a second component, it means that the first component can be directly electrically connected to the second component or indirectly electrically connected to the second component through other devices or connection methods.

Although the following describes the present invention using specific embodiments, the principles of the present invention can also be applied to other embodiments. Furthermore, to avoid obscuring the spirit of the present disclosure, certain details may be omitted. Such omitted details are within the scope of knowledge of a person of ordinary skill in the art.

This disclosure relates to a semiconductor device for a Schork diode. By increasing the area and proportion of the N-type semiconductor region by arranging a P-type semiconductor region at the anode side, the device improves the Schork diode's on-state current. Simultaneously, the P-type semiconductor region at the anode side suppresses leakage current during reverse bias, keeping the Schork diode's off-state leakage current within an acceptable range. Furthermore, the disclosed semiconductor device can also increase its breakdown voltage during reverse bias. Therefore, according to the embodiments disclosed herein, the overall electrical performance of the Schottky diode can be improved, including increasing the on-state current, suppressing the off-state leakage current, and increasing the breakdown voltage under reverse bias.

FIG. 1 is a schematic top view of a semiconductor device 100 according to an embodiment of the present disclosure. To simplify the diagram, FIG. 1 only illustrates some features of the semiconductor device. For other features, see FIG. 2 , which is a schematic cross-sectional view of the semiconductor device 100. As shown in FIG. 1 , semiconductor device 100 includes a first well region 105 of a first conductivity type, such as an N-type well region. A first doped region 110 of a second conductivity type, such as a P-type doped region, is buried within first well region 105. First doped region 110 includes a central portion 110C and a peripheral portion 110P. When viewed from above, peripheral portion 110P is an annular region, such as a rectangular annular region, while central portion 110C is an elongated region. The annular region of peripheral portion 110P surrounds the elongated region of central portion 110C, and each end of the elongated region is connected to two sides of the annular region. Furthermore, the elongated section of the central portion 110C may include a plurality of elongated sections, such as the two elongated sections 110C-1 and 110C-2 shown in FIG. 1 , but the present invention is not limited thereto. The central portion 110C may include another number of elongated sections, with both ends of each elongated section 110C-1 and 110C-2 connected to two sides of the annular section of the peripheral portion 110 P. In one embodiment, the long axes of the two elongated sections 110C-1 and 110C-2 are parallel to each other. Semiconductor device 100 further includes a second doped region 112 of a second conductivity type, such as a P-type doped region, disposed within first well region 105. Second doped region 112 is located directly above peripheral portion 110P of first doped region 110. When viewed from above, second doped region 112 is an annular region, such as a rectangular annular region. In one embodiment, second doped region 112 can completely overlap with peripheral portion 110P of first doped region 110 in vertical projection.

Furthermore, the first well 105 includes a continuous region 105C located directly above the middle portion 110C of the first doped region 110. The first doped region 110 is completely absent from the continuous region 105C of the first well 105, and the second doped region 112 surrounds the continuous region 105C. The semiconductor device 100 further includes an anode electrode 130 located directly above the second doped region 112 and the continuous region 105C of the first well 105. The anode electrode 130 is electrically connected to the continuous region 105C of the first well 105. In one embodiment, the anode electrode 130 is, for example, a rectangular region when viewed from above. Continuing with FIG. 1 , the semiconductor device 100 further includes a conductive structure 120 disposed directly above the second doped region 112 and the peripheral portion 110P of the first doped region 110. In one embodiment, the conductive structure 120 is, for example, a polysilicon layer. When viewed from above, the conductive structure 120 is an annular region, such as a rectangular region. The annular region of the conductive structure 120 covers a portion of the second doped region 112, leaving another portion of the second doped region 112 exposed. Furthermore, the anode electrode 130 covers a portion of the conductive structure 120. Furthermore, the semiconductor device 100 includes a third doped region 107 and a first heavily doped region 109 disposed within the first well region 105. Both the third doped region 107 and the first heavily doped region 109 have a first conductivity type. For example, the third doped region 107 is an N-type well region, and the first heavily doped region 109 is an N-type heavily doped region. A cathode electrode 140 is disposed directly above the third doped region 107 and the first heavily doped region 109 and is electrically connected to the first heavily doped region 109 and the third doped region 107. In one embodiment, when viewed from above, the cathode electrode 140 is, for example, an annular region, and the annular region of the cathode electrode 140 surrounds the rectangular region of the anode electrode 130 and the annular region of the conductive structure 120. Furthermore, when viewed from above, a portion of the first isolation structure 114-1 is located between the cathode electrode 140 and the conductive structure 120. The first isolation structure 114-1 is an annular region, for example, a rectangular annular region.

FIG2 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure, taken along the cross-sectional line A-A in FIG1. As shown in FIG2, semiconductor device 100 includes a substrate 101. In some embodiments, substrate 101 may be composed of silicon (Si), germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or a III-V compound semiconductor, such as gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), other similar compound semiconductors, or combinations thereof. In addition, the substrate 101 can be a P-type or N-type semiconductor substrate, or a semiconductor on insulator (SOI) substrate.

In one embodiment, semiconductor device 100 includes a buried layer 103 of a first conductivity type, such as an n-type buried layer (NBL), and a first well region 105 of the first conductivity type, such as an N-type well region, disposed within substrate 101. Buried layer 103 is located directly below first well region 105 and directly contacts the bottom surface of first well region 105. A first doped region 110 of the second conductivity type, such as a P-type doped region, is buried in the first well region 105. The first doped region 110 includes a central portion 110C and a peripheral portion 110P. The central portion 110C includes elongated portions 110C-1 and 110C-2. The peripheral portion 110P and the central portion 110C are located at the same depth within the first well region 105, and the bottom surfaces of the peripheral portion 110P and the bottom surfaces of the central portion 110C are both higher than the bottom surface of the first well region 105. Furthermore, in some embodiments, the doping concentrations of the peripheral portion 110P and the central portion 110C are the same. A second doped region 112 of the second conductivity type, such as a P-type doped region, is also disposed within the first well region 105. The second doped region 112 is located directly above the peripheral portion 110P of the first doped region 110. The bottom surface of the second doped region 112 directly contacts the top surface of the peripheral portion 110P of the first doped region 110. In vertical projection, the second doped region 112 does not overlap at all with the central portion 110C of the first doped region 110. In some embodiments, the doping concentration of the second doped region 112 can be higher than the doping concentration of the peripheral portion 110P of the first doped region 110. In other embodiments, the doping concentration of the second doped region 112 may be the same as or lower than the doping concentration of the peripheral portion 110 P. Referring to both Figures 1 and 2 , because both ends of the central portion 110C of the first doped region 110 are connected to the peripheral portion 110 P, and the second doped region 112 directly contacts the peripheral portion 110P of the first doped region 110, the second doped region 112, which has the second conductivity type, and the peripheral portion 110P and central portion 110C of the first doped region 110 are connected to each other, thereby jointly suppressing off-state leakage current under reverse bias.

Still referring to FIG. 2 , the first well region 105 includes a continuous block 105C located directly above the middle portion 110C of the first doped region 110. According to some embodiments of the present disclosure, the continuous block 105C of the first well region 105 is completely free of the first doped region 110 or other P-type doped regions. This increases the area and proportion of the N-type semiconductor region used to conduct the on-state current, thereby increasing the on-state current of the Schorky diode. Furthermore, the second doped region 112 surrounds the continuous block 105C of the first well region 105. The bottom surface of the continuous block 105C directly contacts the top surface of the middle portion 110C of the first doped region 110, and the side surfaces of the continuous block 105C directly contact the side surfaces of the second doped region 112. Furthermore, portions of the first well region 105 are located between the middle portion 110C and the peripheral portion 110P of the first doped region 110, and a portion of the first well region 105 is located between the elongated portions 110C-1 and 110C-2 of the middle portion 110C. The continuous block 105C of the first well region 105 directly contacts the top surfaces of these aforementioned portions of the first well region 105. The semiconductor device 100 further includes an anode electrode 130 disposed on the substrate 101 and electrically connected to the continuous region 105C of the first well region 105. In one embodiment, the anode electrode 130 includes a metal layer 131 and a plurality of contact plugs 132. The metal layer 131 is disposed on the surface of the interlayer dielectric layer 150, and the contact plugs 132 are disposed within the interlayer dielectric layer 150. The metal layer 131 and the plurality of contact plugs 132 are both composed of a metal capable of forming a Schottky contact, such as gold (Au), silver (Ag), platinum (Pt), tungsten (W), titanium (Ti), aluminum (Al), nickel (Ni), cobalt (Co), or a combination thereof. In some embodiments, the metal layer 131 and the plurality of contact plugs 132 have the same composition, and the plurality of contact plugs 132 of the anode electrode 130 penetrate the interlayer dielectric layer 150 to directly contact the continuous region 105C of the first well region 105. In addition, semiconductor device 100 further includes a conductive structure 120 and a dielectric layer 121 disposed directly above second doped region 112, wherein dielectric layer 121 is located between conductive structure 120 and second doped region 112. Conductive structure 120 is electrically connected to metal layer 131 of anode electrode 130 via contact plug 134 within interlayer dielectric layer 150. In some embodiments, conductive structure 120 is, for example, a polysilicon layer, and dielectric layer 121 is, for example, a silicon oxide layer. Conductive structure 120 and dielectric layer 121 may be fabricated together with the gate electrode and gate dielectric layer of other transistor devices. By disposing the conductive structure 120 directly above the second doped region 112 and electrically connecting it to the anode electrode 130, the conductive structure 120 can provide electric field dispersion during reverse bias, thereby increasing the breakdown voltage during reverse bias.

In addition, the semiconductor device 100 further includes a third doped region 107 of the first conductivity type, such as an N-type doped region, disposed within the first well region 105. The third doped region 107 surrounds the first doped region 110 and the second doped region 112. A first heavily doped region 109 of the first conductivity type, such as an N-type heavily doped region (N ⁺ ), is disposed within the third doped region 107. The doping concentration of the first heavily doped region 109 is higher than the doping concentration of the third doped region 107. Cathode electrode 140 is disposed on substrate 101. Cathode electrode 140 includes a metal layer 141 and a contact plug 142. Metal layer 141 is disposed on the surface of interlayer dielectric layer 150. Contact plug 142 is disposed within interlayer dielectric layer 150 and penetrates interlayer dielectric layer 150 to directly contact first heavily doped region 109, thereby electrically connecting cathode electrode 140 to third doped region 107 and first heavily doped region 109. In some embodiments, the composition of cathode electrode 140 can be the same as that of anode electrode 130. The first isolation structure 114-1 is disposed within the first well region 105 and between the second doped region 112 and the third doped region 107 to electrically isolate the anode and cathode of the semiconductor device 100. In some embodiments, the first isolation structure 114-1 is, for example, a field oxide (FOX) or a shallow trench isolation (STI).

Still referring to FIG. 2 , the semiconductor device 100 further includes a second well region 115 of a second conductivity type, such as a P-type well region, disposed within the substrate 101 . The second well region 115 is adjacent to the side surfaces of the first well region 105 and surrounds the first well region 105 . The bottom surface of the second well region 115 may be higher than the bottom surface of the first well region 105 , and the top surface of the second well region 115 may be higher than the top surface of the first doped region 110 . In addition, a second heavily doped region 117 of a second conductivity type, such as a P-type heavily doped region (P ⁺ ), is disposed in the second well region 115, and the doping concentration of the second heavily doped region 117 is higher than the doping concentration of the second well region 115. The second well region 115 and the second heavily doped region 117 can be electrically coupled to the base (bulk) potential via other conductive lines (not shown) on the interlayer dielectric layer 150 and other contact plugs (not shown) in the interlayer dielectric layer 150. Furthermore, a second isolation structure 114-2 is disposed within substrate 101, between third doped region 107 and second well region 115, and surrounds third doped region 107 to electrically isolate the cathode and base terminals of semiconductor device 100. Furthermore, a third isolation structure 114-3 is disposed within substrate 101 and surrounds second well region 115 to electrically isolate semiconductor device 100 from other adjacent components. In some embodiments, second isolation structure 114-2 and third isolation structure 114-3 are, for example, field oxide layers (FOX) or shallow trench isolation (STI).

When the Schorl diode of semiconductor device 100 is forward biased, the on-state current is primarily conducted through the first well region 105 of the first conductivity type (e.g., N-type). When the Schorl diode of semiconductor device 100 is reverse biased, the depletion region formed between the first and second doped regions 110 and 112 of the second conductivity type (e.g., P-type) and the first well region 105 of the first conductivity type (e.g., N-type) has a pinching effect on the off-state leakage current. According to some embodiments of the present disclosure, there is no second conductivity type (e.g., P-type) doped region on the surface of the central region of the anode terminal of the Schottky diode of the semiconductor device 100. That is, no second conductivity type (e.g., P-type) doped region is disposed directly above the middle portion 110C of the first doped region 110. The second doped region 112 surrounds the first well region. Compared to a comparative example in which a doped region of the second conductivity type (e.g., P-type) is disposed directly above the middle portion 110C, the area of the first well region 105 used to conduct the on-state current is increased in the embodiment of the present disclosure. This provides more current paths, thereby increasing the on-state current of the Schorky diode. Furthermore, the first doped region 110 and the second doped region 112 can still provide sufficient clamping for the off-state leakage current, maintaining the off-state leakage current level of the Schorky diode of the semiconductor device 100 within an acceptable range. Therefore, the semiconductor device 100 disclosed herein can effectively improve the overall performance of the Schottky diode.

FIG3 is a schematic top view of a semiconductor device 100 according to another embodiment of the present disclosure. In the semiconductor device 100 of FIG3 , the central portion 110C of the first doped region 110 includes a plurality of separated strips 110C-3. The long axes of these strips 110C-3 extend along the Y-axis and are parallel to each other. Each strip 110C-3 has two ends connected to two sides of the annular block of the peripheral portion 110P of the first doped region 110. The number of strips 110C-3 can be adjusted as needed and is not limited to the number shown in FIG3 . Other features of the semiconductor device 100 of FIG3 can be found in the detailed description of FIG1 above and will not be repeated here.

FIG4 is a schematic top view of a semiconductor device 100 according to yet another embodiment of the present disclosure. In the semiconductor device 100 of FIG4 , a central portion 110C of the first doped region 110 includes a plurality of strip portions 110C-1, 110C-2, and 110C-3. The strip portions 110C-1 and 110C-2 are separated from each other, with their long axes extending along the X-axis and being parallel to each other. The plurality of strip portions 110C-3 are separated from each other, with their long axes extending along the Y-axis and being parallel to each other. Furthermore, the long axes of the strip portions 110C-1 and 110C-2 are perpendicular to the long axes of the plurality of strip portions 110C-3. The ends of the strip portions 110C-1 and 110C-2 are each connected to the left and right sides of the annular block of the peripheral portion 110P of the first doped region 110. Each strip portion 110C-3 also has its ends connected to the top and bottom sides of the annular block of the peripheral portion 110P of the first doped region 110. The number of these strip portions 110C-1, 110C-2, and 110C-3 can be adjusted as needed and is not limited to the number shown in FIG. 4 , to achieve both the goal of clamping the off-state leakage current and increasing the on-state current. Other features of the semiconductor device 100 in FIG. 4 can be found in the detailed description of FIG. 1 and will not be repeated here.

FIG. 5 is a graph showing the forward current If versus forward voltage Vf characteristic curves of a semiconductor device according to an embodiment and a comparative example of the present disclosure in the on state, as well as an enlarged view of the framed area E. The horizontal coordinate represents the forward voltage Vf in volts (V), and the vertical coordinate represents the forward current If in amperes (A). The embodiment in FIG. 5 is, for example, the semiconductor device 100 shown in FIG. 1 and FIG. 2 . The comparative example is to add a doped region of a second conductivity type (e.g., P-type) to the semiconductor device 100 in FIG. 1 and FIG. 2 . For example, the comparative example is to add two elongated P-type doped regions directly above the elongated portions 110C-1 and 110C-2 of the middle portion 110C of the first doped region 110, so that the well region of the first conductivity type (e.g., N-type) on the surface of the central region of the anode end of the Schottky diode in the comparative example is discontinuous. As shown in Figure 5, under the same forward voltage Vf, the forward current If of the Schroky diode of the embodiment is greater than the forward current If of the Schroky diode of the comparative example. For example, when the forward voltage Vf is 0.3V, the forward current If of the Schroky diode of the embodiment is increased by 33.7% compared to the forward current If of the Schroky diode of the comparative example. This indicates that according to the embodiments of the present disclosure, the current of the Schroky diode in the on-state can be effectively increased.

FIG. 6 is a graph showing the reverse current Ir versus reverse voltage Vr characteristics of a semiconductor device in the off state according to an embodiment and a comparative example of the present disclosure. The horizontal axis represents reverse voltage Vr in volts (V), and the vertical axis represents reverse current Ir in amperes (A). The embodiment and comparative example in FIG. 6 are the same as those in FIG. For details, please refer to the description of FIG. 5 and will not be repeated here. As shown in FIG6 , under the same reverse voltage Vr, the reverse current Ir of the Schönle diode of the embodiment is only slightly increased compared to the reverse current Ir of the Schönle diode of the comparative example. The reverse current Ir of the Schönle diode of the embodiment and the comparative example is roughly the same, indicating that the Schönle diode of the embodiment can suppress the leakage current in the off state within an acceptable range. Furthermore, according to Figures 5 and 6, the ratio of the on-state current (Ion) to the off-state current (Ioff) of the Schork diode increases from 7.2E4 in the comparative example to 5.4E4 in the exemplary embodiment. Overall, the semiconductor device of the exemplary embodiment of the present disclosure suppresses the off-state leakage current of the Schork diode within a reasonable range. Furthermore, as shown in Figure 6, the breakdown voltage of the Schork diode of the exemplary embodiment increases by approximately 3V compared to that of the comparative example, demonstrating a slight improvement in the breakdown voltage of the Schork diode.

Figures 7, 8, 9, and 10 are schematic cross-sectional views illustrating certain stages of a method for fabricating a semiconductor device 100 according to another embodiment of the present disclosure. Referring to Figure 7, in step S101, a semiconductor substrate 101A, such as a silicon (Si) wafer, a silicon carbide (SiC) wafer, or a P-type semiconductor substrate, is first provided. Next, a buried layer 103, such as an N-type buried layer (NBL), is formed within the semiconductor substrate 101A using a patterned mask (e.g., a patterned photoresist) and an ion implantation process. Then, an epitaxial growth process is used to form an epitaxial layer 101B on the semiconductor substrate 101A. The buried layer 103 is embedded in the semiconductor substrate 101A and the epitaxial layer 101B. The epitaxial layer 101B is, for example, a silicon (Si) epitaxial layer, a silicon carbide (SiC) epitaxial layer, or a P-type semiconductor epitaxial layer. The semiconductor substrate 101A and the epitaxial layer 101B together constitute the base 101.

Still referring to FIG. 7 , in step S103, a first isolation structure 114-1, a second isolation structure 114-2, and a third isolation structure 114-3 are formed within the epitaxial layer 101B of the substrate 101. The second isolation structure 114-2 surrounds the first isolation structure 114-1, and the third isolation structure 114-3 surrounds the second isolation structure 114-2. In one embodiment, the first isolation structure 114-1, the second isolation structure 114-2, and the third isolation structure 114-3 are all field oxide layers (FOX). These isolation structures can be formed simultaneously using a patterned mask and thermal oxidation process. In another embodiment, the first isolation structure 114-1, the second isolation structure 114-2, and the third isolation structure 114-3 are all shallow trench isolation (STI) structures. These isolation structures can be formed simultaneously by etching shallow trenches in a substrate, filling the shallow trenches with a dielectric material, and performing a chemical mechanical planarization process.

Continuing with FIG. 7 , in step S105 , a first well region 105 , such as an N-type well region, is formed in the epitaxial layer 101B of the substrate 101 using a patterned mask (e.g., patterned photoresist) and an ion implantation process. The first well region 105 is located directly above and in contact with the buried layer 103 . In one embodiment, the width of the first well region 105 can be the same as the width of the buried layer 103 . Furthermore, a second isolation structure 114-2 surrounds the first well region 105 , and the first isolation structure 114-1 is located within the first well region 105 .

Next, referring to FIG. 8 , in step S107, a first doped region 110, such as a P-type doped region, is formed in the first well region 105 using a patterned mask (e.g., a patterned photoresist) and an ion implantation process. The first doped region 110 is buried in the first well region 105 and includes a ring-shaped peripheral portion 110P and strip portions 110C-1 and 110C-2 of a strip-shaped middle portion 110C. A first isolation structure 114-1 surrounds the first doped region 110 and can contact the peripheral portion 110P. Furthermore, using another patterned mask (e.g., patterned photoresist) and an ion implantation process, a second well region 115, such as a P-type well region, is formed in the epitaxial layer 101B of the substrate 101. The second well region 115 surrounds and abuts the side surfaces of the first well region 105. The top surface of the second well region 115 is higher than the top surface of the first doped region 110, and the bottom surfaces of the second well region 115 and the first doped region 110 are both higher than the bottom surface of the first well region 105. In some embodiments, the doping concentration of the second well region 115 can be the same as the doping concentration of the first doped region 110, for example, 1E12 atoms/ ^cm2 to 1E13 atoms/ ^cm2 . In addition, the third isolation structure 114 - 3 surrounds the outer periphery of the second well region 115 , and the second isolation structure 114 - 2 is located between the first well region 105 and the second well region 115 .

Continuing with FIG. 8 , in step S109, a patterned mask (e.g., patterned photoresist) and ion implantation process are used to form a second doped region 112, e.g., a P-type doped region, in the first well region 105. The second doped region 112 is located directly above the peripheral portion 110P of the first doped region 110, and the bottom surface of the second doped region 112 directly contacts the peripheral portion 110P. On the top surface of the side portion 110P, in the vertical projection direction, the second doped region 112 completely overlaps with the peripheral portion 110P of the first doped region 110, but the second doped region 112 does not completely overlap with the central portion 110C. The first isolation structure 114-1 surrounds the outer periphery of the second doped region 112 and contacts the second doped region 112. Furthermore, another patterned mask (e.g., patterned photoresist) and another ion implantation process are used to form a third doped region 107, e.g., an N-type doped region, in the first well region 105. The third doped region 107 surrounds the first doped region 110 and the second doped region 112, and the third doped region 107 is aligned with the first doped region 110 and the second doped region 112. The second doped region 112 is separated by a distance, with the first isolation structure 114-1 located between the third doped region 107 and the second doped region 112. The top surface of the third doped region 107 is higher than the top surface of the first doped region 110, and the top surface of the third doped region 107 is coplanar with the top surface of the second doped region 112. Furthermore, the third doped region 107 is located between the first isolation structure 114-1 and the second isolation structure 114-2, and the second well region 115 is located between the second isolation structure 114-2 and the third isolation structure 114-3.

Next, referring to FIG. 9 , in step S111, a dielectric layer 121 and a conductive structure 120 are formed directly above the second doped region 112 and the first isolation structure 114-1 using deposition, photolithography, and etching processes. In one embodiment, the dielectric layer 121 is composed of, for example, silicon oxide, and the conductive structure 120 is composed of, for example, polysilicon. A silicon oxide layer and a polysilicon layer can be sequentially deposited on the substrate 101, and a patterned photoresist is formed on the polysilicon layer to serve as an etching mask. An etching process is then used to simultaneously etch the silicon oxide layer and the polysilicon layer to form the dielectric layer 121 and the conductive structure 120. Then, a spacer material layer is deposited longitudinally on the surface of substrate 101 and conductive structure 120. An anisotropic dry etching process is used to remove the horizontal portion of the spacer material layer to form spacers 123 on the sidewalls of dielectric layer 121 and conductive structure 120. In some embodiments, dielectric layer 121, conductive structure 120, and spacers 123 may be fabricated together with the gate structure of other transistor devices.

Continuing with FIG. 9 , in step S113, a patterned mask (e.g., a patterned photoresist) and an ion implantation process are used to form a first heavily doped region 109, e.g., an N-type heavily doped region, within the third doped region 107. The doping concentration of the first heavily doped region 109 is higher than that of the third doped region 107. In one embodiment, the doping concentration of the first heavily doped region 109 is, for example, 1E13 atoms/cm ² to 1E14 atoms/cm ² . The first heavily doped region 109 is located between the first isolation structure 114-1 and the second isolation structure 114-2 and can be fabricated together with the source/drain regions of other transistor devices. Furthermore, using another patterned mask (e.g., a patterned photoresist) and another ion implantation process, a second heavily doped region 117, such as a P-type heavily doped region, is formed within the second well region 115. In one embodiment, the doping concentration of the second heavily doped region 117 is, for example, 1E13 atoms/ ^cm² to 1E14 atoms/ ^cm² . The second heavily doped region 117 is located between the second isolation structure 114 - 2 and the third isolation structure 114 - 3 , and the second heavily doped region 117 may be formed together with the base region of other devices.

Next, referring to FIG. 10 , in step S115, in one embodiment, a metal layer is first deposited on the surface of substrate 101 and conductive structure 120. A heat treatment process is then performed to allow the metal to react with silicon in substrate 101 and conductive structure 120 to form a metal silicide 136, such as cobalt silicide (CoSix). Metal silicide 136 is formed on the surfaces of conductive structure 120, continuous region 105C of first well 105, first heavily doped region 109, and second heavily doped region 117, thereby reducing the contact resistance between these regions and subsequently formed conductive contacts. Next, an interlayer dielectric layer 150 is deposited over the substrate 101. A patterned mask and etching process are used to form a plurality of contact holes within the interlayer dielectric layer 150, exposing portions of the surfaces of the conductive structure 120, the continuous region 105C of the first well region 105, the first heavily doped region 109, and the second heavily doped region 117. Subsequently, a metal layer is deposited on the surface of the interlayer dielectric layer 150, and the metal material is simultaneously filled into the aforementioned plurality of contact holes to form contact plugs 132, 134, 142, and 152. The metal material layer is then patterned using photolithography and etching processes to form metal layers 131, 141, and 151, wherein metal layer 131 is connected to contact plugs 132 and 134, and metal layer 131 and contact plug 132 constitute anode electrode 130, and conductive structure 120 is electrically connected to metal layer 131 of anode electrode 130 via contact plug 134. Furthermore, metal layer 141 is connected to contact plug 142 and forms cathode electrode 140. Metal layer 151 is connected to contact plug 152 and serves as substrate electrode. Bulk potential can be provided to substrate 101 via substrate electrode, second heavily doped region 117, and second well region 115, completing the fabrication of semiconductor device 100.

According to some embodiments of the present disclosure, by arranging a first doped region and a second doped region of a second conductivity type (e.g., P-type) within a first well region of a first conductivity type (e.g., N-type), the first well region forms a continuous region on the central surface of the anode terminal, providing more current conduction paths and thereby increasing the on-state current of the Schorky diode. Furthermore, the first doped region and the second doped region of the second conductivity type (e.g., P-type) can provide sufficient clamping for the off-state leakage current of the Schorky diode, keeping the off-state leakage current within an acceptable range. Furthermore, the layout of the first and second doped regions, as well as the electrical coupling of the conductive structure directly above the second doped region to the anode electrode, can increase the breakdown voltage of the Schottky diode under reverse bias. Therefore, the semiconductor device disclosed herein can effectively enhance the overall performance of the Schottky diode.

The above description is merely a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the patent application for this invention shall fall within the scope of this invention.

100: Semiconductor devices

101: Base

103: Buried Layer

105: First Well Area

105C: Continuous Block

107: Third Mixed Area

109: First doping area

110: First mixed area

110C: Middle part

110C-1, 110C-2: Long strips

110P: Peripheral area

112: Second mixed area

114-1: First Isolation Structure

114-2: Second Isolation Structure

114-3: Third Isolation Structure

115: Second Well Area

117: Second mixed area

120:Conductive structure

121: Dielectric layer

130: Anode electrode

131, 141: Metal layer

132, 134, 142: Contact plugs

140: Cathode electrode

150: Interlayer dielectric layer

Claims (15)

A semiconductor device comprises: a substrate; a first well region having a first conductivity type and disposed within the substrate; a first doped region having a second conductivity type and buried within the first well region, wherein the first doped region includes a central portion and a peripheral portion, and the first well region includes a continuous block directly above the central portion; a second doped region having the second conductivity type and disposed within the first well region and directly above the peripheral portion of the first doped region; a third doped region having the first conductivity type and disposed within the first well region; a first isolation structure disposed within the first well region and between the second doped region and the third doped region; An anode electrode disposed on the substrate and electrically connected to the continuous region of the first well; and a cathode electrode disposed on the substrate and electrically connected to the third doped region. The semiconductor device of claim 1, wherein the second doped region surrounds the continuous block of the first well region, and a bottom surface of the continuous block directly contacts a top surface of the middle portion of the first doped region, and a side surface of the continuous block directly contacts a side surface of the second doped region. The semiconductor device as described in claim 1, wherein the second doped region directly contacts the top surface of the peripheral portion of the first doped region, and in the vertical projection direction, the second doped region does not overlap with the middle portion of the first doped region. The semiconductor device of claim 1, wherein the first well region includes a portion located between the middle portion and the peripheral portion of the first doped region, and the continuous block of the first well region directly contacts the top surface of the portion. The semiconductor device of claim 1 further comprises a conductive structure and a dielectric layer disposed directly above the second doped region, wherein the dielectric layer is located between the conductive structure and the second doped region, and the conductive structure is electrically connected to the anode electrode. The semiconductor device of claim 1, wherein, when viewed from a top view, the peripheral portion of the first doped region includes an annular block, and the middle portion includes a strip-shaped block, the annular block surrounds the strip-shaped block, and both ends of the strip-shaped block are respectively connected to the annular block. A semiconductor device as described in claim 6, wherein the elongated block includes a plurality of elongated portions, and the long axis directions of the plurality of elongated portions are parallel to each other, perpendicular to each other, or a combination thereof, and both ends of each of the elongated portions are respectively connected to the annular block. The semiconductor device of claim 1 further comprises: a second well region having the second conductivity type, disposed in the substrate and adjacent to a side surface of the first well region, wherein the second well region is electrically coupled to a base potential; and a second isolation structure disposed in the substrate and located between the third doped region and the second well region. The semiconductor device of claim 8, wherein the second well region surrounds the first well region, and the third doped region surrounds the first doped region and the second doped region. The semiconductor device as described in claim 8, wherein the bottom surface of the first doped region and the bottom surface of the second well region are both higher than the bottom surface of the first well region. The semiconductor device of claim 8 further comprises: a first heavily doped region having the first conductivity type, disposed within the third doped region, wherein the cathode electrode directly contacts the first heavily doped region; and a second heavily doped region having the second conductivity type, disposed within the second well region. The semiconductor device of claim 8, wherein a top surface of the second well region is higher than a top surface of the first doped region. The semiconductor device as described in claim 1 further includes a buried layer having the first conductivity type, disposed in the substrate, directly below the first well region, and directly contacting the bottom surface of the first well region. The semiconductor device of claim 1, wherein the anode electrode and the cathode electrode are composed of metal, and the semiconductor device includes a Schottky diode. The semiconductor device of claim 1, wherein the anode electrode directly contacts the continuous region of the first well region.