TWI419237B - Fabrication method of power semiconductor structure with reduced gate impenance - Google Patents

Claims (10)

A method of fabricating a low-threshold impedance power semiconductor structure, comprising the steps of: forming a gate trench in a germanium substrate; forming a dielectric layer covering at least an inner surface of the gate structure; forming a gate polysilicon Structured in the gate trench; implanting a dopant into the germanium substrate through the gate polysilicon structure; forming an isolation layer covering the gate polysilicon structure; applying a heat-distribution process Forming at least a body surrounding the gate polysilicon structure; removing the isolation layer to expose the gate polysilicon structure; and depositing a metal layer on the dielectric layer and the gate polysilicon structure, and applying a thermal process, A self-aligned metal telluride layer is formed on the upper surface of the gate polysilicon structure. The method of fabricating a low-threshold impedance power semiconductor structure according to claim 1, wherein the step of implanting the dopant in the germanium substrate comprises: implanting the first dopant of the first conductivity type And implanting a second dopant of the second conductivity type in the germanium substrate; wherein the thermal diffusion process causes the first dopant and the second dopant to diffuse to form the A body and a source doped region. A method of fabricating a low-threshold impedance power semiconductor structure according to claim 1, wherein the step of implanting a dopant in the germanium substrate is implanting a first dopant of a first conductivity type Within the germanium substrate, the thermal diffusion process causes the first dopant to diffuse to form the body. The method for manufacturing a low-threshold impedance power semiconductor structure according to claim 3, after the step of applying the thermal diffusion process to form the body, before the step of removing the isolation layer, further comprising implanting the second conductive A second dopant of the type is within the tantalum substrate. A method of fabricating a power semiconductor structure having a low gate resistance according to claim 4, wherein the step of implanting the second dopant in the germanium substrate further comprises applying another thermal diffusion process. To form the source doped region. A method of fabricating a power semiconductor structure having a low gate resistance according to claim 1, wherein the isolation layer is made of tantalum nitride. A method of fabricating a power semiconductor structure having a low gate resistance according to the first aspect of the patent application, wherein the dielectric layer is composed of yttrium oxide. The method for fabricating a power semiconductor structure having a low gate resistance according to claim 1, wherein the step of forming the self-aligned metal germanide layer comprises: depositing a metal layer in a comprehensive manner; and applying a thermal process And forming the self-aligned metal telluride layer on the interface between the metal layer and the gate polysilicon structure. A method of fabricating a low-threshold impedance power semiconductor structure according to claim 1, wherein the step of forming an isolation layer covering at least the gate polysilicon structure is along a surface of the germanium substrate and the gate polysilicon structure Ups and downs, a layer of isolation is fully deposited. The method for fabricating a power semiconductor structure having a low gate resistance according to claim 1, wherein the step of forming the isolation layer covering at least the gate polysilicon structure comprises: depositing a spacer layer on the germanium substrate and the gate Extremely polycrystalline structure and filling the gate trench; and utilizing an etch back process to leave a portion of the isolation layer within the gate trench.