TWI838929B - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device includes an epitaxial layer, at least one gate trench, and at least one trench gate structure. The gate trench includes a lower gate trench and an upper gate trench, and a width of the lower gate trench is less than a width of the upper gate trench. The trench gate structure is disposed in the gate trench, and the trench gate structure includes a bottom gate structure, a middle gate structure, and a top gate structure. The thickness of the second gate dielectric layer of the middle gate structure is less than the thickness of the first gate dielectric layer of the bottom gate structure. The thickness of the third gate dielectric layer of the top gate structure is less than the thickness of the second gate dielectric layer of the middle gate structure. The first, second, and third gate electrodes are separated from each other.

Description

Semiconductor device and method for manufacturing the same

This disclosure relates to semiconductor technology, in particular to semiconductor devices including trench gates and methods for manufacturing the same.

Metal oxide semiconductor field effect transistors (MOSFETs) can be used as power transistors in integrated circuits, usually operating under high voltage and/or high current conditions. In general, power MOSFETs can be roughly divided into two categories: planar gate MOSFETs and trench gate MOSFETs.

For trench gate MOSFET, the gate is usually accommodated in the trench, which has the advantages of small footprint and low parasitic capacitance. However, in terms of on-resistance (Ron), breakdown voltage (BVD) and switching loss, traditional trench gate MOSFET still cannot meet all the requirements of power electronic applications. Therefore, it is still necessary to provide a power MOSFET that can exhibit low on-resistance ( _Ron ) and high breakdown voltage (BVD).

In view of this, the present disclosure provides a semiconductor device and a manufacturing method thereof to enhance the electrical performance of conventional semiconductor devices in the prior art.

According to some embodiments of the present disclosure, a semiconductor device includes an epitaxial layer, at least one gate trench and at least one trench gate structure. The gate trench includes a lower gate trench and an upper gate trench, and the width of the lower gate trench is smaller than the width of the upper gate trench. The trench gate structure is disposed in the gate trench, and the trench gate structure includes a bottom gate structure, a middle gate structure and a top gate structure. The bottom gate structure is disposed at the lower portion of the lower gate trench, and the bottom gate structure includes a first gate electrode and a first gate dielectric layer. The middle gate structure is disposed at the upper portion of the lower gate trench, and the middle gate structure includes a second gate electrode and a second gate dielectric layer. The thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer. The top gate structure is disposed in the upper gate trench, and the top gate structure includes a third gate electrode and a third gate dielectric layer. The thickness of the third gate dielectric layer is less than the thickness of the second gate dielectric layer. The first gate electrode, the second gate electrode, and the third gate electrode are separated from each other.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: providing an epitaxial layer; forming an upper gate trench in the epitaxial layer; forming a lower gate trench in the epitaxial layer, wherein the width of the lower gate trench is smaller than the width of the upper gate trench; forming a bottom gate structure at the bottom of the lower gate trench, wherein the bottom gate structure includes a first gate electrode and a first gate dielectric layer; forming a bottom gate structure at the bottom of the lower gate trench ... A middle gate structure is formed on the upper portion of the upper gate, wherein the middle gate structure includes a second gate electrode and a second gate dielectric layer, and the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; and a top gate structure is formed in the upper gate trench, wherein the top gate structure includes a third gate electrode and a third gate dielectric layer, and the thickness of the third gate dielectric layer is less than the thickness of the second gate dielectric layer. The first gate electrode, the second gate electrode, and the third gate electrode are separated from each other.

According to some embodiments of the present disclosure, the first gate electrode, the second gate electrode, and the third gate electrode are separated from each other, and different biases can be applied to conduct the channel of the adjacent trench gate structure. In addition, since the work functions of the first gate electrode, the second gate electrode, and the third gate electrode can be appropriately adjusted, the electric field distribution around the trench gate structure (especially the bottom) can be adjusted accordingly. Therefore, the on-resistance (R _ON ) of the semiconductor device can be reduced, and the breakdown voltage (BVD) can be increased. In addition, since the gate dielectric layer close to the source doped region is thinner than the gate dielectric layer far from the source doped region, the transconductance of the semiconductor device can be improved.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the help of the attached drawings.

10-1: First Area

10-2: Second Area

100:Semiconductor devices

101: Substrate

102: Epitaxial layer

104: Matrix doping area

105: Bottom

106: Source doping region

108: Covering dielectric layer

110: Source contact hole

112:Heavy mixing area

114: Source contact

116: Drain contact

120: Gate groove

130: Patterned mask layer

132: Bottom layer

134: Top floor

140: Upper gate groove

150: Lower gate groove

200: Trench gate structure

201: Lowest side

210: Bottom gate structure

212: First gate dielectric layer

214: First gate electrode

215: Lowest side

220: Middle gate structure

222: Second gate dielectric layer

224: Second gate electrode

230: Top gate structure

232: Third gate dielectric layer

234: Third gate electrode

312: Dielectric materials

314: Conductive materials

D1: Depth

T12:Thickness

T22:Thickness

T32:Thickness

W2: Width

W4: Width

W14: Width

W24: Width

W34: Width

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail, and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Figures 2 to 10 are cross-sectional schematic diagrams of intermediate stages of a semiconductor device manufacturing method according to some embodiments of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. With the different orientations of the semiconductor device (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1, a semiconductor device 100 is provided. In the embodiment, the semiconductor device 100 is a power transistor capable of operating at a high operating voltage such as 100 to 500 volts and/or a high operating current such as 0.1 to 100 amperes, but is not limited thereto. The semiconductor device 100 includes a substrate 101 of a first conductivity type such as an n-type. The substrate 101 is made of a semiconductor material, such as silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN) or other suitable semiconductor materials, and the substrate 101 can serve as a drain region of the semiconductor device 100. An epitaxial layer 102 is disposed on the substrate 101. The epitaxial layer 102 may be made of silicon, gallium nitride, silicon carbide or other suitable materials. A substrate doped region 104 of a second conductivity type, such as a p-type, may be formed on the upper portion of the epitaxial layer 102. A source doped region 106 is formed in the epitaxial layer 102 (or in the substrate doped region 104) and adjacent to the upper surface of the epitaxial layer 102. The source doped region 106 has a second conductivity type, such as a p-type, which is different from the first conductivity type of the substrate doped region 104. A capping dielectric layer 108 is disposed on the source doped region 106. A source contact hole 110 is formed in the capping dielectric layer 108, and the bottom surface of the source contact hole 110 is lower than the top surface of the source doped region 106. A heavily doped region 112 of a second conductivity type, such as a p-type, is formed below the source contact hole 110 and between two adjacent trench gate structures 200, and the doping concentration of the heavily doped region 112 is greater than the doping concentration of the body doped region 104. A source contact 114 is formed on the capping dielectric layer 108 and fills the source contact hole 110. The source contact 114 is electrically connected to the source doping region 106 through the source contact 114 disposed in the source contact hole 110. The semiconductor device 100 may further include a drain contact 116 disposed on the back side of the substrate 101, such that the drain contact 116 is disposed below the trench gate structure 200.

1 , at least one gate trench 120 is disposed in the epitaxial layer 102. In some embodiments, two gate trenches 120 are disposed in the first region 10-1 and the second region 10-2 of the semiconductor device 100, respectively. The sidewalls of each gate trench 120 may be covered by the body doping region 104 or the source doping region 106, and the lowest surface 201 of the gate trench 120 is lower than the bottom surface 105 of the body doping region 104. Each gate trench 120 may extend along a first direction (e.g., Y direction) parallel to the main surface of the substrate 101. Each gate trench 120 includes at least two sub-trench, such as an upper gate trench 140 and a lower gate trench 150. The lower gate trench 150 is disposed below the upper gate trench 140, and the width W2 of the lower gate trench 150 (e.g., along the second direction X) is smaller than the width W4 of the upper gate trench 140 (e.g., along the second direction X). In some embodiments, the lower gate trench 150 may include a vertical sidewall and an arc-shaped bottom surface, the entire vertical sidewall of the lower gate trench 150 is completely covered by the substrate doping region 104, and a portion of the arc-shaped bottom surface of the lower gate trench 150 may be deeper than the bottom surface 105 of the substrate doping region 104.

The upper gate trench 140 is disposed above the lower gate trench 150, and the upper gate trench 140 includes a vertical sidewall and an arc-shaped lower corner connected to the upper edge of the lower gate trench 150. The upper portion of the vertical sidewall of the upper gate trench 140 may be covered by the source doping region 106, and the lower portion of the vertical sidewall of the upper gate trench 140 may be covered by the substrate doping region 104.

The semiconductor 100 further includes at least one trench gate structure 200, for example, two trench gate structures 200 respectively disposed in the gate trench 120. Each trench gate structure 200 may include a bottom gate structure 210, a middle gate structure 220, and a top gate structure 230 sequentially disposed from bottom to top. The bottom gate structure 210 is disposed at the lower portion of the lower gate trench 150, and the bottom gate structure 210 includes a first gate dielectric layer 212 and a first gate electrode 214. The first gate dielectric layer 212 includes a vertical portion having a thickness T12, and the first gate electrode 214 has a width W14. Based on different requirements, the bottom of the first gate dielectric layer 212 may have a thickness that is the same as or greater than the thickness T12 of the vertical portion of the first gate dielectric layer 212. The first gate dielectric layer 212 may be made of silicon oxide or a high dielectric constant (high-k, k>4) dielectric layer, but is not limited thereto. The lowest surface 215 of the first gate electrode 214 is lower than the bottom surface 105 of the substrate doped region 104. The first gate electrode 214 may be made of a conductive material such as polysilicon or a metal material, but is not limited thereto. To adjust the threshold voltage (V _TH ) of the channel in the body doping region 104 adjacent to the bottom gate structure 210 , the work function of the first gate electrode 214 may be adjusted by ion implanting appropriate dopants into the first gate electrode 214 or constructing the first gate electrode 214 using appropriate materials.

The middle gate structure 220 is disposed on the upper portion of the lower gate trench 150, and the middle gate structure 220 includes a second gate dielectric layer 222 and a second gate electrode 224. The second gate dielectric layer 222 may be disposed on the sidewall and bottom surface of the second gate electrode 224. In other words, the second gate dielectric layer 222 may extend from below the second gate electrode 224 to the sidewall of the lower gate trench 150. In addition, the second gate dielectric layer 222 has a vertical portion with a thickness T22. In the present embodiment, the thickness T22 of the second gate dielectric layer 222 is less than the thickness T12 of the first gate dielectric layer 212. The second gate dielectric layer 222 may be made of silicon oxide or a high dielectric constant (high-k, k>4) dielectric layer, but is not limited thereto. The bottom surface of the second gate electrode 224 is higher than the bottom surface 105 of the substrate doped region 104. In addition, the width W24 of the second gate electrode 224 is greater than the width W14 of the first gate electrode 214. The second gate electrode 224 may be made of a conductive material such as polysilicon or a metal material, but is not limited thereto. To adjust the threshold voltage (V _TH ) of the channel in the body doping region 104 near the middle gate structure 220 , the work function of the second gate electrode 224 may be adjusted by adding dopants to the second gate electrode 224 or constructing the second gate electrode 224 using a suitable material.

The top gate structure 230 is disposed in the upper gate trench 140, and the top gate structure 230 includes an arc-shaped lower corner extending beyond the upper edge of the middle gate structure 220. The top gate structure 230 includes a third gate dielectric layer 232 and a third gate electrode 234. The third gate dielectric layer 232 may be disposed on the sidewall and bottom surface of the third gate electrode 234. In other words, the third gate dielectric layer 232 may extend from below the third gate electrode 234 to the sidewall of the upper gate trench 140. In addition, the third gate dielectric layer 232 includes a vertical portion having a thickness T32. In the present embodiment, the thickness T32 of the third gate dielectric layer 232 is less than the thickness T22 of the second gate dielectric layer 222. The third gate dielectric layer 232 may be made of silicon oxide or a high dielectric constant (high-k, k>4) dielectric layer, but is not limited thereto. The top surface of the third gate electrode 234 is higher than the bottom surface of the source doped region 106, and the third gate electrode 234 includes an arc-shaped lower corner lower than the bottom surface of the source doped region 106. The width W34 of the third gate electrode 234 is greater than the width W24 of the second gate electrode 224. The third gate electrode 234 may be made of a conductive material such as polysilicon or a metal material, but is not limited thereto. In order to adjust the threshold voltage ( _VTH ) of the channel in the body doping region 104 adjacent to the top gate structure 230, the work function of the third gate electrode 234 may be adjusted by adding dopants to the third gate electrode 234 or by using a suitable material to construct the third gate electrode 234. In addition, since the gate dielectric layer close to the source doped region (such as the third gate dielectric layer 232) is thinner than the gate dielectric layer far from the source doped region (such as the first gate dielectric layer 212 and the second gate dielectric layer 222), the transconductance of the semiconductor device 100 can be improved.

In some embodiments of the present disclosure, the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 are separated from each other. In addition, the work function of one of the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 is different from the work function of the other two of the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234.

In some embodiments of the present disclosure, each trench gate structure 200 includes three discrete gate electrodes (e.g., a first gate electrode 214, a second gate electrode 224, and a third gate electrode 234) and three gate dielectric layers (e.g., a first gate dielectric layer 212, a second gate dielectric layer 222, and a third gate dielectric layer 232) having different thicknesses (e.g., thicknesses T12, T22, and T32). Therefore, during the operation of the semiconductor device 100, different biases may be applied to the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 to conduct the channel adjacent to the trench gate structure 200, thereby allowing current to flow from the drain contact 116 to the source doped region 106 and the source contact 114. In addition, since the work functions of the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 may be appropriately adjusted, the electric field distribution around (especially at the bottom of) the trench gate structure 200 may be adjusted accordingly. For example, compared to a conventional trench gate MOSFET having a single gate electrode in each gate trench, the peak electric field at the bottom of the trench gate structure 200 of the semiconductor device 100 can be reduced by at least 18.5%. Therefore, in some embodiments, the on-resistance (R _ON ) of the semiconductor device 100 can be reduced by at least 33.2%, and the breakdown voltage (BVD) can be improved by at least 6%.

In order to enable a person with ordinary knowledge in the field to implement the present invention, the manufacturing method of the disclosed semiconductor device is further described below.

FIG. 2 to FIG. 10 are cross-sectional schematic diagrams of intermediate stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 2, in the manufacturing stage shown in FIG. 2, an epitaxial layer 102 is formed on a substrate by an epitaxial growth method. The epitaxial layer 102 may be made of a semiconductor material having a first conductivity type (e.g., n-type). A patterned mask layer 130 including a bottom layer 132 and a top layer 134 may be formed on an upper surface of the epitaxial layer 102. The portion of the epitaxial layer 102 exposed by the patterned mask layer 130 may be etched, thereby forming at least one trench in the epitaxial layer 102. In some embodiments, at least one trench formed in the epitaxial layer 102 includes two upper gate trenches 140 formed in the first region 10-1 and the second region 10-2, respectively, and each upper gate trench 140 has a depth D1 and a width W4.

Referring to FIG. 3, in the manufacturing stage shown in FIG. 3, photolithography and etching processes are performed to form a lower gate trench 150 below the corresponding upper gate trench 140. The width W2 of the lower gate trench 150 is smaller than the width W4 of the upper gate trench 140. In addition, the upper gate trench 140 has a plurality of arc-shaped lower corners, which are respectively connected to the upper edges of the lower gate trench 150.

Referring to FIG. 4, in the manufacturing stage shown in FIG. 4, a deposition process is performed to form a layer of dielectric material 312 on the sidewalls of the upper gate trench 140 and the lower gate trench 150. Then, the upper gate trench 140 and the lower gate trench 150 are filled with a conductive material 314. According to actual needs, the conductive material 314 can be made of a semiconductor material or a metal material. In addition, by using a suitable material or ion implanting a suitable dopant, the work function of the conductive material 314 can be adjusted to a predetermined value.

5, in the manufacturing stage shown in FIG5, the bottom gate structure 210 is formed by etching back the dielectric material 312 and the conductive material 314 in the upper gate trench 140 and the lower gate trench 150 shown in FIG4. For example, the dielectric material 312 and the conductive material 314 in the upper gate trench 140 and the lower gate trench 150 may be etched back until the top surfaces of the dielectric material 312 and the conductive material 314 are located in the lower gate trench 150. By performing the etching back process, the bottom gate structure 210 including the first gate dielectric layer 212 and the first gate electrode 214 may be obtained. In addition, the first gate dielectric layer 212 and the first gate electrode 214 may have a lowest surface 201 and a lowest surface 215, respectively.

Referring to FIG. 6 , in the manufacturing stage shown in FIG. 6 , a deposition process is performed to form a layer of dielectric material 312 on the sidewalls of the upper gate trench 140 and the lower gate trench 150 and on the top surface of the bottom gate structure 210 . The thickness of the dielectric material 312 is less than the thickness of the first gate dielectric layer 212 .

After the manufacturing stage shown in FIG. 6, a conductive material (not shown) is filled into the upper portion of the lower gate trench 150 and the upper gate trench 140. The conductive material can be made of a semiconductor material or a metal material according to actual needs. In addition, the work function of the conductive material can be adjusted to a predetermined value by using a suitable material or ion implanting a suitable dopant.

7 , in the manufacturing stage shown in FIG. 7 , the dielectric material and the conductive material filled in the upper gate trench 140 and the lower gate trench 150 are etched back to form a middle gate structure 220 on the upper portion of the lower gate trench 150. By performing the etching back process, the sidewall of the upper gate trench 140 can be exposed, and the top surface of the middle gate structure 220 is substantially flush with the bottom surface of the upper gate trench 140. The middle gate structure 220 includes a second gate dielectric layer 222 and a second gate electrode 224. In some embodiments, the thickness T12 of the first gate dielectric layer 212 is greater than the thickness T22 of the second gate dielectric layer 222, and the width W14 of the first gate electrode 214 is less than the width W24 of the second gate electrode 224.

8 , at the manufacturing stage shown in FIG. 8 , a top gate structure 230 including a third gate dielectric layer 232 and a third gate electrode 234 is formed in the top gate trench 140. In some embodiments, the top gate structure 230 includes a curved lower corner extending beyond the upper edge of the middle gate structure 220. The thickness T32 of the third gate dielectric layer 232 is less than the thickness T22 of the second gate dielectric layer 222. The third gate electrode 234 includes a curved lower corner, and the width W34 of the third gate electrode 234 is greater than the width W24 of the second gate electrode 224. In some embodiments, the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 are separated from each other. In addition, the work function of one of the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 is different from the work function of the other two of the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234.

9 , in the manufacturing stage shown in FIG. 9 , a substrate doping region 104 of a second conductivity type (e.g., p-type) is formed in the epitaxial layer 102 by performing an ion implantation process. The substrate doping region 104 covers both sides of each lower gate trench 150, and the lowest surface 215 of the first gate electrode 214 is lower than the bottom surface of the substrate doping region 104. Then, a source doping region 106 of a first conductivity type (e.g., n-type) is formed in the epitaxial layer 102 by performing another ion implantation process. The source doped region 106 covers both sides of each upper gate trench 140, and the bottom surface of the third gate structure 230 is lower than the bottom surface of the source doped region 106.

Referring to FIG. 10 , in the manufacturing stage shown in FIG. 10 , a photolithography and etching process is performed to form a source contact hole 110 in the source doped region 106 between two adjacent trench gate structures 200. Then, an ion implantation process is performed to form a heavily doped region 112 of a second conductivity type (e.g., p-type) below the source contact hole 110 and between the two adjacent trench gate structures 200.

After the manufacturing stage shown in FIG. 10 , other processes may be performed to manufacture the desired semiconductor device, such as the semiconductor device 100 shown in FIG. 1 .

According to some embodiments of the present disclosure, the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 are separated from each other, and different biases can be applied to conduct the channels adjacent to the trench gate structure 200. In addition, since the work functions of the first gate electrode 214, the second gate electrode 224, and the third gate electrode 234 can be properly adjusted, the electric field distribution around (especially at the bottom) the trench gate structure 200 can be adjusted accordingly. Therefore, the on-resistance (R _ON ) of the semiconductor device 100 can be reduced, and the breakdown voltage (BVD) can be increased. In addition, since the gate dielectric layer close to the source doped region is thinner than the gate dielectric layer far from the source doped region, the transconductance of the semiconductor device can be improved.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10-1: First Area

10-2: Second Area

100:Semiconductor devices

101: Substrate

102: Epitaxial layer

104: Matrix doping area

105: Bottom

106: Source doping region

108: Covering dielectric layer

110: Source contact hole

112:Heavy mixing area

114: Source contact

116: Drain contact

120: Gate groove

140: Upper gate groove

150: Lower gate groove

200: Trench gate structure

201: Lowest side

210: Bottom gate structure

212: First gate dielectric layer

214: First gate electrode

215: Lowest side

220: Middle gate structure

222: Second gate dielectric layer

224: Second gate electrode

230: Top gate structure

232: Third gate dielectric layer

234: Third gate electrode

T12:Thickness

T22:Thickness

T32:Thickness

W2: Width

W4: Width

W14: Width

W24: Width

W34: Width

Claims (20)

A semiconductor device comprises: an epitaxial layer; at least one gate trench, comprising a lower gate trench and an upper gate trench, wherein the width of the lower gate trench is smaller than the width of the upper gate trench; at least one trench gate structure, disposed in the at least one gate trench, wherein the At least one trench gate structure includes: a bottom gate structure disposed at the bottom of the lower gate trench, wherein the bottom gate structure includes a first gate electrode and a first gate dielectric layer; a middle gate structure disposed at the top of the lower gate trench, wherein the middle gate The structure includes a second gate electrode and a second gate dielectric layer, the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; and a top gate structure, which is arranged in the upper gate trench, wherein the top gate structure includes a third gate electrode and a third gate The third gate dielectric layer extends to the epitaxial layer outside the upper gate trench, and the thickness of the third gate dielectric layer is less than the thickness of the second gate dielectric layer, wherein the first gate electrode, the second gate electrode and the third gate electrode are separated from each other. A semiconductor device as described in claim 1, wherein the width of the second gate electrode is greater than the width of the first gate electrode, and the width of the second gate electrode is less than the width of the third gate electrode. A semiconductor device as described in claim 1, wherein the second gate dielectric layer extends from below the second gate electrode to the sidewall of the lower gate trench. A semiconductor device as described in claim 1, wherein the top gate structure includes a curved lower corner extending beyond the upper edge of the middle gate structure. A semiconductor device as described in item 1 of the patent application, wherein the third gate electrode includes an arc-shaped lower corner. A semiconductor device as described in claim 1, wherein the third gate dielectric layer extends from below the third gate electrode to the sidewall of the upper gate trench. A semiconductor device as described in claim 1, wherein the work function of one of the first gate electrode, the second gate electrode, and the third gate electrode is different from the work function of the other two of the first gate electrode, the second gate electrode, and the third gate electrode. The semiconductor device as described in item 1 of the patent application scope further includes a substrate doping region disposed in the epitaxial layer, wherein the bottom surface of the second gate electrode is higher than the bottom surface of the substrate doping region. A semiconductor device as described in Item 8 of the patent application, wherein the lowest surface of the first gate electrode is lower than the bottom surface of the substrate doping region. The semiconductor device as described in item 1 of the patent application scope further includes a source doping region, which is arranged in the substrate doping region, and the conductivity type of the source doping region is different from the conductivity type of the substrate doping region, wherein the top surface of the third gate electrode is higher than the bottom surface of the source doping region. The semiconductor device as described in item 1 of the patent application scope further includes a drain contact disposed below the at least one trench gate structure. A semiconductor device as described in claim 1, wherein the at least one trench gate structure includes two trench gate structures, and the semiconductor device further includes a heavily doped region disposed at the top surface of the base doped region and between the trench gate structures, and the conductive type of the heavily doped region is the same as the conductive type of the base doped region. A method for manufacturing a semiconductor device, comprising: providing an epitaxial layer; forming an upper gate trench in the epitaxial layer; forming a lower gate trench in the epitaxial layer, wherein the width of the lower gate trench is smaller than the width of the upper gate trench; forming a bottom gate structure at the lower portion of the lower gate trench, wherein the bottom gate structure comprises a first gate electrode and a first gate dielectric layer; forming a middle gate structure at the upper portion of the lower gate trench, wherein the middle gate The structure includes a second gate electrode and a second gate dielectric layer, the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; and a top gate structure is formed in the top gate trench, wherein the top gate structure includes a third gate electrode and a third gate dielectric layer, the thickness of the third gate dielectric layer is less than the thickness of the second gate dielectric layer, wherein the first gate electrode, the second gate electrode and the third gate electrode are separated from each other. The method for manufacturing a semiconductor device as described in claim 13, wherein forming the bottom gate structure at the lower portion of the lower gate trench comprises: forming a dielectric material on the sidewalls of the upper gate trench and the lower gate trench; filling a conductive material in the upper gate trench and the lower gate trench; and etching back the dielectric material and the conductive material until the top surfaces of the dielectric material and the conductive material are located in the lower gate trench. A method for manufacturing a semiconductor device as described in claim 13, wherein forming the middle gate structure on the upper portion of the lower gate trench comprises: forming a dielectric material on the sidewalls of the upper gate trench and the top surface of the bottom gate structure; and etching back the dielectric material to expose the sidewalls of the upper gate trench. A method for manufacturing a semiconductor device as described in claim 13, wherein the width of the second gate electrode is greater than the width of the first gate electrode, and the width of the second gate electrode is less than the width of the third gate electrode. A method for manufacturing a semiconductor device as described in claim 13, wherein the top gate structure includes a curved lower corner extending beyond the upper edge of the middle gate structure. A method for manufacturing a semiconductor device as described in claim 13, wherein the third gate electrode includes a curved lower corner. A method for manufacturing a semiconductor device as described in claim 13, wherein the work function of one of the first gate electrode, the second gate electrode, and the third gate electrode is different from the work function of the other two of the first gate electrode, the second gate electrode, and the third gate electrode. The method for manufacturing a semiconductor device as described in claim 13 further includes forming a substrate doping region in the epitaxial layer, the substrate doping region covering both sides of the lower gate trench, wherein the lowest surface of the first gate electrode is lower than the bottom surface of the substrate doping region.

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