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WO2017067062A1 - 一种双栅极薄膜晶体管及其制作方法、以及阵列基板 - Google Patents

一种双栅极薄膜晶体管及其制作方法、以及阵列基板 Download PDF

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Publication number
WO2017067062A1
WO2017067062A1 PCT/CN2015/098965 CN2015098965W WO2017067062A1 WO 2017067062 A1 WO2017067062 A1 WO 2017067062A1 CN 2015098965 W CN2015098965 W CN 2015098965W WO 2017067062 A1 WO2017067062 A1 WO 2017067062A1
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Prior art keywords
gate
layer
channel
film transistor
drain
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English (en)
French (fr)
Inventor
张合静
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/907,666 priority Critical patent/US10153377B2/en
Publication of WO2017067062A1 publication Critical patent/WO2017067062A1/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of field display, and in particular to a dual gate thin film transistor, a method of fabricating the same, and an array substrate.
  • a flat panel display represented by a liquid crystal LCD and an organic light emitting diode (OLED) has been developed in the direction of large size and high resolution, and the thin film transistor TFT has been widely concerned as a core component of the flat panel display industry.
  • Double-gate thin-film transistors are favored for their unmatched single-gate thin-film transistors.
  • a double gate thin film transistor is easier to control the threshold voltage Vth, high illumination stability, and the like.
  • the double gate thin film transistor is prone to high leakage (ie, the off current Ioff is high), thereby affecting the basic electrical properties and applications of the dual gate transistor.
  • the technical problem to be solved by the present invention is to provide a dual-gate thin film transistor, a manufacturing method thereof, and an array substrate, which can effectively reduce leakage problems caused by an effective channel length between a source and a drain, and improve the double Electrical properties of the gated crystalline thin film tube.
  • a technical solution adopted by the present invention is to provide a method for fabricating a dual gate thin film transistor, the method comprising: sequentially forming a first gate, a gate insulating layer, and a semiconductor on a first substrate.
  • a layer and an etch barrier layer wherein, in the region where the etch barrier layer covers the semiconductor layer, three open regions are opened to expose the semiconductor layer corresponding to the three open regions; and the corresponding exposed semiconductor layer Forming a drain, an independent electrode, and a source in sequence; wherein a first channel is formed between the drain and the independent electrode, and a second is formed between the independent electrode and the source a channel that exposes the etch barrier layer corresponding to the first channel and the second channel; the exposed etch barrier layer and the drain electrode, the source electrode, the independent Forming an insulating protective layer on a surface of the electrode; and forming a second gate on a region of the insulating protective layer opposite to the first gate.
  • the second gate covers at least the first channel and the second channel.
  • the second gate is etched into the first region, and the cross-sectional area of the etched first region relative to the semiconductor layer is less than or equal to the cross-sectional area of the independent electrode.
  • the second gate is etched into the first region, and the cross-sectional area of the etched first region relative to the semiconductor layer is less than or equal to the cross-sectional area of the independent electrode.
  • the step of forming an insulating protective layer on the exposed etch stop layer and the surface of the drain electrode, the source electrode, and the independent electrode is specifically:
  • the insulating protection is formed by sputtering silicon oxide SiO or/and silicon nitride SiN on the surface of the etch barrier layer and the drain, the source, and the individual electrode.
  • a dual-gate thin film transistor including: a first substrate, which is sequentially stacked on the first substrate a metal layer, a gate insulating layer, a semiconductor layer, an etch barrier layer, a second metal layer, an insulating protective layer, and a third metal layer; the first metal layer is a first gate, and the third metal layer is a second gate, wherein the first gate is connected to the second gate; wherein, in the region where the etch barrier layer covers the semiconductor layer, three open regions are opened to correspond to the three openings
  • the semiconductor layer of the region is not covered by the etch barrier layer; the second metal layer corresponds to the semiconductor layer not covered by the etch barrier layer, and is sequentially divided into a drain, an independent electrode, and a source. Forming a first channel between the drain and the independent electrode, forming a second channel between the independent electrode and the source, corresponding to the first channel and the first
  • the etch stop layer of the two channels is exposed
  • the second gate covers at least the first channel and the second channel.
  • the second gate is etched into the first region, and the cross-sectional area of the etched first region relative to the semiconductor layer is less than or equal to the cross-sectional area of the independent electrode.
  • the second gate is etched into the first region, and the cross-sectional area of the etched first region relative to the semiconductor layer is less than or equal to the cross-sectional area of the independent electrode.
  • the insulating protective layer comprises silicon oxide SiO or/and silicon nitride SiN.
  • an effective channel length between the source and the drain is a sum of lengths corresponding to the first channel and the second channel
  • an effective channel length between the source and the drain is a length corresponding to each of the first channel and the second channel, first The sum of the distances between the channel and the second channel.
  • another technical solution adopted by the present invention is to provide an array substrate, which includes the double gate thin film transistor described in any one of the above.
  • the beneficial effects of the present invention are: different from the prior art, adding a separate electrode between the source and the drain, so that the effective channel length between the source and the drain when the double gate thin film transistor is turned on Less than the effective channel length between the source and drain when turned off.
  • the leakage problem caused by the effective channel length between the source and the drain improves the electrical performance of the double-gate thin film transistor and increases its stability.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a dual gate thin film transistor of the present invention
  • FIG. 2 is a cross-sectional structural view showing an embodiment of a dual gate thin film transistor of the present invention
  • FIG. 3 is a cross-sectional structural view showing another embodiment of the dual gate thin film transistor of the present invention.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a dual-gate thin film transistor of the present invention.
  • the manufacturing method of this embodiment includes the following steps:
  • S101 sequentially forming a first gate, a gate insulating layer, a semiconductor layer, and an etch barrier layer on the first substrate.
  • the metal film layer is first formed on the first substrate by deposition, and the metal film layer is exposed through the first photomask to etch the metal film layer into the first gate.
  • the first substrate includes a glass substrate and a quartz substrate.
  • the substrate may be other substrates, which is not limited herein.
  • the metal film layer includes at least one of aluminum Al, molybdenum Mo, copper Cu, and silver Ag. In other embodiments, other metals may be used, and are not limited herein.
  • the deposition process generally refers to the deposition of foreign matter on the surface of the substrate to form a thin film, also known as vapor deposition.
  • a metal film layer is formed on the surface of the first substrate by a metal substance.
  • the metal film layer can also be realized by other deposition methods, which is not limited herein.
  • the etching process generally refers to a process of removing a portion of the film layer on the film that is not masked by the resist, thereby forming a pattern identical to the resist film on the film layer.
  • the etching process generally includes dry etching and wet etching, which is not limited in this embodiment, as long as the first gate can be etched on the metal film layer.
  • a gate insulating layer is deposited on the surface of the first gate.
  • the gate insulating layer includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx. In other embodiments, other insulating materials may be used, which is not limited herein.
  • a semiconductor layer (active layer) is deposited on the surface of the gate insulating layer and in a region opposite to the first gate. Wherein, the semiconductor layer does not completely cover the gate insulating layer, and the cross-sectional area of the semiconductor layer is greater than or equal to the cross-sectional area of the first gate.
  • an etch stop layer is deposited on the surface of the semiconductor layer and the exposed gate insulating layer.
  • three open regions are opened in a region where the etch barrier layer covers the semiconductor layer, so that the semiconductor layers corresponding to the three open regions are exposed.
  • the size of the three open areas is not limited here, and can be set according to actual needs.
  • the first opening region, the second opening region, and the third opening region are used to respectively deposit a drain, a separate electrode, and a source.
  • S102 sequentially forming a drain, an independent electrode, and a source on the corresponding exposed semiconductor layer.
  • a drain, an independent electrode, and a source are sequentially formed on the corresponding exposed semiconductor layer. That is, a drain, an independent electrode, and a source are sequentially formed in each of the three open regions.
  • the drain, the individual electrodes, and the source may partially cover the etch stop.
  • a first channel is formed between the drain and the independent electrode, and a second channel is formed between the independent electrode and the source, so that an etch barrier corresponding to the first channel and the second channel is formed Exposed.
  • the drain, the independent electrode and the source may be formed by depositing a metal film layer on the corresponding exposed semiconductor layer and the etch barrier layer, exposing the metal film layer through the photomask, and etching the metal film layer. Etched into a drain, a separate electrode, and a source.
  • the independent electrode is used to reduce the effective channel length between the source and the drain when the double gate thin film transistor is turned on. That is, when the double gate thin film transistor is turned on, the effective channel length between the source and the drain is the sum of the first channel length and the second channel length. In the double gate thin film transistor is turned off, the effective channel length between the source and the drain is the sum of the first channel length, the second channel length, and the distance between the first channel and the second channel. .
  • an insulating protective layer is formed on the exposed etch barrier layer and the surfaces of the drain electrode, the source electrode, and the individual electrode.
  • the insulating barrier can be formed by sputtering silicon oxide SiO or/and silicon nitride SiN on the surface of the etch barrier layer and the drain, the source and the individual electrodes.
  • S104 forming a second gate on a region of the insulating protection layer opposite to the first gate.
  • a second gate is formed on the insulating protective layer with respect to the region of the first gate.
  • the first gate and the second gate are connected by via holes.
  • a metal film layer is first formed on the insulating protective layer by deposition, and the metal film layer is exposed through a photomask, and the metal film layer is etched into a second gate.
  • the second gate covers the first channel and the second channel. That is, the second gate covers the region of the insulating protective layer opposite to the semiconductor layer, and at least covers the first channel formed between the source and the independent electrode, and the second channel formed between the independent electrode and the drain.
  • the second gate is etched away from the first region, and the cross-sectional area of the etched first region relative to the semiconductor layer is less than or equal to the cross-sectional area of the independent electrode covering the semiconductor layer, so that the second gate can The first channel and the second channel are completely covered.
  • a metal film layer is formed on the insulating protective layer by deposition, the metal film layer is exposed through a photomask, the metal film layer is etched into a second gate, and the second gate is The first region is etched away such that the second gate is divided into two portions by the first region. The two portions separated by the first region by the first region can cover at least the first channel and the second channel, respectively.
  • the etched first region makes the second gate and the independent electrode have no overlapping area with each other, and effectively reduces the parasitic capacitance formed between the second gate and the independent electrode.
  • the above solution is different from the prior art in that a separate electrode is added between the source and the drain, so that the effective channel length between the source and the drain when the double gate thin film transistor is turned on is smaller than the source and the off time.
  • the effective channel length between the drains The longer the channel length is, the smaller the current of the double-gate thin film transistor is, and the above method makes the ratio of the on-state (off-state) current to the off-state current of the double-gate thin film transistor become larger, thereby solving the prior art.
  • the leakage problem caused by the effective channel length between the source and the drain improves the electrical performance of the double-gate thin film transistor and increases its stability.
  • FIG. 2 is a cross-sectional structural view of an embodiment of a dual gate thin film transistor of the present invention.
  • the dual gate thin film transistor of the embodiment includes: a first substrate 110, a first metal layer 120 sequentially stacked on the first substrate 110, a gate insulating layer 130, a semiconductor layer 140, an etch barrier layer 150, and a second The metal layer 160, the insulating protective layer 170, and the third metal layer 180.
  • the first metal layer 120 is a first gate
  • the third metal layer 180 is a second gate
  • the first gate is internally connected to the second gate through a via.
  • the second metal layer 160 includes a drain 161, a separate electrode 162, and a source 163.
  • 161 may also be defined as a source and 163 as a drain.
  • the first gate 120 partially covers the first substrate 110.
  • the first substrate 110 may be a glass substrate or a quartz substrate, and may be other substrates in other embodiments, which is not limited herein.
  • the gate insulating layer 130 completely covers the first gate 120 and the first substrate 110.
  • the semiconductor layer 140 is disposed in a region where the gate insulating layer 130 overlaps the first gate 120.
  • a region where the semiconductor layer 140 overlaps the gate insulating layer 130 is greater than or equal to a region where the gate insulating layer 130 overlaps with the first gate 120.
  • the etch barrier layer 150 covers the gate insulating layer 130 and the semiconductor layer 140, and three open regions are opened in the region where the etch barrier layer 150 covers the semiconductor layer 140, so that the semiconductor layer 140 corresponding to the three open regions is not etched.
  • the barrier layer 150 is covered. Among them, three open regions are covered by the second metal layer 160.
  • the second metal layer 160 corresponds to the semiconductor layer 140 not covered by the etch barrier layer 150, and is sequentially divided into a drain 161, an independent electrode 162 and a source 163, forming a first between the drain 160 and the individual electrode 162.
  • a channel forms a second channel between the individual electrode 162 and the source 163 to expose the etch stop layers corresponding to the first channel and the second channel.
  • the second metal layer 160 forms a drain 161 , a separate electrode 162 , and a source 163 in three open regions of the semiconductor layer 140 .
  • the length of the first channel formed between the drain 160 and the individual electrode 162 is L1
  • the length of the second channel formed between the individual electrode 162 and the source 163 is L2
  • the first channel and the second trench is L3 (the length of the section corresponding to the individual electrodes is L3).
  • the third metal layer (second gate) 180 is disposed in a region where the insulating protective layer 170 overlaps the first metal layer (first gate) 120.
  • the cross-sectional area of the third metal layer 180 may be smaller than the cross-sectional area of the first metal layer 120.
  • the material of the insulating protective layer 170 may include silicon oxide SiO or/and silicon nitride SiN, which is not limited herein.
  • the third metal layer (second gate) 180 covers at least the first channel and the second channel. That is, the third metal layer (second gate) 180 can at least completely cover the first channel and the second channel.
  • the source 163 and the drain 161 are connected through the semiconductor layer 140, and the effective channel length between the source 163 and the drain 161 is corresponding to the first channel and the second channel.
  • the sum of the lengths That is, when the double gate thin film transistor is turned on, since the individual electrode 162 is also conductive, the effective channel length between the source 163 and the drain 161 is the sum of L1 and L2.
  • the source 163 When the double gate thin film transistor is turned off, the source 163 is disconnected from the drain 161, and the effective channel length between the source 163 and the drain 161 is the length corresponding to each of the first channel and the second channel, The sum of the distances between the first channel and the second channel. That is, when the double gate thin film transistor is turned off, the effective channel length between the source 163 and the drain 161 is the sum of L1, L2, and L3.
  • the length L1 of the first channel, the length L2 of the second channel, and the distance L3 between the first channel and the second channel can be set according to actual needs, which is not limited herein.
  • the above solution is different from the prior art in that a separate electrode is added between the source and the drain, so that the effective channel length between the source and the drain when the double gate thin film transistor is turned on is smaller than the source and the off time.
  • the effective channel length between the drains The longer the channel length is, the smaller the current of the double-gate thin film transistor is, and the above method makes the ratio of the on-state (off-state) current to the off-state current of the double-gate thin film transistor become larger, thereby solving the prior art.
  • the leakage problem caused by the effective channel length between the source and the drain improves the electrical performance of the double-gate thin film transistor and increases its stability.
  • FIG. 3 is a cross-sectional structural view showing another embodiment of the dual gate thin film transistor of the present invention. This embodiment differs from the previous embodiment in the third metal layer (second gate) 280.
  • the third metal layer (second gate) 280 of the embodiment is etched away from the first region, and the cross-sectional area of the etched first region relative to the semiconductor layer 140 is less than or equal to the independent electrode 162 overlying the semiconductor layer 140.
  • the cross-sectional area is such that the second gate 280 can completely cover the first channel and the second channel.
  • the third metal layer (second gate) 280 is etched away from the first region, and the first region divides the third metal layer (second gate) 280 into two portions.
  • the two portions of the second gate 280 divided by the first region are at least capable of covering at least the first channel and the second channel, respectively.
  • the first region can make the second gate 280 and the individual electrodes 162 have no overlapping regions or small overlapping regions, and effectively reduce the parasitic capacitance formed between the second gate 280 and the individual electrodes 162.
  • the above solution is different from the prior art in that a separate electrode is added between the source and the drain, so that the effective channel length between the source and the drain when the double gate thin film transistor is turned on is smaller than the source and the off time.
  • the effective channel length between the drains The longer the channel length is, the smaller the current of the double-gate thin film transistor is, and the above method makes the ratio of the on-state (off-state) current to the off-state current of the double-gate thin film transistor become larger, thereby solving the prior art.
  • the leakage problem caused by the effective channel length between the source and the drain improves the electrical performance of the double-gate thin film transistor and increases its stability.
  • the arrangement of the second gate can reduce the parasitic capacitance formed between the second gate 280 and the individual electrode 162, and further improve the performance of the dual gate thin film transistor.
  • the present invention further provides an array substrate (not shown), which includes the double gate thin film transistor described in any of the above.
  • the present invention further provides a liquid crystal display device (not shown) including an upper substrate, a lower substrate, and a liquid crystal layer sandwiched between the upper substrate and the lower substrate.
  • the lower substrate includes the double gate thin film transistor described in any of the above.

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  • Electrodes Of Semiconductors (AREA)

Abstract

一种双栅极薄膜晶体管及其制作方法、阵列基板。其中，所述制作方法包括在第一基板（110）上依次形成第一栅极（120）、栅极绝缘层（130）、半导体层（140）以及刻蚀阻挡层（150）；在对应暴露的所述半导体层（140）上依次形成一漏极（161）、一独立电极（162）以及一源极（163）；在暴露的所述刻蚀阻挡层（150）以及所述漏极（161）、所述源极（163）、所述独立电极（162）的表面形成绝缘保护层（170）；以及在所述绝缘保护层（170）上相对所述第一栅极（120）的区域形成第二栅极（180）。通过上述方式，能够在不增加光罩的前提下，有效改善由于源极（163）和漏极（161）之间的有效沟道长度所引起的漏电问题，提高双栅极薄膜晶体管的电性能，增加其稳定性，简化制造工艺，节省成本。

Description

一种双栅极薄膜晶体管及其制作方法、以及阵列基板
【技术领域】
本发明涉及领域显示领域，特别是涉及一种双栅极薄膜晶体管及其制作方法、以及阵列基板。
【背景技术】
伴随着液晶LCD以及有机发光二极管OLED为代表的平板显示器向着大尺寸、高分辨率的方向发展，薄膜晶体管TFT作为平板显示行业的核心部件，也得到广泛的关注。
双栅极薄膜晶体管因具有单栅极薄膜晶体管无法比拟的有点，而倍受青睐。例如，双栅极薄膜晶体管较容易控制阈值电压Vth、照光稳定性高等。
然而，由于双栅极晶体管结构设计或制程中的差异，双栅极薄膜晶体管容易产生较高的漏电（即关断电流Ioff较高），从而影响双栅极晶体管的基本电性及应用。
【发明内容】
本发明主要解决的技术问题是提供一种双栅极薄膜晶体管及其制作方法、以及阵列基板，能够有效减小由于源极和漏极之间的有效沟道长度所引起的漏电问题，提高双栅极晶体薄膜管的电性能。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种双栅极薄膜晶体管的制作方法，所述方法包括：在第一基板上依次形成第一栅极、栅极绝缘层、半导体层以及刻蚀阻挡层；其中，在所述刻蚀阻挡层覆盖所述半导体层的区域开设有三个开口区域，使对应所述三个开口区域的半导体层暴露；在对应暴露的所述半导体层上依次形成一漏极、一独立电极以及一源极；其中，在所述漏极和所述独立电极之间形成第一沟道，在所述独立电极和所述源极之间形成第二沟道，使对应所述第一沟道和所述第二沟道的所述刻蚀阻挡层暴露；在暴露的所述刻蚀阻挡层以及所述漏电极、所述源电极、所述独立电极的表面形成绝缘保护层；以及在所述绝缘保护层上相对所述第一栅极的区域形成第二栅极。
其中，所述第二栅极至少覆盖所述第一沟道以及所述第二沟道。
其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
其中，在暴露的所述刻蚀阻挡层以及所述漏电极、所述源电极、所述独立电极的表面形成绝缘保护层的步骤具体为：
在所述刻蚀阻挡层以及所述漏极、所述源极以及所述独立电极的表面溅镀氧化硅SiO或/和氮化硅SiN形成所述绝缘保护。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种双栅极薄膜晶体管，所述双栅极薄膜晶体管包括：第一基板、依次层叠设置于所述第一基板上的第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、第二金属层、绝缘保护层以及第三金属层；所述第一金属层为第一栅极，所述第三金属层为第二栅极，且所述第一栅极连接所述第二栅极；其中，在所述刻蚀阻挡层覆盖在所述半导体层的区域开设有三个开口区域，使对应所述三个开口区域的半导体层未被所述刻蚀阻挡层覆盖；所述第二金属层对应未被所述刻蚀阻挡层覆盖的所述半导体层，被依次分割为一漏极、一独立电极以及一源极，在所述漏极和所述独立电极之间形成第一沟道，在所述独立电极和所述源极之间形成第二沟道，使对应所述第一沟道和所述第二沟道的所述刻蚀阻挡层暴露。
其中，所述第二栅极至少覆盖所述第一沟道以及所述第二沟道。
其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
其中，所述绝缘保护层包括氧化硅SiO或/和氮化硅SiN。
其中，当所述双栅极薄膜晶体管导通时，所述源极与所述漏极之间的有效沟道长度为所述第一沟道和所述第二沟道所对应的长度之和；当所述双栅极薄膜晶体管截止时，所述源极与所述漏极之间的有效沟道长度为所述第一沟道和所述第二沟道各自所对应的长度、第一沟道与所述第二沟道之间的距离之和。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种阵列基板，所述阵列基板包括上述任一项所述的双栅极薄膜晶体管。
本发明的有益效果是：区别于现有技术的情况，在源极和漏极之间增加一独立电极，使得双栅极薄膜晶体管在导通时源极和漏极之间的有效沟道长度小于截止时源极和漏极之间的有效沟道长度。由于沟道长度越长，双栅极薄膜晶体管的电流越小，上述方式使得双栅极薄膜晶体管的导通（开态）电流与截止（关态）电流的比值变大，从而解决现有技术中由于源极和漏极之间的有效沟道长度所引起的漏电问题，提高双栅极薄膜晶体管的电性能，增加其稳定性。
【附图说明】
图1是本发明双栅极薄膜晶体管的制作方法一实施例的流程示意图；
图2是本发明双栅极薄膜晶体管一实施例的剖面结构示意图；
图3是本发明双栅极薄膜晶体管另一实施例的剖面结构示意图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
参阅图1，图1是本发明双栅极薄膜晶体管的制作方法一实施例的流程示意图。本实施例的制造方法包括如下步骤：
S101：在第一基板上依次形成第一栅极、栅极绝缘层、半导体层以及刻蚀阻挡层。
具体地，先在第一基板上通过沉积的方式形成金属膜层，经过第一道光罩对金属膜层进行曝光，将金属膜层刻蚀成第一栅极。
其中，第一基板包括玻璃基板以及石英基板，在其他实施方式中还可以为其他基板，在此不做限定。
金属膜层包括铝Al、钼Mo、铜Cu以及银Ag中的至少一种，在其他实施方式中也可以为其他金属，在此也不做限定。
沉积工艺一般是指外来物质淀积于基底表面形成薄膜，又称为气相沉积。本实施方式是通过金属物质在第一基板的表面形成金属膜层。在其他实施方式中，也可以通过其他沉积方式来实现金属膜层，在此不作限定。
刻蚀工艺一般是指把薄膜上未被抗蚀剂掩蔽的部分薄膜层除去，从而在薄膜层上形成与抗蚀剂膜完全相同图形的工艺。刻蚀工艺一般包括干法刻蚀和湿法刻蚀，本实施方式中不作限定，只要能够在金属膜层上刻蚀出第一栅极即可。
在第一栅极形成后，在第一栅极的表面沉积栅极绝缘层。
其中，栅极绝缘层包括氮化硅SiNx，非晶氧化硅SiOx中的至少一种，在其他实施方式中，也可以为其他绝缘物质，在此不做限定。
在栅极绝缘层形成后，在栅极绝缘层的表面，且相对第一栅极的区域沉积半导体层（有源层）。其中，半导体层未完全覆盖栅极绝缘层，半导体层的截面积大于或等于第一栅极的截面积。
在半导体形成后，在半导体层以及暴露的栅极绝缘层的表面沉积刻蚀阻挡层。其中，在刻蚀阻挡层覆盖半导体层的区域开设有三个开口区域，使对应三个开口区域的半导体层暴露。此处对三个开口区域的尺寸不作限定，可根据实际需要进行设置。
第一开口区域、第二开口区域以及第三开口区域用于分别沉积漏极、独立电极以及源极。
S102：在对应暴露的所述半导体层上依次形成一漏极、一独立电极以及一源极。
在在第一基板上依次形成第一栅极、栅极绝缘层、半导体层以及刻蚀阻挡层后，在对应暴露的半导体层上依次形成一漏极、一独立电极以及一源极。即，在上述的三个开口区域依次分别形成一漏极、一独立电极以及一源极。漏极、独立电极以及源极可以部分覆盖刻蚀阻挡层。
其中，在半导体层上，漏极和独立电极之间形成第一沟道，在独立电极和源极之间形成第二沟道，使对应第一沟道和第二沟道的刻蚀阻挡层暴露。
漏极、独立电极以及源极的形成方法可以为：在对应暴露的半导体层和刻蚀阻挡层上通过沉积的方式形成金属膜层，经过光罩对金属膜层进行曝光，将金属膜层刻蚀成漏极、独立电极以及源极。
其中，独立电极用于在双栅极薄膜晶体管导通时，减小源极和漏极之间的有效沟道长度。即在双栅极薄膜晶体管导通，源极和漏极之间的有效沟道长度为第一沟道长度与第二沟道长度之和。在双栅极薄膜晶体管截止，源极和漏极之间的有效沟道长度为第一沟道长度、第二沟道长度、第一沟道与第二沟道之间的距离三者的总和。
由于源极、独立电极、漏极同时进行光刻，不需要增加光罩数量，能够简化制作流程，节省成本。
S103：在暴露的所述刻蚀阻挡层以及所述漏电极、所述源电极、所述独立电极的表面形成绝缘保护层。
在形成漏极、独立电极以及源极之后，在暴露的刻蚀阻挡层以及漏电极、源电极、独立电极的表面形成绝缘保护层。
具体可以为：在刻蚀阻挡层以及漏极、源极以及独立电极的表面溅镀氧化硅SiO或/和氮化硅SiN形成绝缘保护。
S104：在所述绝缘保护层上相对所述第一栅极的区域形成第二栅极。
在形成绝缘保护层后，在绝缘保护层上相对第一栅极的区域形成第二栅极。第一栅极与第二栅极通过过孔进行连接。
具体地，先在绝缘保护层上通过沉积的方式形成金属膜层，经过光罩对该金属膜层进行曝光，将该金属膜层刻蚀成第二栅极。
进一步地，第二栅极覆盖第一沟道以及第二沟道。即，第二栅极覆盖在绝缘保护层上相对半导体层的区域，至少能够覆盖源极与独立电极之间形成的第一沟道，以及独立电极与漏极之间形成的第二沟道。
进一步地，第二栅极被刻蚀掉第一区域，被刻蚀的第一区域相对于半导体层的截面积小于或等于独立电极覆盖在半导体层上的截面积，以使第二栅极能够完全覆盖第一沟道以及第二沟道。
具体为：先在绝缘保护层上通过沉积的方式形成金属膜层，经过光罩对该金属膜层进行曝光，将该金属膜层刻蚀成第二栅极，并且将该第二栅极的第一区域刻蚀掉，以使第二栅极被第一区域分隔成两部分。第二栅极被第一区域分隔成的两部分至少能够分别覆盖第一沟道、第二沟道。
其中，被刻蚀掉的第一区域使得第二栅极与独立电极相互无重叠区域，有效减少第二栅极与独立电极之间形成的寄生电容。
上述方案，区别于现有技术，在源极和漏极之间增加一独立电极，使得双栅极薄膜晶体管在导通时源极和漏极之间的有效沟道长度小于截止时源极和漏极之间的有效沟道长度。由于沟道长度越长，双栅极薄膜晶体管的电流越小，上述方式使得双栅极薄膜晶体管的导通（开态）电流与截止（关态）电流的比值变大，从而解决现有技术中由于源极和漏极之间的有效沟道长度所引起的漏电问题，提高双栅极薄膜晶体管的电性能，增加其稳定性。
参阅图2，图2是本发明双栅极薄膜晶体管一实施例的剖面结构示意图。
本实施例的双栅极薄膜晶体管包括：第一基板110、依次层叠设置于第一基板110上的第一金属层120、栅极绝缘层130、半导体层140、刻蚀阻挡层150、第二金属层160、绝缘保护层170以及第三金属层180。第一金属层120为第一栅极，第三金属层180为第二栅极，且第一栅极在内部通过过孔连接第二栅极。第二金属层160包括漏极161、独立电极162以及源极163。当然，在其他实施例中，也可以将161定义为源极，将163定义为漏极。
如图2所示，第一栅极120部分覆盖第一基板110。其中，第一基板110可以为玻璃基板或石英基板，在其他实施方式中还可以为其他基板，在此不做限定。
栅极绝缘层130完全覆盖第一栅极120以及第一基板110。半导体层140设置于栅极绝缘层130与第一栅极120重合的区域。半导体层140与栅极绝缘层130重合的区域大于或等于栅极绝缘层130与第一栅极120重合的区域。
刻蚀阻挡层150覆盖栅极绝缘层130以及半导体层140，且在刻蚀阻挡层150覆盖在半导体层140的区域开设有三个开口区域，使对应三个开口区域的半导体层140未被刻蚀阻挡层150覆盖。其中，三个开口区域被第二金属层160覆盖。
第二金属层160对应未被刻蚀阻挡层150覆盖的半导体层140，被依次分割为一漏极161、一独立电极162以及一源极163，在漏极160和独立电极162之间形成第一沟道，在独立电极162和源极163之间形成第二沟道，使对应第一沟道和第二沟道的刻蚀阻挡层暴露。
其中，第二金属层160在半导体层140的三个开口区域形成一漏极161、一独立电极162以及一源极163。在漏极160和独立电极162之间形成的第一沟道的长度为L1，在独立电极162和源极163之间形成的第二沟道的长度为L2，第一沟道和第二沟道之间的长度为L3（独立电极对应的截面长度为L3）。
第三金属层（第二栅极）180设置于绝缘保护层170与第一金属层（第一栅极）120重合的区域。第三金属层180的截面积可以小于第一金属层120的截面积。
进一步地，绝缘保护层170的材料可以包括氧化硅SiO或/和氮化硅SiN，此处不作限制。
进一步地，第三金属层（第二栅极）180至少覆盖第一沟道以及第二沟道。即，第三金属层（第二栅极）180至少能够完全覆盖第一沟道和第二沟道。
当双栅极薄膜晶体管导通时，源极163与漏极161通过半导体层140建立连接，源极163与漏极161之间的有效沟道长度为第一沟道和第二沟道所对应的长度之和。即，当双栅极薄膜晶体管导通时，由于独立电极162也导电，源极163与漏极161之间的有效沟道长度为L1和L2之和。
当双栅极薄膜晶体管截止时，源极163与漏极161断开连接，源极163与漏极161之间的有效沟道长度为第一沟道和第二沟道各自所对应的长度、第一沟道与第二沟道之间的距离三者的总和。即，当双栅极薄膜晶体管截止时，源极163与漏极161之间的有效沟道长度为L1、L2、L3三者的总和。
由于沟道长度越长，通过双栅极薄膜晶体管的电流越小，通过在源极和漏极之间增加一个独立电极使得双栅极薄膜晶体管的导通（开态）电流与截止（关态）电流的比值变大。
可以理解的是，第一沟道的长度L1、第二沟道的长度L2以及第一沟道与第二沟道之间的距离L3可根据实际需要进行设置，此处不作限制。
上述方案，区别于现有技术，在源极和漏极之间增加一独立电极，使得双栅极薄膜晶体管在导通时源极和漏极之间的有效沟道长度小于截止时源极和漏极之间的有效沟道长度。由于沟道长度越长，双栅极薄膜晶体管的电流越小，上述方式使得双栅极薄膜晶体管的导通（开态）电流与截止（关态）电流的比值变大，从而解决现有技术中由于源极和漏极之间的有效沟道长度所引起的漏电问题，提高双栅极薄膜晶体管的电性能，增加其稳定性。
请参阅图3，图3是本发明双栅极薄膜晶体管另一实施例的剖面结构示意图。本实施例与上一实施例的不同之处在于第三金属层（第二栅极）280。
本实施例的第三金属层（第二栅极）280被刻蚀掉第一区域，被刻蚀的第一区域相对于半导体层140的截面积小于或等于独立电极162覆盖在半导体层140上的截面积，以使第二栅极280能够完全覆盖第一沟道和第二沟道。
具体的，第三金属层（第二栅极）280被刻蚀掉第一区域，第一区域将第三金属层（第二栅极）280分隔成两部分。第二栅极280被第一区域分割形成的两部分至少能够分别覆盖第一沟道以及第二沟道。
其中，第一区域能够使得第二栅极280与独立电极162相互无重叠区域或较小的重叠区域，有效减少第二栅极280与独立电极162之间形成的寄生电容。
上述方案，区别于现有技术，在源极和漏极之间增加一独立电极，使得双栅极薄膜晶体管在导通时源极和漏极之间的有效沟道长度小于截止时源极和漏极之间的有效沟道长度。由于沟道长度越长，双栅极薄膜晶体管的电流越小，上述方式使得双栅极薄膜晶体管的导通（开态）电流与截止（关态）电流的比值变大，从而解决现有技术中由于源极和漏极之间的有效沟道长度所引起的漏电问题，提高双栅极薄膜晶体管的电性能，增加其稳定性。
并且，第二栅极的设置方式能够减少第二栅极280与独立电极162之间形成的寄生电容，进一步提高双栅极薄膜晶体管的性能。
进一步地，本发明还提供一种阵列基板（图未示），该阵列基板包括上述任一所述的双栅极薄膜晶体管。
进一步地，本发明还提供一种液晶显示装置（图未示），该液晶显示装置包括上基板、下基板以及夹持在上基板与下基板之间的液晶层。其中，下基板包括上述任一所述的双栅极薄膜晶体管。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种双栅极薄膜晶体管的制作方法，其中，所述方法包括：
    在第一基板上依次形成第一栅极、栅极绝缘层、半导体层以及刻蚀阻挡层；其中，在所述刻蚀阻挡层覆盖所述半导体层的区域开设有三个开口区域，使对应所述三个开口区域的半导体层暴露；
    在对应暴露的所述半导体层上依次形成一漏极、一独立电极以及一源极；其中，在所述漏极和所述独立电极之间形成第一沟道，在所述独立电极和所述源极之间形成第二沟道，使对应所述第一沟道和所述第二沟道的所述刻蚀阻挡层暴露；
    在暴露的所述刻蚀阻挡层以及所述漏电极、所述源电极、所述独立电极的表面形成绝缘保护层；以及
    在所述绝缘保护层上相对所述第一栅极的区域形成第二栅极。
  2. 根据权利要求1所述的方法，其中，所述第二栅极至少覆盖所述第一沟道以及所述第二沟道。
  3. 根据权利要求1所述的方法，其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
  4. 根据权利要求2所述的方法，其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
  5. 根据权利要求1所述的方法，其中，在暴露的所述刻蚀阻挡层以及所述漏电极、所述源电极、所述独立电极的表面形成绝缘保护层的步骤具体为：
    在所述刻蚀阻挡层以及所述漏极、所述源极以及所述独立电极的表面溅镀氧化硅SiO或/和氮化硅SiN形成所述绝缘保护。
  6. 一种双栅极薄膜晶体管，其中，所述双栅极薄膜晶体管包括：第一基板、依次层叠设置于所述第一基板上的第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、第二金属层、绝缘保护层以及第三金属层；所述第一金属层为第一栅极，所述第三金属层为第二栅极，且所述第一栅极连接所述第二栅极；
    其中，在所述刻蚀阻挡层覆盖在所述半导体层的区域开设有三个开口区域，使对应所述三个开口区域的半导体层未被所述刻蚀阻挡层覆盖；
    所述第二金属层对应未被所述刻蚀阻挡层覆盖的所述半导体层，被依次分割为一漏极、一独立电极以及一源极，在所述漏极和所述独立电极之间形成第一沟道，在所述独立电极和所述源极之间形成第二沟道，使对应所述第一沟道和所述第二沟道的所述刻蚀阻挡层暴露。
  7. 根据权利要求6所述的双栅极薄膜晶体管，其中，所述第二栅极至少覆盖所述第一沟道以及所述第二沟道。
  8. 根据权利要求6所述的双栅极薄膜晶体管，其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
  9. 根据权利要求7所述的双栅极薄膜晶体管，其中，所述第二栅极被刻蚀第一区域，所述被刻蚀的第一区域相对于所述半导体层的截面积小于或等于所述独立电极的截面积。
  10. 根据权利要求6所述的双栅极薄膜晶体管，其中，所述绝缘保护层包括氧化硅SiO或/和氮化硅SiN。
  11. 根据权利要求6所述的双栅极薄膜晶体管，其中，当所述双栅极薄膜晶体管导通时，所述源极与所述漏极之间的有效沟道长度为所述第一沟道和所述第二沟道所对应的长度之和；
    当所述双栅极薄膜晶体管截止时，所述源极与所述漏极之间的有效沟道长度为所述第一沟道和所述第二沟道各自所对应的长度、第一沟道与所述第二沟道之间的距离之和。
  12. 一种阵列基板，其中，所述阵列基板包括权利要求6所述的双栅极薄膜晶体管。
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