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WO2016078112A1 - 薄膜晶体管基板的制作方法及制造设备 - Google Patents

薄膜晶体管基板的制作方法及制造设备 Download PDF

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Publication number
WO2016078112A1
WO2016078112A1 PCT/CN2014/092504 CN2014092504W WO2016078112A1 WO 2016078112 A1 WO2016078112 A1 WO 2016078112A1 CN 2014092504 W CN2014092504 W CN 2014092504W WO 2016078112 A1 WO2016078112 A1 WO 2016078112A1
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Prior art keywords
layer
semiconductor
protective layer
forming
drain
Prior art date
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Ceased
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PCT/CN2014/092504
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English (en)
French (fr)
Inventor
吕晓文
李文辉
石龙强
苏智昱
曾志远
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to GB1706041.9A priority Critical patent/GB2546667B/en
Priority to DE112014007071.8T priority patent/DE112014007071T5/de
Priority to RU2017121359A priority patent/RU2669546C1/ru
Priority to JP2017525605A priority patent/JP6440228B2/ja
Priority to US14/407,865 priority patent/US9570482B2/en
Priority to KR1020177015608A priority patent/KR20170077245A/ko
Publication of WO2016078112A1 publication Critical patent/WO2016078112A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C30/00—Coating with metallic material characterised only by the composition of the metallic material, i.e. not characterised by the coating process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H10P72/04—

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a device for fabricating a thin film transistor substrate.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Display
  • organic electro-laser display organic electro-laser display
  • LCD liquid crystal displays require backlight illumination to display
  • OLEDs are self-illuminating.
  • OLED displays have the advantages of wide viewing angle, fast response, lighter weight, more power saving, etc., and will be the mainstream of next-generation display technology after LCD display technology.
  • TFT Thin Film
  • Transistor a thin film transistor
  • an oxide semiconductor TFT has a high mobility and an amorphous structure, which makes it compatible with current a-Si process processes, and thus is widely used in a large-sized display panel.
  • the structure commonly used for oxide semiconductor TFTs is an etch stop (ESL) structure.
  • ESL etch stop
  • the etch stop structure has the advantages of simple fabrication and high device stability, but requires a large number of masks in the manufacturing process, and the process is complicated.
  • step S101 in the process of fabricating an oxide semiconductor TFT having an etch-preventing structure, in step S101, a first metal layer 11 is deposited on the substrate 10, and the first reticle is used. A metal layer 11 is patterned to form the gate of the thin film transistor.
  • step S102 an insulating layer 12 is deposited on the gate, and the insulating layer 12 is patterned by a second mask to form a gate insulating layer of the thin film transistor.
  • step S103 the semiconductor layer 13 is deposited on the gate insulating layer, and the semiconductor layer 13 is patterned by a third mask to form a semiconductor channel of the thin film transistor.
  • step S104 a first protective layer 14 is deposited on the semiconductor via, and the first protective layer 14 is patterned using a fourth mask.
  • step S105 a second metal layer 15 is deposited on the semiconductor via, and the second metal layer 15 is patterned using a fifth mask to form a source and a drain.
  • step S106 a photomask is further required to form the second protective layer 16 and the pixel electrode layer 17, respectively. Therefore, in the process of forming the gate of the thin film transistor, the gate insulating layer, the semiconductor layer, the first protective layer, and the source and drain, at least five masks are required, and the number of masks is large, and the process is complicated, which is disadvantageous for cost reduction.
  • the technical problem to be solved by the present invention is to provide a method and a manufacturing apparatus for a thin film transistor substrate, which can reduce the number of masks and reduce the complexity of the process.
  • a technical solution adopted by the present invention is to provide a method for fabricating a thin film transistor substrate for an OLED display panel, comprising: sequentially depositing and patterning a first metal layer on a substrate And an insulating layer to respectively form a gate electrode and a gate insulating layer of the thin film transistor; a semiconductor layer and a first protective layer are sequentially deposited on the gate insulating layer, wherein the first protective layer is an etch barrier layer, and the material thereof is Silicon nitride; patterning the first protective layer to remove a portion of the first protective layer, and retain at least a first protective layer on a semiconductor layer of a semiconductor channel for forming the thin film transistor, wherein In a first protective layer covering a semiconductor layer for forming the semiconductor channel, a thickness of the first protective layer covering the semiconductor layer for forming a semiconductor channel in contact with the source and drain is smaller than covering other semiconductor layers The thickness of the first protective layer; the semiconductor layer is patterned by using the first protective layer after patterning to
  • the step of patterning the first protective layer comprises: patterning the first protective layer to remain in a space for forming a storage capacitor a first protective layer on the semiconductor layer of the first electrode, and a thickness of the first protective layer on the semiconductor layer of the first electrode for forming the storage capacitor is smaller than the first protective layer covering the other semiconductor layer a step of etching the first protective layer covering the semiconductor layer for forming the semiconductor channel, further comprising: removing the semiconductor layer on the first electrode for forming the storage capacitor a protective layer to expose the semiconductor layer for forming a first electrode of the storage capacitor; the first protective layer after the etching is used for forming the photomask and the drain
  • the step of metallizing the semiconductor layer of the contacted semiconductor channel further comprises: using the first protective layer after the etching as the mask pair to expose the first electrode for forming the storage capacitor Metalized conductor layer to form a first electrode of the storage capacitor.
  • the thickness of the first protective layer on the semiconductor layer for forming the first electrode of the storage capacitor and the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source and drain The thickness is the same and is one-half the thickness of the first protective layer covering the other semiconductor layers.
  • the step of depositing and patterning a second metal layer on the semiconductor channel to form a source and a drain of the thin film transistor includes: forming on a substrate on which the source and drain are formed a second protective layer; a via hole is disposed in the second protective layer above the drain; a transparent conductive layer as a second electrode of the storage capacitor is formed on the second protective layer, and the A transparent conductive layer is connected to the drain through the via hole.
  • another technical solution adopted by the present invention is to provide a method for fabricating a thin film transistor substrate, comprising: sequentially depositing and patterning a first metal layer and an insulating layer on a substrate to form a thin film transistor, respectively.
  • a gate and a gate insulating layer sequentially depositing a semiconductor layer and a first protective layer on the gate insulating layer; patterning the first protective layer to remove a portion of the first protective layer, and remaining at least a first protective layer on the semiconductor layer for forming the semiconductor channel of the thin film transistor; patterning the semiconductor layer with the first protective layer after patterning to remove the a semiconductor layer covered by the protective layer, further forming a semiconductor channel of the thin film transistor on the gate insulating layer; depositing and patterning a second metal layer on the semiconductor channel to form a source of the thin film transistor And a drain, the source and the drain being in contact with the semiconductor channel, respectively.
  • the step of patterning the first protective layer includes: covering a first protective layer covering a semiconductor layer for forming the semiconductor channel, and covering for forming contact with the source and the drain
  • the thickness of the first protective layer of the semiconductor layer of the semiconductor channel is smaller than the thickness of the first protective layer covering the other semiconductor layers; the first protective layer after the patterning is patterned by the photomask
  • the step of removing the semiconductor layer not covered by the first protective layer comprising: etching the first protective layer covering the semiconductor layer for forming the semiconductor channel to remove the cover a first protective layer of a semiconductor layer forming a semiconductor channel in contact with the source and the drain, thereby exposing a semiconductor layer for forming a semiconductor channel in contact with the source and the drain; using the first after etching
  • the protective layer is a mask for metallizing the exposed semiconductor layer for forming a semiconductor channel in contact with the source and the drain, and further, the gate insulating layer Forming the thin film transistor semiconductor channel.
  • the step of patterning the first protective layer comprises: patterning the first protective layer to remain in a space for forming a storage capacitor a first protective layer on the semiconductor layer of the first electrode, and a thickness of the first protective layer on the semiconductor layer of the first electrode for forming the storage capacitor is smaller than the first protective layer covering the other semiconductor layer a step of etching the first protective layer covering the semiconductor layer for forming the semiconductor channel, further comprising: removing the semiconductor layer on the first electrode for forming the storage capacitor a protective layer to expose the semiconductor layer for forming a first electrode of the storage capacitor; the first protective layer after the etching is used for forming the photomask and the drain
  • the step of metallizing the semiconductor layer of the contacted semiconductor channel further comprises: using the first protective layer after the etching as the mask pair to expose the first electrode for forming the storage capacitor Metalized conductor layer to form a first electrode of the storage capacitor.
  • the thickness of the first protective layer on the semiconductor layer for forming the first electrode of the storage capacitor and the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source and drain The thickness is the same and is one-half the thickness of the first protective layer covering the other semiconductor layers.
  • the step of depositing and patterning a second metal layer on the semiconductor channel to form a source and a drain of the thin film transistor includes: forming on a substrate on which the source and drain are formed a second protective layer; a via hole is disposed in the second protective layer above the drain; a transparent conductive layer as a second electrode of the storage capacitor is formed on the second protective layer, and the A transparent conductive layer is connected to the drain through the via hole.
  • a manufacturing apparatus of a thin film transistor substrate comprising: a coating mechanism; and a first mask for coating the substrate on the coating mechanism After the first metal layer, the first metal layer is patterned to form a gate of the thin film transistor; and a second photomask is used after the coating mechanism applies an insulating layer on the gate The insulating layer is patterned to form a gate insulating layer of the thin film transistor; and a third photomask is used for sequentially coating a semiconductor layer and a first protection on the gate insulating layer on the coating mechanism After the layer, the first protective layer is patterned to remove a portion of the first protective layer, and at least the first protective layer on the semiconductor layer for forming the semiconductor channel of the thin film transistor is retained to utilize retention The first protective layer is patterned by the photomask to remove the semiconductor layer not covered by the first protective layer, thereby forming a semiconductor pass of the thin film transistor on the gate insulating layer.
  • the manufacturing apparatus further includes: an etching mechanism for forming the cover for forming The first protective layer of the semiconductor layer of the semiconductor channel is etched to remove the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source and drain, thereby exposing for forming and a semiconductor layer of the semiconductor channel in contact with the source and the drain; a metallization mechanism for using the first protective layer after the etching as the photomask pair to expose the semiconductor for contacting the source and the drain
  • the semiconductor layer of the channel is metallized to form a semiconductor channel of the thin film transistor on the gate insulating layer.
  • the material of the semiconductor layer is indium gallium zinc oxide;
  • the third photomask is further configured to pattern the first protective layer to remain on the semiconductor layer of the first electrode for forming the storage capacitor a first protective layer, and a thickness of the first protective layer on the semiconductor layer of the first electrode for forming the storage capacitor is smaller than a thickness of the first protective layer covering the other semiconductor layers;
  • the etching mechanism further Etching the first protective layer on the semiconductor layer of the first electrode for forming a storage capacitor to remove the first protective layer on the semiconductor layer of the first electrode for forming a storage capacitor And exposing the semiconductor layer for forming the first electrode of the storage capacitor;
  • the metallization mechanism is further configured to utilize the first protective layer after the etching as the photomask pair to expose the first one for forming a storage capacitor
  • the semiconductor layer of the electrode is metallized to form a first electrode of the storage capacitor.
  • the thickness of the first protective layer on the semiconductor layer for forming the first electrode of the storage capacitor and the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source and drain The thickness is the same and is one-half the thickness of the first protective layer covering the other semiconductor layers.
  • the coating mechanism is further configured to apply a second protective layer on the substrate forming the source and the drain; the manufacturing apparatus further includes a fifth mask for performing the second protective layer Patterning to form via holes in the second protective layer over the drain; the coating mechanism is further configured to coat the second protective layer as a second electrode of the storage capacitor a transparent conductive layer, and the transparent conductive layer is connected to the drain through the via hole.
  • the beneficial effects of the present invention are different from the prior art, in the method for fabricating the thin film transistor substrate of the present invention, after forming the gate electrode and the gate insulating layer of the thin film transistor, sequentially depositing the semiconductor layer and the first protective layer, After patterning the first protective layer, the semiconductor layer is patterned by using the first protective layer after patterning to form a semiconductor channel of the thin film transistor, thereby eliminating the need to add another semiconductor channel mask to the semiconductor layer Exposure can reduce the number of masks, help reduce costs, and reduce alignment errors and capacitive coupling.
  • FIG. 1 is a schematic view showing a method of fabricating a thin film transistor substrate in the prior art
  • FIG. 2 is a flow chart showing an embodiment of a method for fabricating a thin film transistor substrate of the present invention
  • FIG. 3 is a cross-sectional view showing an embodiment of a method of fabricating a thin film transistor substrate of the present invention
  • FIG. 4 is a cross-sectional view showing another embodiment of a method of fabricating a thin film transistor substrate of the present invention.
  • Figure 5 is a cross-sectional view showing still another embodiment of a method of fabricating a thin film transistor substrate of the present invention.
  • Figure 6 is a cross-sectional view showing still another embodiment of a method of fabricating a thin film transistor substrate of the present invention.
  • FIG. 7 is a schematic structural view of an embodiment of a manufacturing apparatus of a thin film transistor substrate of the present invention.
  • FIG. 8 is a schematic structural view of another embodiment of a manufacturing apparatus of a thin film transistor substrate of the present invention.
  • Fig. 9 is a view showing the configuration of still another embodiment of the apparatus for manufacturing a thin film transistor substrate of the present invention.
  • a thin film transistor substrate is a thin film transistor substrate applied to an OLED display panel. Since the OLED is a current-driven drive, each pixel requires two thin film transistors to be driven, one thin film transistor acts as a switch for switching on and off, and the other thin film transistor serves as a provider of driving current for pixel illumination to control The current size of the OLED. Therefore, in this embodiment, each pixel on the thin film transistor substrate corresponds to two thin film transistors, and the manufacturing process includes the following steps:
  • Step S201 sequentially depositing and patterning the first metal layer and the insulating layer on the substrate to form a gate electrode and a gate insulating layer of the thin film transistor, respectively.
  • FIG. 3 is a schematic diagram of a method of fabricating a thin film transistor substrate of the present invention.
  • the step is a first mask process
  • a first metal layer is first deposited on the substrate 30, and the first metal layer is exposed by using a photomask having a gate pattern to respectively Gates 31a, 31b of two thin film transistors are formed, wherein the gate 31a is the gate of the thin film transistor Q1 for switching, and the gate 31b is the gate of the thin film transistor Q2 for controlling the OLED current.
  • the first metal layer can be a copper metal layer.
  • Step S302 is a second mask process, depositing an insulating layer on the gate electrodes 31a, 31b, and exposing the insulating layer by using a photomask having a gate insulating layer pattern to form a gate insulating layer of the thin film transistors Q1, Q2. 32, and a via hole 32a is formed on the gate insulating layer 32 above the gate electrode 31a.
  • the gate insulating layer 32 covers the gate electrodes 31a, 31b.
  • Step S202 sequentially depositing a semiconductor layer and a first protective layer on the gate insulating layer.
  • the semiconductor layer 33 and the first protective layer 34 are sequentially deposited on the gate insulating layer 32.
  • the semiconductor layer 33 covers the gate insulating layer 32, and the first protective layer 34 covers the semiconductor layer 33.
  • the semiconductor layer 33 is used to form an active layer of the thin film transistors Q1 and Q2, that is, a semiconductor channel.
  • the first protective layer 34 is an etch barrier layer (ES, Etch-Stopper), and specifically may be a silicon nitride material layer. Other material layers such as silica may also be used.
  • Step S203 patterning the first protective layer to remove a portion of the first protective layer and retain at least a first protective layer on the semiconductor layer of the semiconductor channel for forming the thin film transistor.
  • the step is a third mask process.
  • the first protective layer 34 is exposed by using a third mask to remove part of the first protective layer 34, and is reserved for use.
  • the other first protective layers 34 are removed except for the first protective layers 34a, 34b on the semiconductor layers of the semiconductor vias for forming the thin film transistors Q1, Q2.
  • Step S204 patterning the semiconductor layer by using the patterned first protective layer as a photomask to remove the semiconductor layer not covered by the first protective layer, thereby forming a semiconductor channel of the thin film transistor on the gate insulating layer.
  • step S305 shown in FIG. 3 corresponds to the fourth mask process, but in this step, no additional mask is required to expose the semiconductor layer 33.
  • step S303 after exposing the first protective layer 34, the first protective layers 34a, 34b on the semiconductor layer for forming the semiconductor vias are left on the substrate, and the semiconductor layer 33 is used to form the semiconductor vias. That is, it is only necessary to retain a semiconductor layer for forming a semiconductor channel on the substrate.
  • the semiconductor layer 33 is exposed by using the remaining first protective layers 34a, 34b as a self-aligning mask to remove the semiconductor layer 33 not covered by the first protective layer 34, while retaining the
  • the semiconductor layers 33 covered by the first protective layers 34a, 34b form semiconductor channels 33a, 33b of the two thin film transistors Q1, Q2, respectively.
  • the first protective layer 34a, 34b is an etch barrier layer, for example, a silicon nitride layer, which forms a protective effect on the semiconductor channels 33a, 33b, is beneficial to prevent corrosion and dishing of the semiconductor channels 33a, 33b, and can improve the breakdown voltage. And device reliability.
  • Step S205 depositing and patterning a second metal layer on the semiconductor channel to form a source and a drain of the thin film transistor, and the source and the drain are respectively in contact with the semiconductor channel.
  • the second metal layer is exposed by a photomask having source and drain patterns to form a source 35b and a drain 35a of the thin film transistor Q1, and a source forming the thin film transistor Q2.
  • Extreme 35b' and 35a' are in contact with the semiconductor channel 33a of the corresponding thin film transistor Q1, and the sources 35b' and 35a' are in contact with the semiconductor channel 33b of the corresponding thin film transistor Q2.
  • the drain 35a' of the thin film transistor Q2 functioning as a switch is connected to the gate 31 of the thin film transistor Q1 for controlling the OLED through the via hole 32a.
  • the source and drain of the two thin film transistors can be electrically connected or electrically insulated by the action of the semiconductor channels 33a, 33b, respectively.
  • the prior art in the process of forming a thin film transistor, a photomask is first used to form a semiconductor channel, then an etch stop layer is deposited on the semiconductor channel, and another reticle is used to expose the etch stop layer, so the prior art A total of five masks are required in the process of forming the gate electrode, the gate insulating layer, the semiconductor channel, the etch stop layer, and the source and drain electrodes, and the number of masks required is large.
  • the semiconductor layer 33 is exposed as a self-aligned photomask by using the patterned first protective layers 34a, 34b when forming the semiconductor vias to form the semiconductor vias 33a, 33b. Therefore, it is not necessary to expose the semiconductor layer by a separate mask, and the mask of the semiconductor layer can be reduced, so that the number of masks can be reduced, the cost can be reduced, and the mask alignment error and capacitive coupling can be reduced.
  • the source electrodes 35b, 35b' and the drain electrodes 35a, 35a' are in contact with the side faces of the semiconductor vias 33a, 33b.
  • a half-tone is used in another embodiment of the method for fabricating a thin film transistor substrate of the present invention.
  • a mask (halftone mask) technique patterns the first protective layer 34 to increase the contact area between the source drain and the semiconductor channel. Referring to FIG. 4, the same steps can be referred to the above embodiment, and are not described herein.
  • the source 35b, 35b' and the drains 35a, 35a' are adjacent to the semiconductor channels 33a, 33b.
  • the upper surfaces of the first protective layers 34a, 34b are in contact to increase the contact area.
  • the first protective layer 34 is exposed using a halftone mask as a third mask such that the remaining first protective layers 34a, 34b are located on the semiconductor layer 33 for forming the semiconductor vias.
  • the thickness of the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source 35b, 35b' and the drains 35a, 35a' is smaller than the thickness of the first protective layer covering the other semiconductor layers.
  • the first protective layer 34 of the intermediate portion is not exposed at all.
  • the thickness remains the thickest, and the first protective layer 34 at both ends is exposed to some extent to remove a portion of the first protective layer to retain a first protective layer having a certain thickness on the semiconductor layer 33.
  • the first protective layer at both ends is a first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source 35b, 35b' and the drains 35a, 35a', and the position on the semiconductor layer 33 is a position where the source and drain are in contact with the upper surface of the semiconductor channel
  • step S405 the semiconductor layer 33 is exposed as a mask by using the patterned first protective layers 34a, 34b to remove the semiconductor layer not covered by the first protective layers 34a, 34b, while retaining the first protection.
  • the semiconductor layers covered by the layers 34a, 34b, the remaining semiconductor layers form the semiconductor vias 33a, 34b.
  • step S406 the first protective layers 34a, 34b covering the semiconductor layer 33 for forming the semiconductor vias are etched to remove the semiconductors for forming contacts with the source electrodes 35b, 35b' and the drains 35a, 35a'.
  • the first protective layer of the semiconductor layer of the channel in turn, exposes a semiconductor layer for forming a semiconductor channel in contact with the source 35b, 35b' and the drain 35a, 35a'.
  • the thickness of the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source 35b, 35b' and the drains 35a, 35a' is smaller than the thickness of the intermediate first protective layer, in the pair of semiconductor vias 33a.
  • the first protective layer having a smaller thickness at both ends can be completely removed by controlling the etching conditions, thereby exposing the semiconductor channels at both ends, and the first protective layer having a thicker intermediate thickness. Only a portion is removed, the amount removed is substantially the same as the amount of the first protective layer having a smaller thickness, so that the intermediate first protective layer can still remain partially on the semiconductor vias 33a, 33b to protect the semiconductor vias 33a, 33b. .
  • a second metal layer is deposited and patterned on the semiconductor vias 33a, 33b to form source 35b, 35b' and drains 35a, 35a'.
  • the first protective layer 34a is located between the source 35b and the drain 35a, and the source 35b and the drain 35a are both in contact with the upper surface of the semiconductor via 33a adjacent to the first protective layer 34a;
  • the first protective layer 34b is located between the source 35b' and the drain 35a', and the source 35b' and the drain 35a' are both in contact with the upper surface of the semiconductor via 33b adjacent to the first protective layer 34b.
  • the contact area can be increased, which is advantageous for improving the reliability of the device.
  • the semiconductor layer is an amorphous IGZO (indium gallium zinc oxide) material layer, whereby carrier mobility can be improved, and the charge and discharge rate of the pixel electrode can be greatly improved.
  • the semiconductor layer may also be an amorphous silicon (a-Si) material layer.
  • step S507 shown in FIG. 5 unlike the embodiment shown in FIG. 4, a metallization process is added, that is, step S507 shown in FIG.
  • step S506 after the first protective layer 34a, 34b is etched to remove the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source 35b, 35b' and the drain 35a, 35a', Step S507, using the first protective layers 34a, 34b after etching to metallize the exposed semiconductor layer for forming the semiconductor channel in contact with the source 35b, 35b' and the drains 35a, 35a', thereby forming Semiconductor channels 33a, 33b.
  • a second metal layer is deposited and patterned to form source and drain. Wherein, the source and the drain are in contact with the semiconductor layer after metallization.
  • the impedance at the contact of the semiconductor via and the source 35b, 35b' and the drains 35a, 35a' can be reduced, thereby further improving the performance of the device.
  • the first protective layer 34a, 34b after etching is used to metallize the semiconductor layer by using a self-aligning mask, without adding an additional mask for metallization, and adding a mask separately. Compared with the metallization scheme, the number of masks can be reduced, which is advantageous in reducing manufacturing costs.
  • a storage capacitor is usually provided to maintain the potential so that the display panel can be normally displayed.
  • the insulating layer is usually sandwiched by a metal electrode, but the metal is an opaque material, which causes a decrease in panel aperture ratio.
  • a transparent semiconductor IGZO is used to form a semiconductor layer and an electrode of a storage capacitor to increase the aperture ratio.
  • step S601 is to form the gate electrodes 31a, 31b
  • step S602 is to form the gate insulating layer 32
  • step S603 is to sequentially deposit the semiconductor layer 33 and the first protective layer 34.
  • the first protective layer 34 is patterned. Specifically, the first protective layer 34 is exposed by a halftone mask to remove a portion of the first protective layer, and remains in addition to the first protective layer remaining on the semiconductor layer for forming the semiconductor channel.
  • the semiconductor layer for forming the protective semiconductor channel is a semiconductor layer located in a semiconductor layer for forming a semiconductor channel except for a semiconductor layer for forming a semiconductor channel in contact with the source and drain.
  • the pattern of the first protective layer after exposure includes the stepped first protective layers 34a, 34b on the semiconductor layer 33 for forming the semiconductor vias, and is located for formation.
  • the first protective layer 34c on the semiconductor layer 33 of the first electrode of the storage capacitor is stored.
  • the first protective layer having a smaller thickness is a first protective layer covering the semiconductor layer for forming a semiconductor channel in contact with the source drain.
  • the partially exposed first protective layer is half-exposure to remove the first protective layer of half thickness, so that the cover is used to form contact with the source drain.
  • the thickness of the first protective layer of the semiconductor layer and the thickness of the first protective layer covering the semiconductor layer of the first electrode for forming the storage capacitor are half of the thickness of the first protective layer which is not exposed at all, that is, the thickness The thickness of the first protective layer is half of the original thickness.
  • the thickness of the first protective layer covering the semiconductor layer for forming the contact with the source drain and the thickness of the first protective layer covering the semiconductor layer of the first electrode for forming the storage capacitor are also The thickness may not be equal, and the thickness may not be limited to half of the original thickness, and may be set according to actual needs as long as it is smaller than the thickness of the first protective layer which is not exposed at all and can ensure complete shielding of the semiconductor layer.
  • step S605 the semiconductor layer 33 is exposed by using the first protective layers 34a, 34b, and 34c after exposure as a mask, thereby removing the semiconductor layer not covered by the first protective layers 34a, 34b, and 34c, and retaining the A semiconductor layer covered by a protective layer 34a, 34b, 34c for forming a first electrode of the semiconductor via and the storage capacitor.
  • the first protective layer 34a, 34b, 34c is etched to remove the first protective layer 34a, 34b covering the semiconductor layer for forming the semiconductor channel in contact with the source drain and the cap is used to form the storage capacitor.
  • the first protective layer 34c of the semiconductor layer of the first electrode is exposed such that a semiconductor layer for forming a semiconductor channel in contact with the source drain and a semiconductor layer for forming a first electrode of the storage capacitor are exposed.
  • the first protective layer having a smaller thickness is etched by controlling the etching conditions. After being dropped, the first protective layer 34a, 34b covering the semiconductor layer for forming the protective semiconductor via can still remain partially on the semiconductor via to protect the semiconductor via.
  • the exposed first semiconductor layers 34a, 34b are used as a mask to metallize the exposed semiconductor layer, thereby forming the semiconductor channel 33a of the thin film transistor Q1, the semiconductor channel 33b of the thin film transistor Q2, and the storage capacitor.
  • An electrode 33c the semiconductor layer can be metallized by H diffusion, ion implantation, or plasma plasma treatment.
  • step S608 a second metal layer is deposited and patterned on the semiconductor vias 33a, 33b to form the source 35b and the drain 35a of the thin film transistor Q1, the source 35b' of the thin film transistor Q2, and the drain 35a'.
  • step S608 formation is performed on the substrate on which the source electrodes 35b, 35b' and the drain electrodes 35a, 35a' are formed.
  • the second protective layer 36 is patterned by the photomask to form via holes 36a in the second protective layer 36 on the drain 35a of the thin film transistor Q2.
  • the second protective layer is an insulating layer or a passivation layer, and can be made of a silicon dioxide material.
  • the transparent conductive layer 37 serves as a second electrode of the storage capacitor, and a storage capacitor is formed by interposing the second protective layer 36 with the first electrode 33c.
  • the mask of the semiconductor layer 33 can be reduced, and the alignment can be reduced.
  • the error and capacitance are coupled, and the first protective layer 34a, 34b after etching is used for metallizing the mask, which can further reduce one metallized mask, which is beneficial to reduce cost.
  • the impedance at the source-drain and semiconductor channel contact can be reduced, which is advantageous for improving electron transport.
  • the storage capacitor is formed using a transparent IGZO semiconductor layer and a transparent conductive layer, and is advantageous in improving the aperture ratio as compared with a storage capacitor formed using a metal that does not transmit light.
  • the thin film transistor substrate may also be an array substrate for a liquid crystal display panel, which is different from the above-described embodiment of the thin film transistor substrate for an OLED in the substrate.
  • the number of the thin film transistors is one, that is, the thin film transistor Q1 for switching.
  • the transparent conductive layer for forming the pixel electrode is connected to the drain of the thin film transistor Q1, and the specific fabrication process is similar to the above embodiments. , I will not go into details here.
  • the present invention also provides an embodiment of a thin film transistor substrate which is produced by using the method of fabricating the thin film transistor substrate according to any of the above embodiments.
  • the thin film transistor substrate includes a storage capacitor, the first electrode of the storage capacitor is made of indium gallium zinc oxide, and the second electrode is formed of a transparent conductive layer as a pixel electrode.
  • an embodiment of a device for fabricating a thin film transistor substrate of the present invention includes a coating mechanism 70, a first mask 71, a second mask 72, a third mask 73, and a fourth mask 74.
  • the coating mechanism 70 is used to apply a first metal layer, an insulating layer, a semiconductor layer, a first protective layer, and a second metal layer.
  • the first mask 71 is used to pattern the first metal layer after the coating mechanism 70 coats the first metal layer on the substrate to form a gate of the thin film transistor.
  • the second mask 72 is used to pattern the insulating layer after the coating mechanism coats the insulating layer on the gate to form a gate insulating layer of the thin film transistor.
  • the third mask 73 is configured to pattern the first protective layer to remove a portion of the first protective layer after the coating mechanism sequentially applies the semiconductor layer and the first protective layer on the gate insulating layer, and at least remains for Forming a first protective layer on the semiconductor layer of the semiconductor channel of the thin film transistor to pattern the semiconductor layer with the remaining first protective layer as a photomask to remove the semiconductor layer not covered by the first protective layer, and further A semiconductor channel of the thin film transistor is formed on the very insulating layer.
  • the first protective layer is an etch barrier layer (ES).
  • the fourth mask 74 is configured to pattern the second metal layer after the coating mechanism applies the second metal layer on the semiconductor channel to form a source and a drain of the thin film transistor, and the source and the drain respectively Semiconductor channel contact.
  • the subsequent first protective layer is a self-aligned reticle to pattern the semiconductor layer, thereby completing the above process with only four masks, which can reduce the number of masks and reduce alignment errors and capacitive coupling.
  • the manufacturing apparatus further includes an etching mechanism 85 and a metallization mechanism 86.
  • the third mask 83 is for patterning the first protective layer and leaving the remaining first protective layer on the semiconductor layer for forming the semiconductor via, for covering the source and drain contacts
  • the thickness of the first protective layer of the semiconductor layer of the semiconductor channel is smaller than the thickness of the first protective layer covering the other semiconductor layers.
  • the etching mechanism 85 is for covering the first protective layer of the semiconductor layer for forming the semiconductor channel Etching is performed to remove the first protective layer covering the semiconductor layer for forming the semiconductor channel in contact with the source and drain, thereby exposing the semiconductor layer for forming the semiconductor channel in contact with the source and drain.
  • the metallization mechanism 86 is configured to metallize the exposed semiconductor layer for forming the semiconductor channel in contact with the source and the drain by using the first protective layer after the etching, thereby forming a thin film transistor on the gate insulating layer. Semiconductor channel.
  • the coating mechanism 80 coats a second metal layer on the formed semiconductor channel, and a fourth mask 84 is used to pattern the second metal layer to form a source and a drain. .
  • the source and the drain are in contact with the semiconductor layer after metallization.
  • a storage capacitor is further formed on the thin film transistor substrate.
  • the material of the semiconductor layer is indium gallium zinc oxide, and the storage capacitor is formed by the semiconductor layer, thereby improving Opening ratio.
  • the first protective layer is patterned by the third photomask 93, in addition to the first protective layer remaining on the semiconductor layer for forming the semiconductor via.
  • a first protective layer on the semiconductor layer of the first electrode for forming the storage capacitor is also retained.
  • the first protective layer covering the semiconductor layer that needs to be completely removed in the subsequent process is full exposure, and covers the first protective layer of the semiconductor layer for forming the semiconductor channel in contact with the source and drain in the subsequent process and
  • the first protective layer on the semiconductor layer of the first electrode for forming the storage capacitor is partially exposed, and the first protective layer covering the semiconductor layer for forming the protective semiconductor via in the subsequent process is not exposed at all.
  • the semiconductor layer for forming the protective semiconductor channel is a semiconductor layer located in a semiconductor layer for forming a semiconductor channel except for a semiconductor layer for forming a semiconductor channel in contact with the source and drain.
  • the fully exposed first protective layer is completely removed to expose the corresponding semiconductor layer, while the first unprotected first protective layer retains the original thickness, and the partially exposed first protective layer is removed.
  • the first protective layer having a certain thickness is retained, and the thickness of the first protective layer having a certain thickness is smaller than the thickness of the first protective layer not exposed at all.
  • the pattern of the first protective layer after exposure includes a stepped first protective layer on the semiconductor layer for forming the semiconductor via, and a first protective layer on the semiconductor layer of the first electrode for forming the storage capacitor .
  • the first protective layer having a smaller thickness is a first protective layer covering the semiconductor layer for forming a semiconductor channel in contact with the source drain.
  • the partially exposed first protective layer is half-exposure to remove the first protective layer of half thickness, so that the cover is used to form contact with the source drain.
  • the thickness of the first protective layer of the semiconductor layer and the thickness of the first protective layer covering the semiconductor layer of the first electrode for forming the storage capacitor are half of the thickness of the first protective layer which is not exposed at all, that is, the thickness The thickness of the first protective layer is half of the original thickness.
  • the thickness of the first protective layer covering the semiconductor layer for forming the contact with the source drain and the thickness of the first protective layer covering the semiconductor layer of the first electrode for forming the storage capacitor are also The thickness may not be equal, and the thickness may not be limited to half of the original thickness, and may be set according to actual needs as long as it is smaller than the thickness of the first protective layer which is not exposed at all and can ensure complete shielding of the semiconductor layer.
  • the partially exposed first protective layer is half-exposure to remove the first protective layer of half thickness, so that the cover is used to form contact with the source drain.
  • the thickness of the first protective layer of the semiconductor layer and the thickness of the first protective layer covering the semiconductor layer of the first electrode for forming the storage capacitor are half of the thickness of the first protective layer which is not exposed at all, that is, the thickness of the first protective layer
  • the thickness of the first protective layer is half of the original thickness.
  • the thickness of the first protective layer covering the semiconductor layer for forming the contact with the source drain and the thickness of the first protective layer covering the semiconductor layer of the first electrode for forming the storage capacitor are also The thickness may not be equal, and the thickness may not be limited to half of the original thickness, and may be set according to actual needs as long as it is smaller than the thickness of the first protective layer which is not exposed at all and can ensure complete shielding of the semiconductor layer.
  • the etching mechanism 95 is used to cover the first protective layer for forming the semiconductor layer in contact with the source drain and the cover for forming the storage capacitor.
  • the semiconductor layer of the first electrode is etched to remove a first protective layer covering the semiconductor layer for forming contact with the source drain and a semiconductor layer covering the first electrode for forming the storage capacitor, thereby exposing for forming and A semiconductor layer in contact with the source drain and a semiconductor layer for forming a first electrode of the storage capacitor.
  • the metallization mechanism 96 is for metallizing the exposed semiconductor layer with a first protective layer after etching to form a semiconductor channel of the thin film transistor and a first electrode of the storage capacitor.
  • the coating mechanism 90 After forming the semiconductor channel of the thin film transistor and the first electrode of the storage capacitor, the coating mechanism 90 applies a second metal layer on the semiconductor channel, and the fourth mask 94 is used to pattern the second metal layer to form a thin film transistor. Source and drain.
  • the manufacturing apparatus further includes a fifth photomask 97.
  • the coating mechanism 90 is configured to apply a second protective layer on the source and the drain, and the second protective layer may be an insulating layer or a passivation layer, and the second oxide may be used. Made of silicon material.
  • the fifth photomask 97 is used to pattern the second protective layer to form via holes in the second protective layer on the drain of the thin film transistor.
  • the coating mechanism 90 is further configured to coat a transparent conductive layer as a second electrode of the storage capacitor on the second protective layer, and connect the transparent conductive layer to the drain through the via hole. Wherein, the transparent conductive layer also serves as a pixel electrode to achieve display.
  • the opening can be improved compared with the conventional technique of forming a storage capacitor using an opaque metal. rate.
  • the first protective layer after the patterning is used to expose the semiconductor layer by the self-aligning mask, the mask of the semiconductor layer can be reduced, and the alignment error and the capacitive coupling are reduced, and the first after the etching is utilized.
  • the protective layer is a metallization of the semiconductor layer by the self-aligning mask, which can reduce the mask required for metallization and further reduce the number of masks.

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Abstract

一种薄膜晶体管基板的制作方法及制造设备，所述方法中，在形成薄膜晶体管的栅极（31a，31b）和栅极绝缘层（32）之后，依次沉积半导体层（33）和第一保护层（34），在对第一保护层（34）图案化之后，利用图案化之后的第一保护层（34）为光罩对半导体层（33）进行图案化，以形成薄膜晶体管的半导体通道。通过上述方式，能够减少光罩数目，有利于降低成本。

Description

薄膜晶体管基板的制作方法及制造设备
【技术领域】
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管基板的制作方法及制造设备。
【背景技术】
目前，显示器主要分为LCD（Liquid Crystal Display，液晶显示）液晶显示器和OLED（Organic Light Emitting Display，有机电激光显示）显示器，两种主要的区别在于LCD液晶显示器需要背光源照射才能够显示，而OLED则是自发光。与LCD液晶显示器相比，OLED显示器具有宽视角、响应快、更轻薄、更省电等优点，将是继LCD显示技术之后的下一代显示技术的主流。
无论是LCD液晶显示器还是OLED显示器，通常都是采用TFT（Thin Film Transistor，薄膜晶体管）进行驱动，而氧化物半导体TFT具有较高的迁移率，同时是非晶结构，使得其与目前a-Si制程工艺兼容性高，因此在大尺寸显示面板中得到广泛应用。目前，氧化物半导体TFT常使用的结构为蚀刻阻止（ESL）结构。蚀刻阻止结构具有制作简单、器件稳定性较高的优点，但是在制造过程中需要较多的光罩数，制程复杂。
以OLED显示器为例，如图1所示，在制作蚀刻阻止结构的氧化物半导体TFT的过程中，步骤S101中，在基板10上沉积第一金属层11，并利用第一道光罩对第一金属层11进行图案化，以形成薄膜晶体管的栅极。步骤S102中，在栅极上沉积绝缘层12，并利用第二道光罩对绝缘层12进行图案化以形成薄膜晶体管的栅极绝缘层。步骤S103中，在栅极绝缘层上沉积半导体层13，并利用第三道光罩对半导体层13进行图案化以形成薄膜晶体管的半导体通道。步骤S104中，在半导体通道上沉积第一保护层14，并利用第四道光罩对第一保护层14进行图案化。步骤S105中，在半导体通道上沉积第二金属层15，并利用第五道光罩对第二金属层15进行图案化以形成源极和漏极。此外，步骤S106中，还分别需要一道光罩形成第二保护层16和像素电极层17。因此，在形成薄膜晶体管的栅极、栅极绝缘层、半导体层、第一保护层以及源漏极的过程中，至少需要五道光罩，光罩数较多，制程复杂，不利于成本降低。
【发明内容】
本发明主要解决的技术问题是提供一种薄膜晶体管基板的制作方法及制造设备，能够减少光罩数目，降低工艺的复杂性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管基板的制作方法，所述薄膜晶体管基板用于OLED显示面板，包括：在基板上依次沉积并图案化第一金属层和绝缘层，以分别形成薄膜晶体管的栅极和栅极绝缘层；在所述栅极绝缘层上依次沉积半导体层和第一保护层，所述第一保护层为蚀刻阻挡层，其材料为氮化硅；对所述第一保护层进行图案化以除去部分所述第一保护层，并至少保留位于用于形成所述薄膜晶体管的半导体通道的半导体层上的第一保护层，其中，使覆盖用于形成所述半导体通道的半导体层的第一保护层中，覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度；利用图案化之后的所述第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层；对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻，以除去所述覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与所述源极、漏极接触的半导体通道的半导体层；利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道；在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极，所述源极和所述漏极分别与所述半导体通道接触。
其中，所述半导体层的材料为氧化铟镓锌；所述对所述第一保护层进行图案化的步骤包括：对所述第一保护层进行图案化，以保留位于用于形成存储电容的第一电极的半导体层上的第一保护层，且所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度小于所述覆盖其他半导体层的第一保护层的厚度；所述对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻的步骤，还包括：除去所述位于用于形成存储电容的第一电极的半导体层上的第一保护层，以暴露所述用于形成存储电容的第一电极的半导体层；所述利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化的步骤，还包括：利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成存储电容的第一电极的半导体层进行金属化，以形成所述存储电容的第一电极。
其中，所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度和覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度相同，且为所述覆盖其他半导体层的第一保护层的厚度的二分之一。
其中，所述在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极的步骤之后，包括：在形成所述源极和漏极的基板上形成第二保护层；在所述漏极之上的第二保护层中设置导通孔；在所述第二保护层上形成作为所述存储电容的第二电极的透明导电层，并使所述透明导电层通过所述导通孔与所述漏极连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种薄膜晶体管基板的制作方法，包括：在基板上依次沉积并图案化第一金属层和绝缘层，以分别形成薄膜晶体管的栅极和栅极绝缘层；在所述栅极绝缘层上依次沉积半导体层和第一保护层；对所述第一保护层进行图案化以除去部分所述第一保护层，并至少保留位于用于形成所述薄膜晶体管的半导体通道的半导体层上的第一保护层；利用图案化之后的所述第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道；在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极，所述源极和所述漏极分别与所述半导体通道接触。
其中，所述对所述第一保护层进行图案化的步骤包括：使覆盖用于形成所述半导体通道的半导体层的第一保护层中，覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度；在所述利用图案化之后的所述第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层的步骤之后，包括：对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻，以除去所述覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与所述源极、漏极接触的半导体通道的半导体层；利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道。
其中，所述半导体层的材料为氧化铟镓锌；所述对所述第一保护层进行图案化的步骤包括：对所述第一保护层进行图案化，以保留位于用于形成存储电容的第一电极的半导体层上的第一保护层，且所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度小于所述覆盖其他半导体层的第一保护层的厚度；所述对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻的步骤，还包括：除去所述位于用于形成存储电容的第一电极的半导体层上的第一保护层，以暴露所述用于形成存储电容的第一电极的半导体层；所述利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化的步骤，还包括：利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成存储电容的第一电极的半导体层进行金属化，以形成所述存储电容的第一电极。
其中，所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度和覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度相同，且为所述覆盖其他半导体层的第一保护层的厚度的二分之一。
其中，所述在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极的步骤之后，包括：在形成所述源极和漏极的基板上形成第二保护层；在所述漏极之上的第二保护层中设置导通孔；在所述第二保护层上形成作为所述存储电容的第二电极的透明导电层，并使所述透明导电层通过所述导通孔与所述漏极连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种薄膜晶体管基板的制造设备，包括：涂布机构；第一光罩，用于在所述涂布机构在基板上涂布第一金属层后对所述第一金属层进行图案化，以形成薄膜晶体管的栅极；第二光罩，用于在所述涂布机构在所述栅极上涂布绝缘层后，对所述绝缘层进行图案化，以形成所述薄膜晶体管的栅极绝缘层；第三光罩，用于在所述涂布机构在所述栅极绝缘层上依次涂布半导体层和第一保护层后，对所述第一保护层进行图案化以除去部分所述第一保护层，并至少保留位于用于形成所述薄膜晶体管的半导体通道的半导体层上的第一保护层，以利用保留的第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道；第四光罩，用于在所述涂布机构在所述半导体通道上涂布第二金属层后，对所述第二金属层进行图案化，以形成所述薄膜晶体管的源极和漏极，所述源极和所述漏极分别与所述半导体通道接触。
其中，所述第三光罩用于对所述第一保护层进行图案化，以使覆盖用于形成所述半导体通道的半导体层的第一保护层中，覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度；所述制造设备还包括：蚀刻机构，用于对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻，以除去所述覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与所述源极、漏极接触的半导体通道的半导体层；金属化机构，用于利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道。
其中，所述半导体层的材料为氧化铟镓锌；所述第三光罩还用于对所述第一保护层进行图案化，以保留位于用于形成存储电容的第一电极的半导体层上的第一保护层，且所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度小于所述覆盖其他半导体层的第一保护层的厚度；所述蚀刻机构还用于对所述位于用于形成存储电容的第一电极的半导体层上的第一保护层进行蚀刻，以除去所述位于用于形成存储电容的第一电极的半导体层上的第一保护层，进而暴露所述用于形成存储电容的第一电极的半导体层；所述金属化机构还用于利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成存储电容的第一电极的半导体层进行金属化，以形成所述存储电容的第一电极。
其中，所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度和覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度相同，且为所述覆盖其他半导体层的第一保护层的厚度的二分之一。
其中，所述涂布机构还用于在形成所述源极和漏极的基板上涂布第二保护层；所述制造设备还包括第五光罩，用于对所述第二保护层进行图案化，以在所述漏极之上的第二保护层中形成导通孔；所述涂布机构还用于在所述第二保护层上涂布作为所述存储电容的第二电极的透明导电层，并使所述透明导电层通过所述导通孔与所述漏极连接。
本发明的有益效果是：区别于现有技术的情况，本发明薄膜晶体管基板的制作方法中，在形成薄膜晶体管的栅极和栅极绝缘层之后，依次沉积半导体层和第一保护层，在对第一保护层图案化之后，利用图案化之后的第一保护层为光罩对半导体层进行图案化，以形成薄膜晶体管的半导体通道，由此不需要增加另外的半导体通道光罩对半导体层进行曝光，能够减少光罩数目，有利于降低成本，同时能够减少对位误差和电容耦合。
【附图说明】
图1是现有技术中一种薄膜晶体管基板的制作方法示意图；
图2是本发明薄膜晶体管基板的制作方法一实施方式的流程图；
图3是本发明薄膜晶体管基板的制作方法一实施方式的截面图；
图4是本发明薄膜晶体管基板的制作方法另一实施方式的截面图；
图5是本发明薄膜晶体管基板的制作方法又一实施方式的截面图；
图6是本发明薄膜晶体管基板的制作方法又一实施方式的截面图；
图7是本发明薄膜晶体管基板的制造设备一实施方式的结构示意图；
图8是本发明薄膜晶体管基板的制造设备另一实施方式的结构示意图；
图9是本发明薄膜晶体管基板的制造设备又一实施方式的结构示意图。
【具体实施方式】
下面将结合附图及实施方式对本发明进行详细说明。
参阅图2，本发明薄膜晶体管基板的制作方法一实施方式中，薄膜晶体管基板为应用于OLED显示面板的薄膜晶体管基板。由于OLED为电流型驱动，因此每个像素需要两个薄膜晶体管驱动，一个薄膜晶体管作为开关作用，以进行开启、关闭的控制，另一薄膜晶体管作为像素发光的驱动电流的提供者，用以控制OLED的电流大小。因此，本实施方式中，薄膜晶体管基板上每个像素对应两个薄膜晶体管，其制作过程包括如下步骤：
步骤S201：在基板上依次沉积并图案化第一金属层和绝缘层，以分别形成薄膜晶体管的栅极和栅极绝缘层。
结合图3，图3是本发明薄膜晶体管基板的制作方法的示意图。如图3所示的步骤S301，该步骤为第一道光罩制程，在基板30上首先沉积第一金属层，并利用具有形成栅极图案的光罩对第一金属层进行曝光，以分别形成两个薄膜晶体管的栅极31a、31b，其中栅极31a为用于开关的薄膜晶体管Q1的栅极，栅极31b为用于控制OLED电流的薄膜晶体管Q2的栅极。第一金属层可以为铜金属层。
步骤S302为第二道光罩制程，在栅极31a、31b上沉积绝缘层，并利用具有形成栅极绝缘层图案的光罩对绝缘层进行曝光，以形成薄膜晶体管Q1、Q2的栅极绝缘层32，且在栅极31a上方的栅极绝缘层32上形成导通孔32a。栅极绝缘层32覆盖栅极31a、31b。
步骤S202：在栅极绝缘层上依次沉积半导体层和第一保护层。
如图3所示的步骤S303，在栅极绝缘层32上依次沉积半导体层33和第一保护层34。半导体层33覆盖栅极绝缘层32，第一保护层34覆盖半导体层33。其中，半导体层33用于形成薄膜晶体管Q1、Q2的有源层，即半导体通道，第一保护层34为蚀刻阻挡层（ES，Etch-Stopper），具体可以为氮化硅材料层，当然，也可以是二氧化硅等其他材料层。
步骤S203：对第一保护层进行图案化以除去部分第一保护层，并至少保留位于用于形成薄膜晶体管的半导体通道的半导体层上的第一保护层。
对应于图3所示的步骤S304，该步骤为第三道光罩制程，本步骤中，利用第三道光罩对第一保护层34进行曝光，以除去部分第一保护层34，且保留位于用于形成薄膜晶体管Q1、Q2的半导体通道的半导体层上的第一保护层34a、34b。其中，除了位于用于形成薄膜晶体管Q1、Q2的半导体通道的半导体层上的第一保护层34a、34b之外，其他第一保护层34均去除。
步骤S204：利用图案化之后的第一保护层为光罩对半导体层进行图案化，以除去没有被第一保护层覆盖的半导体层，进而在栅极绝缘层上形成薄膜晶体管的半导体通道。
对应于图3所示的步骤S305，该步骤相当于第四道光罩制程，但在本步骤中，并不需要另外的光罩对半导体层33进行曝光。在步骤S303中，对第一保护层34进行曝光后，在基板上保留了位于用于形成半导体通道的半导体层上的第一保护层34a、34b，而半导体层33则是用于形成半导体通道，即在基板上只需保留用于形成半导体通道的半导体层即可。因此，本实施方式中，利用保留的第一保护层34a、34b为自对准光罩对半导体层33进行曝光，以将没有被第一保护层34覆盖的半导体层33除去，而保留了被第一保护层34a、34b所覆盖的半导体层33，从而分别形成了两个薄膜晶体管Q1、Q2的半导体通道33a、33b。而第一保护层34a、34b为蚀刻阻挡层，例如可以为氮化硅层，对半导体通道33a、33b形成保护作用，有利于防止半导体通道33a、33b的腐蚀和凹陷，且能够提高击穿电压和器件可靠性。
步骤S205：在半导体通道上沉积并图案化第二金属层，以形成薄膜晶体管的源极和漏极，源极和漏极分别与半导体通道接触。
对应于图3所示的步骤S306，利用具有源极和漏极图案的光罩对第二金属层进行曝光，以形成薄膜晶体管Q1的源极35b和漏极35a，以及形成薄膜晶体管Q2的源极35b’和35a’。其中，源极35b和漏极35a与相对应的薄膜晶体管Q1的半导体通道33a接触，源极35b’和35a’与相对应的薄膜晶体管Q2的半导体通道33b接触。此外，作为开关作用的薄膜晶体管Q2的漏极35a’通过导通孔32a与用于控制OLED的薄膜晶体管Q1的栅极31连接。通过半导体通道33a、33b的作用可分别实现两个薄膜晶体管的源极和漏极电性连接或电性绝缘。
现有技术中，在形成薄膜晶体管的过程中，首先利用一道光罩来形成半导体通道，然后在半导体通道上沉积蚀刻阻止层，并利用另一道光罩对蚀刻阻止层进行曝光，因此现有技术形成栅极、栅极绝缘层、半导体通道、蚀刻阻止层、源漏极的过程中共需要五道光罩，所需光罩数目较多。与现有技术相比，本实施方式中，在形成半导体通道时利用图案化之后的第一保护层34a、34b作为自对准光罩对半导体层33进行曝光，以形成半导体通道33a、33b，由此不需要单独的光罩对半导体层进行曝光，可减少半导体层的光罩，因此能够减少光罩数目，有利于降低成本，同时还能够减少光罩对位误差及电容耦合。
上述实施方式中，源极35b、35b’和漏极35a、35a’与半导体通道33a、33b的侧面相接触。为了提高半导体通道和源漏极之间接触的可靠性，在本发明薄膜晶体管基板的制作方法另一实施方式中，采用half-tone mask（半色调光罩）技术对第一保护层34进行图案化，以增大源漏极和半导体通道之间的接触面积。参阅图4，其中，相同的步骤可参考上述实施方式进行，此处不进行一一赘述，本实施方式中，使源极35b、35b’和漏极35a、35a’与半导体通道33a、33b靠近第一保护层34a、34b的上表面相接触，以增大接触面积。具体地，在步骤S404中，采用半色调光罩作为第三道光罩对第一保护层34进行曝光，使得保留的位于用于形成半导体通道的半导体层33上的第一保护层34a、34b中，覆盖用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度。进一步而言，对第一保护层34曝光时，需要保留的位于用于形成半导体通道的半导体层33上的第一保护层34a、34b中，中间部分的第一保护层34为全不曝光，厚度保留最厚，两端的第一保护层34为一定程度的曝光以除去部分厚度的第一保护层，以保留具有一定厚度的第一保护层在半导体层33上。其中，两端的第一保护层即为覆盖用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层的第一保护层，其在半导体层33上的位置即为源极和漏极与半导体通道的上表面相接触的位置
接着在步骤S405中利用图案化之后的第一保护层34a、34b为光罩对半导体层33进行曝光，以除去没有被第一保护层34a、34b覆盖的半导体层，而保留了被第一保护层34a、34b所覆盖的半导体层，保留的半导体层即形成半导体通道33a、34b。在步骤S406中，对覆盖用于形成半导体通道的半导体层33的第一保护层34a、34b进行蚀刻，以除去覆盖用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层。由于覆盖用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层的第一保护层的厚度小于中间的第一保护层的厚度，因此在对半导体通道33a、33b上的第一保护层34a、34b进行蚀刻时，通过控制蚀刻条件可以将两端较小厚度的第一保护层完全去除，进而暴露两端的半导体通道，而中间厚度较厚的第一保护层仅是被除去一部分，被除去的量与厚度较小的第一保护层的量基本相同，因此中间的第一保护层仍能保留部分在半导体通道33a、33b上，以保护半导体通道33a、33b。
在步骤S407中，在半导体通道33a、33b上沉积并图案化第二金属层，以形成源极35b、35b’和漏极35a、35a’。其中，在薄膜晶体管Q1中，第一保护层34a位于源极35b和漏极35a之间，源极35b和漏极35a均与半导体通道33a的靠近第一保护层34a的上表面相接触；在薄膜晶体管Q2中，第一保护层34b位于源极35b’和漏极35a’之间，源极35b’和漏极35a’均与半导体通道33b的靠近第一保护层34b的上表面相接触，由此可以增大接触面积，有利于提高器件的可靠性。
在本发明薄膜晶体管基板的制造方法的实施方式中，半导体层为非晶IGZO（氧化铟镓锌）材料层，从而可以提高载流子迁移率，进而可大大提高像素电极的充放电速率。当然，在其他实施方式中，半导体层也可以是非晶硅（a-Si）材料层。
在使用非晶IGZO材料形成半导体层时，由于氧化物半导体和金属材料接触处有势垒的存在，影响器件电子传输，因此，在本发明薄膜晶体管基板的制造方法的又一实施方式中，如图5所示，与图4所示的实施方式不同的是，增加了一道金属化制程，即图5所示的步骤S507。在步骤S506中，对第一保护层34a、34b进行蚀刻以除去覆盖用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层的第一保护层之后，执行步骤S507，利用蚀刻之后的第一保护层34a、34b为光罩对暴露的用于形成与源极35b、35b’和漏极35a、35a’接触的半导体通道的半导体层进行金属化，进而形成半导体通道33a、33b。在对暴露的半导体通道进行金属化之后，沉积并图案化第二金属层以形成源极和漏极。其中，源极和漏极与金属化之后的半导体层接触。
通过对半导体层进行金属化，能够降低半导体通道和源极35b、35b’和漏极35a、35a’接触处的阻抗，从而进一步提高器件的性能。此外，在本实施方式中，利用蚀刻之后的第一保护层34a、34b为自对准光罩对半导体层进行金属化，不需要增加额外的光罩来进行金属化，与单独增加一道光罩进行金属化的方案相比，能够减少光罩数目，有利于降低制造成本。
在薄膜晶体管的制作过程中，通常会设置存储电容，用以保持电位，以使得显示面板能够正常显示。现有技术中，通常是以金属电极夹置绝缘层制作，然而金属为不透光材料，会造成面板开口率降低。本发明薄膜晶体管基板的制作方法的实施方式中，采用透明的IGZO形成半导体层和存储电容的一个电极，以提高开口率。具体地，参阅图6，其中步骤S601为形成栅极31a、31b，步骤S602为形成栅极绝缘层32，步骤S603为依次沉积半导体层33和第一保护层34。
在步骤S604中，对第一保护层34进行图案化。具体为利用半色调光罩对第一保护层34进行曝光，以除去部分第一保护层，且除了保留位于用于形成半导体通道的半导体层上的第一保护层外，还保留位于用于形成存储电容的第一电极的半导体层上的第一保护层。其中，覆盖在后续制程中需要完全除去的半导体层的第一保护层为全曝光，而覆盖在后续制程中用于形成与源极和漏极接触的半导体通道的半导体层的第一保护层以及位于用于形成存储电容的第一电极的半导体层上的第一保护层为部分程度曝光，覆盖在后续制程中用于形成保护半导体通道的半导体层的第一保护层为全不曝光。所述的用于形成保护半导体通道的半导体层即为位于用于形成半导体通道的半导体层中，除用于形成与源极和漏极接触的半导体通道的半导体层之外的其他半导体层。经过上述曝光之后，全曝光的第一保护层被完全除去，以使得对应的半导体层暴露，而全不曝光的第一保护层则保留原始的厚度，部分程度曝光的第一保护层被除去一部分，保留具有一定厚度的第一保护层，且该具有一定厚度的第一保护层的厚度小于全不曝光的第一保护层的厚度。
因此，如图6所示的步骤S604，曝光之后的第一保护层的图案包括位于用于形成半导体通道的半导体层33上的呈阶梯状的第一保护层34a、34b，以及位于用于形成存储电容的第一电极的半导体层33上的第一保护层34c。呈阶梯状的第一保护层34a、34b中，厚度较小的第一保护层为覆盖用于形成与源极漏极接触的半导体通道的半导体层的第一保护层。
进一步地，为了更好地控制曝光条件，本实施方式中，部分程度曝光的第一保护层为半曝光，以除去一半厚度的第一保护层，从而使得覆盖用于形成与源极漏极接触的半导体层的第一保护层的厚度和覆盖用于形成存储电容的第一电极的半导体层的第一保护层的厚度为全不曝光的第一保护层的厚度的一半，即该具有一定厚度的第一保护层的厚度为原始厚度的一半。当然，在其他实施方式中，覆盖用于形成与源极漏极接触的半导体层的第一保护层的厚度和覆盖用于形成存储电容的第一电极的半导体层的第一保护层的厚度也可以不相等，且其厚度也可不限于为原始厚度的一半，可根据实际需要进行设定，只要满足其小于全不曝光的第一保护层的厚度且能够确保完全遮挡半导体层即可。
步骤S605中，以曝光之后的第一保护层34a、34b、34c为光罩对半导体层33进行曝光，从而除去没有被第一保护层34a、34b、34c覆盖的半导体层，并保留了被第一保护层34a、34b、34c覆盖的半导体层，以用于形成半导体通道和存储电容的第一电极。
步骤S606中，对第一保护层34a、34b、34c进行蚀刻，以除去覆盖用于形成与源极漏极接触的半导体通道的半导体层的第一保护层34a、34b和覆盖用于形成存储电容的第一电极的半导体层的第一保护层34c，以使得用于形成与源极漏极接触的半导体通道的半导体层和用于形成存储电容的第一电极的半导体层暴露。而由于覆盖用于形成保护半导体通道的半导体层的第一保护层34a、34b的厚度比其他第一保护层的厚度大，因此通过控制蚀刻条件，在其他厚度较小的第一保护层被蚀刻掉之后，覆盖用于形成保护半导体通道的半导体层的第一保护层34a、34b仍能保留部分在半导体通道上，以保护半导体通道。
步骤S607中，以蚀刻之后的第一保护层34a、34b为光罩，对暴露的半导体层进行金属化，从而形成薄膜晶体管Q1的半导体通道33a、薄膜晶体管Q2的半导体通道33b以及存储电容的第一电极33c。其中，可以通过H扩散、离子注入或Plasma电浆处理等方式对半导体层进行金属化。
步骤S608中，在半导体通道33a、33b上沉积并图案化第二金属层，以形成薄膜晶体管Q1的源极35b和漏极35a、薄膜晶体管Q2的源极35b’和漏极35a’。
更进一步地，本实施方式中，在形成源极35b、35b’和漏极35a、35a’之后，在步骤S608中，在形成源极35b、35b’和漏极35a、35a’的基板上形成第二保护层36，并利用光罩对第二保护层36进行图案化，以在薄膜晶体管Q2的漏极35a上的第二保护层36中形成导通孔36a。其中，第二保护层为绝缘层或钝化层，可以使用二氧化硅材料制成。之后，在第二保护层36上形成透明导电层37，该透明导电层37用于形成像素电极，其通过导通孔36a与薄膜晶体管Q2的漏极35a连接。此外，该透明导电层37作为存储电容的第二电极，与第一电极33c通过夹置第二保护层36而形成存储电容。
通过本实施方式，通过利用图案化之后的第一保护层34a、34b、34c作为自对准光罩对半导体层33进行曝光，由此能够减少半导体层33曝光的光罩，同时能减少对位误差和电容耦合，且利用蚀刻之后的第一保护层34a、34b为光罩进行金属化，能够进一步减少一道金属化光罩，有利于降低成本。此外，通过对与源漏极接触的部分半导体通道进行金属化，能够减少源漏极和半导体通道接触处的阻抗，有利于提高电子传输。并且，存储电容为使用透明的IGZO半导体层和透明导电层形成，与采用不透光的金属形成的存储电容相比，有利于提高开口率。
在本发明薄膜晶体管基板的制造方法的另一实施方式中，薄膜晶体管基板还可以是用于液晶显示面板的阵列基板，其与上述用于OLED的薄膜晶体管基板的实施方式不同的是，基板中的薄膜晶体管的数量为1个，即用于开关作用的薄膜晶体管Q1，此时用于形成像素电极的透明导电层与薄膜晶体管Q1的漏极连接，具体的制作过程与上述各实施方式相类似，此处不进行一一赘述。
本发明还提供薄膜晶体管基板的一实施方式，所述薄膜晶体管基板为通过利用上述任一实施方式所述的薄膜晶体管基板的制作方法所制成。其中，薄膜晶体管基板包括存储电容，该存储电容的第一电极为利用氧化铟镓锌制成，第二电极为作为像素电极的透明导电层形成。
参阅图7，本发明薄膜晶体管基板的制作设备一实施方式中，包括涂布机构70、第一光罩71、第二光罩72、第三光罩73以及第四光罩74。其中，涂布机构70用于涂布第一金属层、绝缘层、半导体层、第一保护层以及第二金属层。第一光罩71用于在涂布机构70在基板上涂布第一金属层后对第一金属层进行图案化，以形成薄膜晶体管的栅极。第二光罩72用于在涂布机构在栅极上涂布绝缘层后，对绝缘层进行图案化，以形成薄膜晶体管的栅极绝缘层。第三光罩73用于在涂布机构在栅极绝缘层上依次涂布半导体层和第一保护层之后，对第一保护层进行图案化以除去部分第一保护层，并至少保留用于形成薄膜晶体管的半导体通道的半导体层上的第一保护层，以利用保留的第一保护层为光罩对半导体层进行图案化，以除去没有被第一保护层覆盖的半导体层，进而在栅极绝缘层上形成薄膜晶体管的半导体通道。其中，第一保护层为蚀刻阻挡层（ES）。第四光罩74用于在涂布机构在半导体通道上涂布第二金属层后，对第二金属层进行图案化，以形成薄膜晶体管的源极和漏极，源极和漏极分别与半导体通道接触。
通过上述方式，在形成栅极、栅极绝缘层、半导体通道、第一保护层以及源极漏极的过程中，与现有的需要五道光罩相比，本实施方式中，通过利用图案化之后的第一保护层为自对准光罩对半导体层进行图案化，由此只需四道光罩即可完成上述过程，能够减少光罩数目，同时可以减少对位误差和电容耦合。
在本发明薄膜晶体管基板的制造设备另一实施方式中，如图8所示，与上述实施方式的主要不同之处在于，制造设备还包括蚀刻机构85和金属化机构86。第三光罩83用于对第一保护层进行图案化，并使得所保留的位于用于形成半导体通道的半导体层上的第一保护层中，覆盖用于形成与源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度。在利用图案化之后的第一保护层对半导体层进行图案化以除去没有被第一保护层覆盖的半导体层之后，蚀刻机构85用于对覆盖用于形成半导体通道的半导体层的第一保护层进行蚀刻，以除去覆盖用于形成与源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与源极、漏极接触的半导体通道的半导体层。金属化机构86用于利用蚀刻之后的第一保护层为光罩对暴露的用于形成与源极、漏极接触的半导体通道的半导体层进行金属化，进而在栅极绝缘层上形成薄膜晶体管的半导体通道。对暴露的半导体层进行金属化之后，涂布机构80在所形成的半导体通道上涂布第二金属层，第四光罩84用于对第二金属层进行图案化以形成源极和漏极。其中，源极和漏极与金属化之后的半导体层接触。通过对半导体层进行金属化，能够减小半导体通道与源极和漏极接触处的阻抗，有利于提高电子传输效率。
在本发明薄膜晶体管基板的制造设备又一实施方式中，薄膜晶体管基板上还形成存储电容，本实施方式中，半导体层的材料为氧化铟镓锌，利用半导体层形成存储电容，由此可提高开口率。具体地，参阅图9，与上述实施方式不同的是，在利用第三光罩93对第一保护层进行图案化时，除了保留位于用于形成半导体通道的半导体层上的第一保护层之外，还保留位于用于形成存储电容的第一电极的半导体层上的第一保护层。其中，覆盖在后续制程中需要完全除去的半导体层的第一保护层为全曝光，而覆盖在后续制程中用于形成与源极和漏极接触的半导体通道的半导体层的第一保护层以及位于用于形成存储电容的第一电极的半导体层上的第一保护层为部分程度曝光，覆盖在后续制程中用于形成保护半导体通道的半导体层的第一保护层为全不曝光。所述的用于形成保护半导体通道的半导体层即为位于用于形成半导体通道的半导体层中，除用于形成与源极和漏极接触的半导体通道的半导体层之外的其他半导体层。经过上述曝光之后，全曝光的第一保护层被完全除去，以使得对应的半导体层暴露，而全不曝光的第一保护层则保留原始的厚度，部分程度曝光的第一保护层被除去一部分，保留具有一定厚度的第一保护层，且该具有一定厚度的第一保护层的厚度小于全不曝光的第一保护层的厚度。
曝光之后的第一保护层的图案包括位于用于形成半导体通道的半导体层上的呈阶梯状的第一保护层，以及位于用于形成存储电容的第一电极的半导体层上的第一保护层。呈阶梯状的第一保护层中，厚度较小的第一保护层为覆盖用于形成与源极漏极接触的半导体通道的半导体层的第一保护层。
进一步地，为了更好地控制曝光条件，本实施方式中，部分程度曝光的第一保护层为半曝光，以除去一半厚度的第一保护层，从而使得覆盖用于形成与源极漏极接触的半导体层的第一保护层的厚度和覆盖用于形成存储电容的第一电极的半导体层的第一保护层的厚度为全不曝光的第一保护层的厚度的一半，即该具有一定厚度的第一保护层的厚度为原始厚度的一半。当然，在其他实施方式中，覆盖用于形成与源极漏极接触的半导体层的第一保护层的厚度和覆盖用于形成存储电容的第一电极的半导体层的第一保护层的厚度也可以不相等，且其厚度也可不限于为原始厚度的一半，可根据实际需要进行设定，只要满足其小于全不曝光的第一保护层的厚度且能够确保完全遮挡半导体层即可。
此外，为了更好地控制曝光条件，本实施方式中，部分程度曝光的第一保护层为半曝光，以除去一半厚度的第一保护层，从而使得覆盖用于形成与源极漏极接触的半导体层的第一保护层的厚度和覆盖用于形成存储电容的第一电极的半导体层的第一保护层的厚度为全不曝光的第一保护层的厚度的一半，即该具有一定厚度的第一保护层的厚度为原始厚度的一半。当然，在其他实施方式中，覆盖用于形成与源极漏极接触的半导体层的第一保护层的厚度和覆盖用于形成存储电容的第一电极的半导体层的第一保护层的厚度也可以不相等，且其厚度也可不限于为原始厚度的一半，可根据实际需要进行设定，只要满足其小于全不曝光的第一保护层的厚度且能够确保完全遮挡半导体层即可。
在利用图案化之后的第一保护层对半导体层进行图案化之后，蚀刻机构95用于对覆盖用于形成与源极漏极接触的半导体层的第一保护层和覆盖用于形成存储电容的第一电极的半导体层进行蚀刻，以除去覆盖用于形成与源极漏极接触的半导体层的第一保护层和覆盖用于形成存储电容的第一电极的半导体层，进而暴露用于形成与源极漏极接触的半导体层和用于形成存储电容的第一电极的半导体层。金属化机构96用于利用蚀刻之后的第一保护层为光罩对暴露的半导体层进行金属化，从而形成薄膜晶体管的半导体通道和存储电容的第一电极。
形成薄膜晶体管的半导体通道和存储电容的第一电极之后，涂布机构90在半导体通道上涂布第二金属层，第四光罩94用于对第二金属层进行图案化以形成薄膜晶体管的源极和漏极。
此外，本实施方式中，制造设备进一步还包括第五光罩97。在形成薄膜晶体管的源极和漏极之后，涂布机构90用于在源极和漏极上涂布第二保护层，该第二保护层可以为绝缘层或钝化层，可以使用二氧化硅材料制成。第五光罩97用于对第二保护层进行图案化，以在薄膜晶体管的漏极上的第二保护层中形成导通孔。涂布机构90还用于在第二保护层上涂布作为存储电容的第二电极的透明导电层，并使该透明导电层通过导通孔与漏极连接。其中，该透明导电层同时也作为像素电极以实现显示。
本实施方式中，通过使用透明的氧化铟镓锌和透明导电层通过夹置第二保护层以形成存储电容，与现有的采用不透光的金属形成存储电容的技术相比，能够提高开口率。同时，本实施方式利用图案化之后的第一保护层为自对准光罩对半导体层进行曝光，能够减少半导体层的光罩，且减少对位误差和电容耦合，且利用蚀刻之后的第一保护层为自对准光罩对半导体层进行金属化，能够减少金属化所需的光罩，进一步减少光罩数目。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种薄膜晶体管基板的制作方法，其中，所述薄膜晶体管基板用于OLED显示面板，包括：
    在基板上依次沉积并图案化第一金属层和绝缘层，以分别形成薄膜晶体管的栅极和栅极绝缘层；
    在所述栅极绝缘层上依次沉积半导体层和第一保护层，所述第一保护层为蚀刻阻挡层，其材料为氮化硅；
    对所述第一保护层进行图案化以除去部分所述第一保护层，并至少保留位于用于形成所述薄膜晶体管的半导体通道的半导体层上的第一保护层，其中，使覆盖用于形成所述半导体通道的半导体层的第一保护层中，覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度；
    利用图案化之后的所述第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层；
    对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻，以除去所述覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与所述源极、漏极接触的半导体通道的半导体层；
    利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道；
    在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极，所述源极和所述漏极分别与所述半导体通道接触。
  2. 根据权利要求1所述的制作方法，其中，
    所述半导体层的材料为氧化铟镓锌；
    所述对所述第一保护层进行图案化的步骤包括：
    对所述第一保护层进行图案化，以保留位于用于形成存储电容的第一电极的半导体层上的第一保护层，且所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度小于所述覆盖其他半导体层的第一保护层的厚度；
    所述对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻的步骤，还包括：
    除去所述位于用于形成存储电容的第一电极的半导体层上的第一保护层，以暴露所述用于形成存储电容的第一电极的半导体层；
    所述利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化的步骤，还包括：
    利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成存储电容的第一电极的半导体层进行金属化，以形成所述存储电容的第一电极。
  3. 根据权利要求2所述的制作方法，其中，
    所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度和覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度相同，且为所述覆盖其他半导体层的第一保护层的厚度的二分之一。
  4. 根据权利要求2所述的制作方法，其中，
    所述在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极的步骤之后，包括：
    在形成所述源极和漏极的基板上形成第二保护层；
    在所述漏极之上的第二保护层中设置导通孔；
    在所述第二保护层上形成作为所述存储电容的第二电极的透明导电层，并使所述透明导电层通过所述导通孔与所述漏极连接。
  5. 一种薄膜晶体管基板的制作方法，其中，包括：
    在基板上依次沉积并图案化第一金属层和绝缘层，以分别形成薄膜晶体管的栅极和栅极绝缘层；
    在所述栅极绝缘层上依次沉积半导体层和第一保护层；
    对所述第一保护层进行图案化以除去部分所述第一保护层，并至少保留位于用于形成所述薄膜晶体管的半导体通道的半导体层上的第一保护层；
    利用图案化之后的所述第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道；
    在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极，所述源极和所述漏极分别与所述半导体通道接触。
  6. 根据权利要求5所述的制作方法，其中，
    所述对所述第一保护层进行图案化的步骤包括：
    使覆盖用于形成所述半导体通道的半导体层的第一保护层中，覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度；
    在所述利用图案化之后的所述第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层的步骤之后，包括：
    对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻，以除去所述覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与所述源极、漏极接触的半导体通道的半导体层；
    利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道。
  7. 根据权利要求6所述的制作方法，其中，
    所述半导体层的材料为氧化铟镓锌；
    所述对所述第一保护层进行图案化的步骤包括：
    对所述第一保护层进行图案化，以保留位于用于形成存储电容的第一电极的半导体层上的第一保护层，且所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度小于所述覆盖其他半导体层的第一保护层的厚度；
    所述对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻的步骤，还包括：
    除去所述位于用于形成存储电容的第一电极的半导体层上的第一保护层，以暴露所述用于形成存储电容的第一电极的半导体层；
    所述利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化的步骤，还包括：
    利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成存储电容的第一电极的半导体层进行金属化，以形成所述存储电容的第一电极。
  8. 根据权利要求7所述的制作方法，其中，
    所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度和覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度相同，且为所述覆盖其他半导体层的第一保护层的厚度的二分之一。
  9. 根据权利要求7所述的制作方法，其中，
    所述在所述半导体通道上沉积并图案化第二金属层，以形成所述薄膜晶体管的源极和漏极的步骤之后，包括：
    在形成所述源极和漏极的基板上形成第二保护层；
    在所述漏极之上的第二保护层中设置导通孔；
    在所述第二保护层上形成作为所述存储电容的第二电极的透明导电层，并使所述透明导电层通过所述导通孔与所述漏极连接。
  10. 一种阵列基板的制造设备，其中，包括：
    涂布机构；
    第一光罩，用于在所述涂布机构在基板上涂布第一金属层后对所述第一金属层进行图案化，以形成薄膜晶体管的栅极；
    第二光罩，用于在所述涂布机构在所述栅极上涂布绝缘层后，对所述绝缘层进行图案化，以形成所述薄膜晶体管的栅极绝缘层；
    第三光罩，用于在所述涂布机构在所述栅极绝缘层上依次涂布半导体层和第一保护层后，对所述第一保护层进行图案化以除去部分所述第一保护层，并至少保留位于用于形成所述薄膜晶体管的半导体通道的半导体层上的第一保护层，以利用保留的第一保护层为光罩对所述半导体层进行图案化，以除去没有被所述第一保护层覆盖的半导体层，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道；
    第四光罩，用于在所述涂布机构在所述半导体通道上涂布第二金属层后，对所述第二金属层进行图案化，以形成所述薄膜晶体管的源极和漏极，所述源极和所述漏极分别与所述半导体通道接触。
  11. 根据权利要求10所述的制造设备，其中，
    所述第三光罩用于对所述第一保护层进行图案化，以使覆盖用于形成所述半导体通道的半导体层的第一保护层中，覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度小于覆盖其他半导体层的第一保护层的厚度；
    所述制造设备还包括：
    蚀刻机构，用于对所述覆盖用于形成所述半导体通道的半导体层的第一保护层进行蚀刻，以除去所述覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层，进而暴露用于形成与所述源极、漏极接触的半导体通道的半导体层；
    金属化机构，用于利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成与所述源极、漏极接触的半导体通道的半导体层进行金属化，进而在所述栅极绝缘层上形成所述薄膜晶体管的半导体通道。
  12. 根据权利要求11所述的制造设备，其中，
    所述半导体层的材料为氧化铟镓锌；
    所述第三光罩还用于对所述第一保护层进行图案化，以保留位于用于形成存储电容的第一电极的半导体层上的第一保护层，且所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度小于所述覆盖其他半导体层的第一保护层的厚度；
    所述蚀刻机构还用于对所述位于用于形成存储电容的第一电极的半导体层上的第一保护层进行蚀刻，以除去所述位于用于形成存储电容的第一电极的半导体层上的第一保护层，进而暴露所述用于形成存储电容的第一电极的半导体层；
    所述金属化机构还用于利用蚀刻之后的第一保护层为光罩对暴露的所述用于形成存储电容的第一电极的半导体层进行金属化，以形成所述存储电容的第一电极。
  13. 根据权利要求12所述的制造设备，其中，
    所述位于用于形成存储电容的第一电极的半导体层上的第一保护层的厚度和覆盖用于形成与所述源极、漏极接触的半导体通道的半导体层的第一保护层的厚度相同，且为所述覆盖其他半导体层的第一保护层的厚度的二分之一。
  14. 根据权利要求12所述的制造设备，其中，
    所述涂布机构还用于在形成所述源极和漏极的基板上涂布第二保护层；
    所述制造设备还包括第五光罩，用于对所述第二保护层进行图案化，以在所述漏极之上的第二保护层中形成导通孔；
    所述涂布机构还用于在所述第二保护层上涂布作为所述存储电容的第二电极的透明导电层，并使所述透明导电层通过所述导通孔与所述漏极连接。
PCT/CN2014/092504 2014-11-21 2014-11-28 薄膜晶体管基板的制作方法及制造设备 Ceased WO2016078112A1 (zh)

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