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WO2008093414A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
WO2008093414A1
WO2008093414A1 PCT/JP2007/051601 JP2007051601W WO2008093414A1 WO 2008093414 A1 WO2008093414 A1 WO 2008093414A1 JP 2007051601 W JP2007051601 W JP 2007051601W WO 2008093414 A1 WO2008093414 A1 WO 2008093414A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
same
sealing resin
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/051601
Other languages
English (en)
French (fr)
Inventor
Susumu Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to KR1020097012746A priority Critical patent/KR101057368B1/ko
Priority to JP2008555983A priority patent/JP5120266B6/ja
Priority to CN200780049019A priority patent/CN101617400A/zh
Priority to PCT/JP2007/051601 priority patent/WO2008093414A1/ja
Publication of WO2008093414A1 publication Critical patent/WO2008093414A1/ja
Priority to US12/479,915 priority patent/US8018033B2/en
Anticipated expiration legal-status Critical
Priority to US13/198,986 priority patent/US8497156B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H10W74/117
    • H10W42/20
    • H10W70/60
    • H10W74/014
    • H10W74/016
    • H10W74/40
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • H10W70/657
    • H10W72/0198
    • H10W72/073
    • H10W72/07331
    • H10W72/07552
    • H10W72/07553
    • H10W72/354
    • H10W72/527
    • H10W72/536
    • H10W72/5363
    • H10W72/537
    • H10W72/5445
    • H10W72/5522
    • H10W72/5525
    • H10W72/884
    • H10W74/00
    • H10W90/701
    • H10W90/724
    • H10W90/734
    • H10W90/754
    • H10W99/00

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

半導体装置(30)は、配線基板(32)と、当該配線基板(32)上に搭載された半導体素子(33)と、前記半導体素子(33)を被覆する封止用樹脂(36)と、一端が前記配線基板の配線層(32)に接続され、且つその一部が前記封止用樹脂(36)の表面に露出された接地用電極(38)と、前記封止用樹脂(36)を被覆し、且つ前記接地用電極(38)に接続されたシールド部材(39)とを有する。
PCT/JP2007/051601 2007-01-31 2007-01-31 半導体装置及びその製造方法 Ceased WO2008093414A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020097012746A KR101057368B1 (ko) 2007-01-31 2007-01-31 반도체 장치 및 그 제조 방법
JP2008555983A JP5120266B6 (ja) 2007-01-31 2007-01-31 半導体装置及びその製造方法
CN200780049019A CN101617400A (zh) 2007-01-31 2007-01-31 半导体器件及其制造方法
PCT/JP2007/051601 WO2008093414A1 (ja) 2007-01-31 2007-01-31 半導体装置及びその製造方法
US12/479,915 US8018033B2 (en) 2007-01-31 2009-06-08 Semiconductor device and manufacturing method of the same
US13/198,986 US8497156B2 (en) 2007-01-31 2011-08-05 Semiconductor device and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/051601 WO2008093414A1 (ja) 2007-01-31 2007-01-31 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/479,915 Continuation US8018033B2 (en) 2007-01-31 2009-06-08 Semiconductor device and manufacturing method of the same

Publications (1)

Publication Number Publication Date
WO2008093414A1 true WO2008093414A1 (ja) 2008-08-07

Family

ID=39673734

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/051601 Ceased WO2008093414A1 (ja) 2007-01-31 2007-01-31 半導体装置及びその製造方法

Country Status (5)

Country Link
US (2) US8018033B2 (ja)
JP (1) JP5120266B6 (ja)
KR (1) KR101057368B1 (ja)
CN (1) CN101617400A (ja)
WO (1) WO2008093414A1 (ja)

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WO2017200103A1 (ja) * 2016-05-20 2017-11-23 日立化成株式会社 離型フィルム
CN107535081A (zh) * 2015-05-11 2018-01-02 株式会社村田制作所 高频模块
WO2018164158A1 (ja) * 2017-03-08 2018-09-13 株式会社村田製作所 高周波モジュール
WO2018164159A1 (ja) * 2017-03-08 2018-09-13 株式会社村田製作所 モジュール
WO2019230705A1 (ja) * 2018-06-01 2019-12-05 株式会社村田製作所 高周波モジュール
WO2020110578A1 (ja) * 2018-11-30 2020-06-04 株式会社村田製作所 モジュール
JP2020109844A (ja) * 2019-01-01 2020-07-16 蔡 憲 聰 パッケージ内コンパートメントシールドを備える半導体パッケージ及びその製造方法
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