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WO2008105496A1 - キャパシタ搭載インターポーザ及びその製造方法 - Google Patents

キャパシタ搭載インターポーザ及びその製造方法 Download PDF

Info

Publication number
WO2008105496A1
WO2008105496A1 PCT/JP2008/053523 JP2008053523W WO2008105496A1 WO 2008105496 A1 WO2008105496 A1 WO 2008105496A1 JP 2008053523 W JP2008053523 W JP 2008053523W WO 2008105496 A1 WO2008105496 A1 WO 2008105496A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
substrate
interposer
main body
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/053523
Other languages
English (en)
French (fr)
Inventor
Akinobu Shibuya
Yasuhiro Ishii
Toru Mori
Koichi Takemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to US12/529,378 priority Critical patent/US20100044089A1/en
Priority to JP2009501297A priority patent/JP5463908B2/ja
Publication of WO2008105496A1 publication Critical patent/WO2008105496A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H10W70/635—
    • H10W70/685—
    • H10W72/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09763—Printed component having superposed conductors, but integrated in one circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • H10W72/07251—
    • H10W72/20—
    • H10W72/90—
    • H10W72/9226—
    • H10W72/923—
    • H10W72/9415—
    • H10W72/942—
    • H10W72/952—
    • H10W90/724—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

　キャパシタ搭載インターポーザ（１００）は、ビアプラグ（１２）が形成されたプラグ基板（１０）と、キャパシタが形成されたキャパシタ基板（２０）とを有する。キャパシタ基板（２０）は、基板本体（２１）と、基板本体の主面上に形成されたキャパシタ（２２）と、キャパシタを覆うカバー絶縁膜（２５）と、キャパシタの電極に接続されカバー絶縁膜の表面に形成された端子電極（２６）と、基板本体の裏面に形成された電極パッド（２４）と、端子電極と電極パッドとを接続するビアプラグ２３とを備える。プラグ基板（１０）は、基板本体（１１）と、基板本体の主面上に、キャパシタ基板の端子電極に対応して形成された電極パッド（１３）と、基板本体を貫通し電極パッドに接続されるビアプラグ（１２）とを備える。
PCT/JP2008/053523 2007-03-01 2008-02-28 キャパシタ搭載インターポーザ及びその製造方法 Ceased WO2008105496A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/529,378 US20100044089A1 (en) 2007-03-01 2008-02-28 Interposer integrated with capacitors and method for manufacturing the same
JP2009501297A JP5463908B2 (ja) 2007-03-01 2008-02-28 キャパシタ搭載インターポーザ及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-051131 2007-03-01
JP2007051131 2007-03-01

Publications (1)

Publication Number Publication Date
WO2008105496A1 true WO2008105496A1 (ja) 2008-09-04

Family

ID=39721320

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053523 Ceased WO2008105496A1 (ja) 2007-03-01 2008-02-28 キャパシタ搭載インターポーザ及びその製造方法

Country Status (3)

Country Link
US (1) US20100044089A1 (ja)
JP (1) JP5463908B2 (ja)
WO (1) WO2008105496A1 (ja)

Cited By (12)

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JP2014531756A (ja) * 2011-09-14 2014-11-27 インヴェンサス・コーポレイション 低ｃｔｅインターポーザ
US9245814B2 (en) 2013-04-05 2016-01-26 Hoya Corporation Substrate assembly, method of manufacturing substrate assembly and method of manufacturing chip package
JP2018133362A (ja) * 2017-02-13 2018-08-23 Tdk株式会社 電子部品内蔵基板
WO2018211614A1 (ja) * 2017-05-17 2018-11-22 株式会社野田スクリーン 薄膜キャパシタ構造、および当該薄膜キャパシタ構造を備えた半導体装置
JP2022508408A (ja) * 2019-08-23 2022-01-19 エスケイシー・カンパニー・リミテッド パッケージング基板及びこれを含む半導体装置
US11437308B2 (en) 2019-03-29 2022-09-06 Absolics Inc. Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus
US11652039B2 (en) 2019-03-12 2023-05-16 Absolics Inc. Packaging substrate with core layer and cavity structure and semiconductor device comprising the same
US11967542B2 (en) 2019-03-12 2024-04-23 Absolics Inc. Packaging substrate, and semiconductor device comprising same
US11981501B2 (en) 2019-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied
US12165979B2 (en) 2019-03-07 2024-12-10 Absolics Inc. Packaging substrate and semiconductor apparatus comprising same
US12198994B2 (en) 2019-03-12 2025-01-14 Absolics Inc. Packaging substrate and method for manufacturing same
US12288742B2 (en) 2019-03-07 2025-04-29 Absolics Inc. Packaging substrate and semiconductor apparatus comprising same

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US8730647B2 (en) * 2008-02-07 2014-05-20 Ibiden Co., Ltd. Printed wiring board with capacitor
US8765549B2 (en) 2012-04-27 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US8878338B2 (en) 2012-05-31 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US20140151095A1 (en) * 2012-12-05 2014-06-05 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
WO2014143016A1 (en) * 2013-03-15 2014-09-18 Intel Corporation Integrated capacitor based power distribution
US9478887B2 (en) 2013-11-01 2016-10-25 Quell Corporation Flexible electrical connector insert with conductive and non-conductive elastomers
US9692188B2 (en) 2013-11-01 2017-06-27 Quell Corporation Flexible electrical connector insert with conductive and non-conductive elastomers
WO2015171597A1 (en) 2014-05-05 2015-11-12 3D Glass Solutions, Inc. 2d and 3d inductors antenna and transformers fabricating photoactive substrates
TWI571185B (zh) * 2014-10-15 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
US12165809B2 (en) * 2016-02-25 2024-12-10 3D Glass Solutions, Inc. 3D capacitor and capacitor array fabricating photoactive substrates
KR102776261B1 (ko) * 2016-12-22 2025-03-07 삼성전기주식회사 적층형 커패시터 및 그 실장 기판
CA3084818C (en) 2017-12-15 2023-01-17 3D Glass Solutions, Inc. Coupled transmission line resonate rf filter
CA3135975C (en) 2019-04-05 2022-11-22 3D Glass Solutions, Inc. Glass based empty substrate integrated waveguide devices
JP2023516817A (ja) 2020-04-17 2023-04-20 スリーディー グラス ソリューションズ，インク 広帯域誘導
US11817379B2 (en) * 2020-07-13 2023-11-14 Qualcomm Incorporated Substrate comprising an inductor and a capacitor located in an encapsulation layer
US12407123B1 (en) 2020-11-23 2025-09-02 Quell Corporation Electrically dissipative flexible unitary connector insert
JP7444048B2 (ja) * 2020-12-22 2024-03-06 株式会社村田製作所 積層セラミックコンデンサ及び積層セラミックコンデンサの製造方法
US12439616B2 (en) * 2021-03-26 2025-10-07 Intel Corporation Integrated circuit package redistribution layers with metal-insulator-metal (MIM) capacitors
US20240079352A1 (en) * 2022-09-02 2024-03-07 Qualcomm Incorporated Integrated circuit (ic) packages employing capacitor interposer substrate with aligned external interconnects, and related fabrication methods

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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014531756A (ja) * 2011-09-14 2014-11-27 インヴェンサス・コーポレイション 低ｃｔｅインターポーザ
US9245814B2 (en) 2013-04-05 2016-01-26 Hoya Corporation Substrate assembly, method of manufacturing substrate assembly and method of manufacturing chip package
JP2018133362A (ja) * 2017-02-13 2018-08-23 Tdk株式会社 電子部品内蔵基板
WO2018211614A1 (ja) * 2017-05-17 2018-11-22 株式会社野田スクリーン 薄膜キャパシタ構造、および当該薄膜キャパシタ構造を備えた半導体装置
JP6427747B1 (ja) * 2017-05-17 2018-11-28 株式会社野田スクリーン 薄膜キャパシタ構造、および当該薄膜キャパシタ構造を備えた半導体装置
US12288742B2 (en) 2019-03-07 2025-04-29 Absolics Inc. Packaging substrate and semiconductor apparatus comprising same
US12165979B2 (en) 2019-03-07 2024-12-10 Absolics Inc. Packaging substrate and semiconductor apparatus comprising same
US12456672B2 (en) 2019-03-12 2025-10-28 Absolics Inc. Packaging substrate having element group in cavity unit and semiconductor device comprising the same
US12198994B2 (en) 2019-03-12 2025-01-14 Absolics Inc. Packaging substrate and method for manufacturing same
US11652039B2 (en) 2019-03-12 2023-05-16 Absolics Inc. Packaging substrate with core layer and cavity structure and semiconductor device comprising the same
US11967542B2 (en) 2019-03-12 2024-04-23 Absolics Inc. Packaging substrate, and semiconductor device comprising same
US11981501B2 (en) 2019-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied
US11437308B2 (en) 2019-03-29 2022-09-06 Absolics Inc. Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus
JP2022508408A (ja) * 2019-08-23 2022-01-19 エスケイシー・カンパニー・リミテッド パッケージング基板及びこれを含む半導体装置
JP7416868B2 (ja) 2019-08-23 2024-01-17 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
US12027454B1 (en) 2019-08-23 2024-07-02 Absolics Inc. Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
US11728259B2 (en) 2019-08-23 2023-08-15 Absolics Inc. Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
US11469167B2 (en) 2019-08-23 2022-10-11 Absolics Inc. Packaging substrate having electric power transmitting elements on non-circular core via of core vias and semiconductor device comprising the same
JP2022133442A (ja) * 2019-08-23 2022-09-13 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
JP7104245B2 (ja) 2019-08-23 2022-07-20 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置

Also Published As

Publication number Publication date
US20100044089A1 (en) 2010-02-25
JPWO2008105496A1 (ja) 2010-06-03
JP5463908B2 (ja) 2014-04-09

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