TWI902451B - Package structure and method of manufacturing the same - Google Patents

Abstract

A package structure includes a chip; a first metal film disposed over the chip; a sintered layer disposed on and in direct contact with the first metal film; a metal foil disposed on the sintered layer; and an interconnection conductor disposed on the metal foil and is electrically connected to the chip. The first metal film includes a first nano-twinned structure. A method for manufacturing the package structure is also provided.

Description

Packaging structure and manufacturing method

This invention relates to packaging technology, and more particularly to a packaging structure having a nano-twin structure and a method for manufacturing the same.

The inverter in the motor control unit of an electric vehicle is the most important key component for converting electrical energy into kinetic energy. The most important part affecting the power conversion efficiency is the power electronic module. The voltage/current specifications of automotive motor power module components reach 600V/450A, which is much higher than that of general power modules and consumer integrated circuits (ICs). They also need to pass various reliability tests of automotive-grade AEC-Q101. Therefore, the threshold for their packaging technology and materials is extremely high.

Interconnect technology is a technique in electronic packaging that uses a conductive material to connect chips and substrates. For the interconnects between the pads on power IC chips and the copper pads on ceramic substrates or printed circuit boards, thick metal wires or strips of 200 micrometers or more are mainly used. The thick metal wires or strips are bonded to the pads on the chip using an ultrasonic mechanism, which is not only low in cost but also highly efficient in production. However, conventional thick aluminum wires or aluminum strips, due to their low melting point (e.g., below 700°C), can no longer meet the requirements of power modules with higher current and higher voltage.

In recent years, the packaging industry has begun to experiment with using thick copper wire or strip, or thick silver wire or strip. These materials not only have better electrical and thermal conductivity than thick aluminum wire or strip, but also superior strength and reliability. However, the hardness of thick copper wire, copper strip, thick silver wire, and silver strip is much higher than that of thick aluminum wire or strip. Therefore, during ultrasonic wire bonding, power IC chips often break, which is a problem that urgently needs to be solved in power module packaging.

In one embodiment, a packaging structure is provided. The packaging structure includes a wafer, a first metal film disposed above the wafer, a sintered layer disposed on and in direct contact with the first metal film, a metal foil disposed on the sintered layer, and interconnect conductors disposed on the metal foil and electrically connected to the wafer. The first metal film has a first nanocrystalline structure.

In another embodiment, a method for manufacturing a packaging structure is provided. The method includes providing a wafer, forming a first metal thin film over the wafer, wherein the first metal thin film has a first nanocrystalline structure, performing a bonding process to bond a metal foil to the first metal thin film through a sintering layer, wherein the first metal thin film is in direct contact with the sintering layer, and bonding interconnect conductors to the metal foil using ultrasonic wire bonding, wherein the interconnect conductors are electrically connected to the wafer.

The following disclosure provides numerous embodiments or examples for implementing different elements of the provided object. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For instance, if the description mentions that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where additional elements are formed between the first and second elements so that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference numerals and/or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and/or configurations discussed.

The following describes some variations of the embodiments. In embodiments with different diagrams and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or deleted in other embodiments of the method.

Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

The terminology used herein is for the purpose of illustrating specific embodiments only and is not intended to limit the concepts of the invention. Unless an expression has a clearly distinct meaning in the context, the singular form of an expression also encompasses the plural form. In this specification, it should be understood that terms such as “comprising,” “having,” and “including” are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may be present or added.

The following describes some embodiments of the present invention, in which additional steps may be provided before, during, and/or after the multiple stages described in these embodiments. Some of the said stages may be substituted or omitted in different embodiments. The packaging structure may add additional components. Some of the said components may be substituted or omitted in different embodiments. Although some of the embodiments discussed are performed in a particular order, these steps may still be performed in another logically sound order.

The use of thick copper wire, copper strip, thick silver wire, or silver strip for ultrasonic wire bonding often results in the breakage of power IC chips. A known solution (US Patent US8164176B2) involves depositing a copper film with a thickness of 10 micrometers or more on top of the power IC chip to cushion the external load of the ultrasonic wire bonding process and prevent chip breakage. However, the inventors of this patent have discovered that depositing a copper film thicker than 10 micrometers on the chip surface easily causes the copper film to peel off from the chip, leading to failure of the ultrasonic wire bonding process.

Another known solution (US Patent US10347566B2) involves sintering a thick copper plate on top of the chip (Cu clip bonding) and then directly connecting this thick copper plate to a copper bonding pad on top of the ceramic substrate using silver sintering. However, the inventors of this invention have found that the height of the thick copper plate in this interconnection method is difficult to control, which can easily cause gaps in the connection or even failure to connect. Furthermore, the difference in the coefficients of thermal expansion between the thick copper plate, the chip, and the ceramic substrate can generate extremely high thermal stress, leading to cracking of the power chip and interconnects, and even damage to the entire power module.

Another known solution is to sinter a copper plate onto the pad surface of the power IC chip using silver sintering to block the external load of ultrasonic wire bonding. However, the inventors of this invention have discovered that silver sintering requires a temperature above 250°C. Therefore, during the silver sintering process, the difference in the coefficients of thermal expansion between the copper plate and the chip generates extremely high thermal stress, causing the power IC chip to... Damage to the sintered silver paste, coupled with its numerous pores, reduces the overall conductivity and thermal conductivity of the power module. In particular, aluminum pad breakage of the chip is the most common failure mode. Furthermore, the numerous pores in the sintered silver paste reduce conductivity, thermal conductivity, and bonding strength. Especially near the chip, the numerous pores in the sintered layer connect to form cracks, easily leading to delamination of the bonding interface. The purpose of this disclosure is to provide a packaging structure and its manufacturing method to solve at least one of the above problems.

To this end, this disclosure provides a packaging structure with a nano-twinned (NT) structure and its manufacturing method. Due to the excellent atomic diffusion capability of the nano-twinned structure surface, the wafer and metal foil can be sintered and bonded at low temperatures, avoiding wafer damage caused by extremely high thermal stress. Furthermore, low-temperature sintering reduces the porosity of the sintered layer and increases its strength, thereby improving the electrical and thermal conductivity of the sintered layer, as well as the bonding strength between the wafer and the metal foil. Alternatively, it can prevent these pores from forming cracks that lead to sintered layer peeling. Moreover, the high hardness of the nano-twinned structure can withstand the load during ultrasonic wire bonding to prevent wafer breakage.

Figures 1 through 4 are cross-sectional views illustrating the formation of the packaging structure 100 at different process stages, based on some embodiments disclosed herein.

Referring to Figure 1, a chip 102 is provided. In some embodiments, chip 102 may include a power integrated circuit (IC) chip, but this disclosure is not limited thereto. In other embodiments, chip 102 is a chip for other purposes, such as a driver IC chip or a control IC chip. The power IC chip may include a silicon chip, a silicon carbide chip, or a gallium nitride chip, but this disclosure is not limited thereto.

In some embodiments, the wafer 102 may include a solder pad 1021 disposed on the surface 102F of the wafer 102, and a dielectric layer 1022 disposed on the same layer as the solder pad 1021. For example, the solder pad 1021 and the dielectric layer 1022 are part of a redistribution layer (RDL) in the wafer 102, the solder pad 1021 is formed in the topmost dielectric layer 1022, and the surface of the solder pad 1021 is substantially coplanar (e.g., flush) with the dielectric layer 1022. In some embodiments, the solder pad 1021 may include or be made of aluminum, copper, or other suitable metal materials. The dielectric layer 1022 may include or be silicon dioxide, polyimide or other suitable dielectric materials.

Referring again to Figure 1, a first metal thin film 106 with a nanocrystalline structure is formed above the wafer 102. The nanocrystalline structure has parallel grain boundaries with a spacing of 1 nanometer to 50 nanometers (e.g., 2 to 10 nanometers). Generally, the smaller the spacing of the parallel grain boundaries, the higher the hardness of the first metal thin film 106. In the cross-sectional metallographic image of the first metal thin film 106, the parallel grain boundaries account for more than 50% (e.g., more than 60%, 70%, 80%, or 90%) of the total grain boundaries. It should be noted that the nanocrystalline structure of the first metal film 106 can be uniformly or steppedly distributed in the first metal film 106, or the nanocrystalline structure can be concentrated in the region of the first metal film 106 adjacent to the sintering layer 108 (shown in Figure 2) to be formed later, while the remaining portion is still a random grain, the thickness of which accounts for 10% to 100% of the total thickness of the first metal film 106. The nanocrystalline structure located at the interface between the first metal film 106 and the sintering layer 108 (shown in Figure 2) to be formed later has a high atomic diffusion capability with a high density (111) crystal orientation, thus facilitating low-temperature bonding between the first metal film 106 and the sintering layer 108.

The formation of twin structures is due to the accumulation of strain energy within the material, which drives atoms in certain regions to uniformly shear to lattice positions that are mirror-symmetrical with the unsheared atoms within the grain. Twins include annealing twins, mechanical twins, and nano-twins. The mutually symmetrical interface between them is called a twin boundary.

Twins mainly occur in face-centered cubic (FCC) or hexagonal closed-packed (HCP) crystalline materials with the tightest lattice arrangement. In addition to the tightest lattice arrangement, materials with lower stacking fault energy are generally more prone to twin formation. The nano-twin of this invention is characterized by the parallel stacking of most nanometer-thick twin grains, and the twin interfaces of each twin grain have a (111) crystal orientation.

Twin grain boundaries exhibit a coherent crystalline structure, belonging to the low-energy Σ3 and Σ9 special grain boundaries. Their crystal orientation is the {111} plane. Compared to high-angle grain boundaries formed by typical annealing and recrystallization, the interfacial energy of twin grain boundaries is approximately 5% of that of typical high-angle grain boundaries. Due to the lower interfacial energy of twin grain boundaries, they avoid becoming pathways for oxidation, sulfidation, and chloride ion corrosion. Therefore, they exhibit better oxidation and corrosion resistance. Furthermore, the symmetrical lattice arrangement of these twin grains provides less obstruction to electron transport, resulting in better electrical and thermal conductivity. Because twin grain boundaries impede differential packing movement, the material maintains high strength. This combination of high strength and high conductivity has been proven in copper thin films.

Regarding high-temperature stability, due to the lower interfacial energy of twin grain boundaries, they are more stable than typical high-angle grain boundaries. Twin grain boundaries themselves are not easily moved at high temperatures and also exert a locking effect on the high-angle grain boundaries surrounding them, preventing these high-angle grain boundaries from moving. Therefore, the overall grain structure does not exhibit significant grain growth at high temperatures, thus maintaining the material's high-temperature strength. Regarding the reliability of current carrying, the diffusion rate of atoms through or across low-energy twin grain boundaries is lower. When using electronic products, the movement of atoms within the wire accompanied by high-density current is also more difficult. This solves the electromigration problem that often occurs in wires when current is carried. Reports have confirmed that twin crystals can suppress electromigration in copper thin films.

The characteristics of the nanotwin structure offer numerous advantages to the packaging structure 100. For example, due to the excellent atomic diffusion capability of the nanotwin structure surface, the wafer 102 can be subsequently sintered and bonded to the metal foil 110 at low temperatures (illustrated in Figure 2). Furthermore, low-temperature sintering reduces the porosity of the sintered layer 108 and increases its strength. Moreover, the high hardness of the nanotwin structure prevents the wafer 102 from cracking during subsequent ultrasonic wire bonding (illustrated in Figure 4). This will be explained in detail later with reference to Figures 2 and 4.

In some embodiments, the first metal film 106 may include or be silver, copper, or a silver-copper alloy. The thickness of the first metal film 106 is from 0.5 micrometers to 20 micrometers (e.g., 1 micrometer, 4 micrometers, 8 micrometers, 15 micrometers, or 10 micrometers). If the thickness of the first metal film 106 is less than 0.5 micrometers, it cannot effectively block the load during ultrasonic wire bonding to avoid the breakage of the wafer 102. When the thickness of the first metal film 106 is greater than 20 micrometers, the first metal film 106 can easily peel off from the wafer 102 (or the adhesive layer 104, if present), especially when cutting the wafer 102 covered by the first metal film 106, peeling of the first metal film 106 is more likely to occur. In addition, the production time for forming a thick first metal film 106 is too long and the cost is also high.

In some embodiments, the first metal thin film 106 can be formed by sputtering, evaporation, or electroplating. According to some embodiments, sputtering employs single-gun sputtering or multi-gun co-plating. The sputtering power source can be, for example, direct current (DC), DC pulse, radio frequency (RF), high-power impulse magnetron sputtering (HIPIMS), etc. The sputtering power of the first metal thin film 106 can be, for example, from about 100W to about 500W. The sputtering process temperature is room temperature, but the sputtering process temperature rises by about 50°C to about 200°C. The deposition rate of the first metal thin film 106 can be, for example, from about 0.5 nm/s to about 3 nm/s. The sputtering background pressure is less than 1 x ^10⁻⁵ torr, and the operating pressure can be, for example, from about 1 x ^10⁻³ torr to 1 x ^10⁻² torr. The argon flow rate is about 10 sccm to about 20 sccm. The stage speed can be, for example, from about 5 rpm to about 20 rpm. Preferably, a bias voltage of about -100V to about -500V (e.g., -150V or -300V) can be applied to the substrate during the sputtering process to form high-density nanocrystals. If the bias voltage is lower than -100V or higher than -500V, the nanocrystal density of the sputtered metal thin film will be less than 50%, and low-temperature sintering bonding cannot be achieved.

According to other embodiments, the first metal film 106 can be formed on the adhesive layer 104 by vapor deposition. In some embodiments, the background pressure of the vapor deposition process is less than 1 x ^10⁻⁵ torr, the operating pressure can be, for example, about 1 x ^10⁻⁴ torr to about 5 x ^10⁻⁴ torr, and the argon flow rate can be about 2 sccm to about 10 sccm. The stage speed can be, for example, about 5 rpm to about 20 rpm. The deposition rate of the first metal film 106 can be, for example, about 1 nm/s to about 5.0 nm/s. Preferably, during the evaporation process, ion bombardment can be applied to the first metal film 106 at a voltage of about 10V to about 300V (e.g., 100V or 200V) and a current of about 0.1A to about 1.0A (e.g., 0.3A or 0.8A) to form high-density nanocrystals. If the voltage of the ion bombardment is lower than 10V or higher than 300V, or the current is lower than 0.1A or higher than 1.0A, the nanocrystal density of the evaporated metal film will be less than 50%, and low-temperature sintering bonding will not be achieved.

According to some embodiments, the first metal film 106 can be formed by electroplating. Preferably, the electroplating solution is stirred simultaneously at a speed of 500 rpm to 3000 rpm (e.g., 1000 rpm or 2000 rpm) during the electroplating process to form high-density nanocrystals. If the speed of stirring the electroplating solution is lower than 500 rpm or higher than 3000 rpm, the nanocrystal density of the sputtered metal film will be less than 50%, and low-temperature sintering bonding effect cannot be achieved.

In some embodiments, an adhesion layer 104 may be optionally formed on the wafer 102 before the formation of the first metal thin film 106, and the first metal thin film 106 is formed on the adhesion layer 104. The adhesion layer 104 can provide better adhesion between the wafer 102 and the first metal thin film 106. Furthermore, the adhesion layer 104 has a lattice buffering effect; if the first metal thin film 106 is formed directly on the wafer 102, the nanocrystalline structure of the first metal thin film 106 may be affected by the crystal orientation of the wafer 102. The material of the adhesion layer 104 may include tungsten, titanium, chromium, the aforementioned alloys, or other suitable adhesive materials. The thickness of the adhesion layer 104 is from 0.1 micrometers to 0.9 micrometers. It should be understood that the thickness of the adhesive layer 104 can be appropriately adjusted according to the actual application, and this disclosure is not limited thereto. The adhesive layer 104 can be formed on the surface 102F of the wafer 102 by sputtering, evaporation or electroplating.

Referring to Figure 2, a bonding process 120 is performed to bond the metal foil 110 to the first metal film 106 via a sintering layer 108, with the first metal film 106 in direct contact with the sintering layer 108. In some embodiments, the sintering layer 108 is used to provide better adhesion between the first metal film 106 and the metal foil 110 to prevent the metal foil 110 from peeling off the surface of the first metal film 106. The sintering layer 108 may include silver, copper, or a silver-copper composite.

In some embodiments, the metal foil 110 is used to block or reduce the load on the wafer 102 during ultrasonic wire bonding of the interconnect conductors 112 (shown in Figure 4), thereby preventing the wafer 102 from cracking. The metal foil 110 may include or be silver, copper, or a silver-copper alloy. The thickness of the metal foil 110 is greater than 20 micrometers (e.g., greater than 100 micrometers). It should be understood that the thickness of the metal foil 110 can be appropriately adjusted according to the actual application, and this disclosure is not limited thereto, as long as the metal foil 110 does not deform significantly during the sintering bonding process to the point of affecting subsequent processes.

In some embodiments, the bonding process 120 may include first applying a sintering material (not shown) to a first metal film 106, and then bonding the metal foil 110 to the sintering material. The sintering material may be a sintering paste comprising silver or copper powder, or a sintered preform formed by sintering silver or copper powder. Specifically, the sintering paste is composed of silver or copper powder and additives (such as flux and adhesive), while the sintered preform is formed by sintering silver or copper powder using a powder sintering method. Next, the bonding process 120 between the metal foil 110 and the wafer 102 is performed. The bonding process 120 includes sintering the sintering material to form a sintered layer 108.

In some embodiments, the sintering process can be performed under vacuum or atmosphere. The sintering process can be performed continuously at a temperature of 150°C to 240°C for 5 to 60 minutes. If the temperature is below 150°C, the sintering reaction may be incomplete, while if the temperature is above 240°C, the resulting thermal stress may damage the wafer 102 and crack the metal foil 110. Sintering bonding can be completed within the above-mentioned time; prolonged heating (e.g., for more than 60 minutes) may damage the wafer 102. In addition, the sintering process may include applying a compressive stress of 0 to 30 MPa to the package structure 100, which helps to improve the bonding effect.

The packaging structure 100 disclosed herein has a first metal thin film 106 (including a nano-twin structure). Due to the high atomic diffusion capability of the high-density (111) crystal orientation on the surface of the nano-twin structure, the wafer 102 and the metal foil 110 can be sintered and bonded through the sintering layer 108 at a low temperature below 240°C to avoid damage to the wafer 102 caused by extremely high thermal stress. This thermal stress is caused by the difference in the coefficients of thermal expansion between the metal foil 110 and the wafer 102. Furthermore, since the sintering process can be completed at a low temperature below 240°C, the porosity of the sintered layer 108 can be less than 10% (e.g., less than 3%) after sintering is completed, and its strength is improved. In this way, the electrical conductivity, thermal conductivity, and bonding strength between the wafer 102 and the metal foil 110 of the sintered layer 108 can be improved, or the pores can be prevented from connecting into cracks, which would cause the sintered layer 108 to crack or peel off. Unless otherwise defined, the term "porosity" refers to the ratio of the total cross-sectional area of the pores to the cross-sectional area of the sintered layer 108, which is a value calculated by image analysis using commercial software (such as Fiji ImageJ) based on cross-sectional images obtained using scanning electron microscopy (SEM).

Referring to Figure 3, after completing bonding process 120, the metal foil 110, sintering layer 108, first metal film 106, and adhesive layer 104 (if present) are patterned to expose a portion of the surface 102F of the wafer 102. In embodiments where a dielectric layer 1022 is present, the patterning exposes the dielectric layer 1022. In some embodiments, the patterning process may include photolithography and etching processes. For example, a photoresist pattern (e.g., consistent with the pattern of the solder pad 1021) is first defined on the unpatterned metal foil 110, and then the metal foil 110, sintering layer 108, first metal film 106, and adhesive layer 104 (if present) are etched using this photoresist pattern as a mask. In some embodiments, the lithography process may include photoresist coating (e.g., rotational coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying, but this disclosure is not limited thereto. The etching process may include dry etching, wet etching, reactive ion etching (RIE), ashing, and/or other etching methods, but this disclosure is not limited thereto.

Figure 4 is a partial cross-sectional view of the package structure 100 according to some embodiments of this disclosure. In some embodiments, the chip 102 is disposed on a substrate 302 having copper pads 304a and 304b. The copper pads 304a and 304b are spaced apart from each other. For simplicity, only one copper pad 304a is shown on the substrate 302 in the figure, but this disclosure is not limited thereto. In other embodiments, the substrate 302 may also have a plurality of spaced copper pads 304a corresponding to the number of chips 102. For simplicity, the copper pads 304a and 304b are sometimes collectively referred to as copper pads 304.

In some embodiments, the substrate 302 may include a printed circuit board or a ceramic substrate. The ceramic substrate may comprise aluminum oxide ( _Al₂O₃ ) _, aluminum nitride (AlN), or silicon nitride ( _Si₃N₄ ). In some embodiments, the copper solder pad 304 is part of a patterned circuit design and _is disposed on the surface of the substrate 302. In some embodiments, the copper solder pad 304 comprises or is made of copper. The copper solder pad 304 is disposed on the substrate 302 using direct bonded copper (DBC), direct plated copper (DPC), or active metal brazing (AMB). The thickness of the copper solder pad 304 is from 0.5 mm to 1 mm, for example, 0.635 mm.

In some embodiments, a protective film (not shown) may be included above the copper solder pad 304, to which the wafer 102 is bonded. The protective film serves to prevent the copper solder pad 304 from oxidizing or corroding upon contact with air in a normal environment. The protective layer may include or be an organic solderability preservative (OSP) or a thin metal film. The thin metal film may include or be nickel (Ni), nickel/gold (Ni/Au), or nickel/palladium/gold (Ni/Pd/Au). The thickness of the protective film ranges from 0.1 micrometers to 100 micrometers.

Referring again to Figure 4, in some embodiments, the wafer 102 is bonded to the substrate 302, for example, the wafer 102 is bonded to the copper solder pad 304a (or protective film, if present) of the substrate 302. The wafer 102 may be bonded to the copper solder pad 304a of the substrate 302 by die bonding methods such as eutectic bonding, adhesive bonding, solder bonding or sintering bonding, but this disclosure is not limited thereto.

Next, the interconnect conductor 112 is bonded to the metal foil 110 using ultrasonic wire bonding, thereby electrically connecting the interconnect conductor 112 to the chip 102. In some embodiments, the interconnect conductor 112 is used to provide signal and power transmission between the chip 102 and the substrate 302, and may also serve a heat dissipation function. The interconnect conductor 112 is selected from the following family: coarse aluminum wire, coarse aluminum ribbon, coarse copper wire, coarse copper ribbon, aluminized coarse copper wire, aluminized coarse copper ribbon, silver alloy coarse wire, and silver alloy coarse ribbon. Unless otherwise defined, the term "thick strip" refers to a continuous long strip of material that is generally flat, with a thickness of 10 to 500 micrometers and a width that is 2 to 200 times the thickness but usually no more than 5 millimeters (mm). The term "thick wire" refers to a continuous long wire with a circular cross-section that is generally 100 micrometers or more in diameter, much larger than the thin wires (with a diameter of less than 25.4 micrometers) used in the thermoforming of ICs or light-emitting diodes (LEDs).

In some embodiments, one end 1121 of the interconnect conductor 112 is electrically and physically connected to the chip 102 via the metal foil 110, while the other end 1122 is electrically and physically connected to the substrate 302 via the copper solder pad 304b. In this way, the chip 102 can be electrically connected to the substrate 302 via the first metal film 106, the metal foil 110, the interconnect conductor 112, and the copper solder pad 304b. Specifically, one end 1121 of the interconnect conductor material is first ultrasonically wire-bonded to the metal foil 110 to form a first solder point A, and then the other end 1122 of the interconnect conductor material is ultrasonically wire-bonded to the copper solder pad 304b to form a second solder point B. After forming the second solder point B, the interconnect conductor material can be cut to form an interconnect conductor 112 with the first solder point A and the second solder point B. Using ultrasonic wire bonding for interconnection can avoid the generation of joint gaps or non-joining problems, making the package structure 100 highly reliable.

In some embodiments, ultrasonic wire bonding is performed under process conditions of 50 to 300 milliwatts (mW), a bonding time of 100 to 150 millisieverts (ms), a contact load of 100 to 800 millinewtons (cN) (e.g., 200 to 600 millinewtons), and a bonding load of 200 to 1000 millinewtons (e.g., 300 to 800 millinewtons) to form a first solder joint A and a second solder joint B, respectively. In some embodiments disclosed herein, unless specifically defined, the term "load" refers to the intensity applied to the solder joint (e.g., the first solder joint A and the second solder joint B) during the ultrasonic wire bonding process. It is worth noting that in this embodiment of the invention, the metal foil 110 and the first metal film 106 with high hardness block or reduce the load on the wafer 102 when the interconnect conductor 112 is ultrasonically wire bonded, so the wafer 102 does not crack.

As shown in Figure 4, the package structure 100 disclosed herein includes a wafer 102, a first metal thin film 106 disposed above the wafer 102 and having a nanocrystalline structure, a sintering layer 108 disposed on and in direct contact with the first metal thin film 106, a metal foil 110 disposed on the sintering layer 108, and an interconnect conductor 112 disposed on the metal foil 110 and electrically connected to the wafer 102.

It should be understood that after ultrasonic wire bonding is completed, subsequent packaging processes can be carried out as needed to complete the packaging structure 100. Since this is not the focus of this disclosure, it will not be elaborated here.

Figures 5 and 6 are cross-sectional views illustrating the formation of the package structure 200 at different process stages according to other embodiments of this disclosure. It should be noted that processes or components identical or similar to those in the foregoing embodiments will use the same component symbols, and their details will not be repeated. In this embodiment, the package structure 200 also includes a second metal film 206 located between the sintered layer 108 and the metal foil 110.

Figure 5 follows the steps in Figure 1, and the packaging structure 200 in Figure 5 is similar to the packaging structure 100 in Figure 2. The difference is that before performing the bonding process 120, a second metal film 206 is formed on the surface 110S of the metal foil 110 facing the wafer 102, and the second metal film 206 has a nanocrystalline structure. The structure, material, thickness, and formation method of the second metal film 206 and its nanocrystalline structure can be referred to the first metal film 106 and its nanocrystalline structure described in Figure 1, and will not be elaborated here for the sake of simplicity. Subsequently, the bonding process 120 is performed.

Referring to Figure 6, a patterned metal foil 110, a second metal film 206, a sintering layer 108, a first metal film 106, and an adhesive layer 104 (if present) are arranged to expose a portion of the surface 102F of the wafer 102. The patterning process can be referred to the patterning process described in Figure 3, and will not be elaborated here for the sake of simplicity.

Figure 7 is a cross-sectional schematic diagram of the package structure 200 according to other embodiments of this disclosure. The wafer 102 is bonded to the substrate 302 and ultrasonic wire bonding is performed; the remaining process details are as previously described and will not be repeated here. In some embodiments, the package structure 200 in Figure 7 is similar to the package structure 100 in Figure 4, except that the package structure 200 further includes a second metal film 206 disposed between the sintering layer 108 and the metal foil 110. The second metal film 206, having a nanocrystalline structure, can further prevent the wafer 102 from cracking during ultrasonic wire bonding.

The following describes some experimental examples of the packaging structures disclosed herein, as well as the test results of comparative examples.

Experimental examples 1 : SiC/Cr/nt-Ag/Ag/Cu Structure

The SiC/Cr/nt-Ag/Ag/Cu structure is an example of the packaging structure 100 in Figure 2. Specifically, chromium (adhesive layer 104) and a nano-twinned silver nanoparticle (nt) (first metal film 106) are sequentially sputtered over silicon carbide (wafer 102). Then, copper (metal foil 110) is bonded to the nano-twinned silver nanoparticle (first metal film 106) using silver paste (sintering material).

Comparative example 1 : SiC/Cr/Ni/Ag/Ag/Cu Structure

SiC/Cr/Ni/Ag/Ag/Cu is an example of a packaging structure known to the inventors. Specifically, a chromium adhesion layer, a nickel diffusion barrier layer, and a silver metal layer (with an equiaxed coarse-grained structure) are sequentially sputtered over a silicon carbide wafer. Then, copper (metal foil) is bonded to the silver metal layer using silver paste (sintering material). In other words, the silver nanocrystals (first metal film 106) in Experimental Example 1 are replaced by a nickel diffusion barrier layer and a silver metal layer (without a nanocrystal structure). It should be noted that since the structure of Experimental Example 1 has silver nanocrystals (first metal film 106), it facilitates the low-temperature bonding process and avoids unwanted diffusion caused by high temperature. Therefore, no diffusion barrier layer is needed between chromium (adhesive layer 104) and silver nanocrystals (first metal film 106).

[ Porosity and bonding strength measurement ]

After bonding was completed, a compressive stress of 10 MPa was applied to the structures of Comparative Example 1 and Experimental Example 1, respectively, and sintering was performed at sintering temperatures of 150°C, 180°C, and 225°C for 60 minutes each to complete sintering (i.e., the sintered material formed a sintered layer). Next, the cross-sectional images of the structures of Comparative Example 1 and Experimental Example 1 were obtained using scanning electron microscopy (SEM), and the porosity was calculated using Fiji ImageJ software. The bond strength (or shear strength) was measured using a DAGE 4000 weld strength tester manufactured by Nordson. The results are shown in Tables 1 and 2, respectively.

[Table 1] Porosity of sintered layer (%) Connection temperature 150°C 180°C 225°C Comparative example 1 18 10 6 Experimental Example 1 8 4 3

[Table 2] Bond strength (MPa) Connection temperature 150°C 180°C 225°C Comparative example 1 10 twenty one 32 Experimental Example 1 32 38 44

According to Tables 1 and 2, it can be confirmed that Experimental Example 1 (with a nano-twin structure) exhibited lower sintered layer porosity and higher bond strength compared to Comparative Example 1 (without a nano-twin structure) under various bonding temperatures (e.g., 150°C, 180°C, and 225°C). In other words, under various bonding temperature conditions, the encapsulation structure with a nano-twin layer exhibited better sintered layer porosity and bond strength compared to the encapsulation structure with an equiaxed coarse-grained layer. Furthermore, after sintering, the porosity of the sintered layer in Experimental Example 1 was less than 10% (3% to 8%).

Experimental examples -2 : SiC/Ti/nt-AgCu/Ag/Cu Structure

Figure 8 is a cross-sectional view of a silicon carbide (SiC)/titanium (Ti)/silver-copper nanotwin (nt-AgCu)/silver (Ag) sintered layer/copper (Cu) foil structure obtained using scanning electron microscopy, based on an experimental example disclosed herein. The SiC/Ti/nt-AgCu/Ag/Cu structure is an example of the packaging structure 100 in Figure 2. Specifically, a titanium layer (adhesive layer 104) with a thickness of 0.2 micrometers and a silver-copper nanotwin (first metal film 106) having an Ag-8.2%Cu nanotwin (nt) structure are sequentially sputtered on top of silicon carbide (wafer 102). Next, copper (metal foil 110) with thicknesses of 20 μm, 40 μm, 60 μm (as shown in Figure 8), 80 μm, and 100 μm, respectively, is bonded to the silver-copper nanocrystal (first metal film 106) using silver paste (sintering material). Then, a compressive stress of 15 MPa is applied to the above structure and sintering is carried out at a sintering temperature of 150°C for 10 minutes to complete sintering (that is, the sintering material is formed into a sintered layer 108).

[ Porosity and bonding strength measurement ]

After sintering, the cross-sectional images of each structure in Experiment 2 were obtained using scanning electron microscopy (SEM). The porosity was calculated using Fiji ImageJ software, and the bond strength (or shear strength) was measured using a Nordson DAGE 4000 weld strength tester. The results are shown in Table 3.

[Table 3] Metal foil thickness (micrometers) Porosity of sintered layer (%) Bond strength (MPa) 20 2.1 26.1 40 1.6 38.6 60 1.3 48.3 80 1.9 29.2 100 1.4 35.5

According to Table 3, it can be confirmed that as long as the encapsulation structure 100 has a nano-twin crystal structure (first metal film 106), regardless of the thickness of the copper foil (metal foil 110), after sintering, the porosity of the silver sintered layer (sintered layer 108) is less than 10% (1.3 to 2.1%), and the bonding strength can reach 26.1 to 48.3 MPa.

[ Nanocrystalline structure analysis ]

Figure 9 is a partial cross-sectional metallographic image of the structure in the aforementioned Experimental Example-2, obtained using a focused ion beam (FIB) according to an experimental example disclosed herein. In Figure 9, it can be clearly seen that the first metallic film, AgCu, possesses a nanocrystalline structure. This nanocrystalline structure has parallel-aligned grain boundaries, with a spacing of approximately 15 nanometers between them, and these parallel-aligned grain boundaries account for approximately 92% of the total grain boundaries.

[ Ultrasonic wire bonding performance test ]

The aforementioned Experimental Example-2 structure was ultrasonically wire-bonded using thick copper wires (interconnect conductors 112) with a diameter of 380 micrometers and a bonding load (BL) of 2040 to 3059 grams, respectively. The copper (metal foil 110) thicknesses were 20 micrometers, 40 micrometers, 60 micrometers, 80 micrometers, and 100 micrometers (as shown in the photograph in Figure 10). During ultrasonic wire bonding, a contact load of 600 millinewtons (cN), a bonding load of 200 to 800 millinewtons, and a bonding power of 85.5 milliwatts (mW) were applied for a bonding time of 150 milliseconds. After ultrasonic wire bonding, the wafer 102 was visually observed for cracking. Furthermore, the bond strength of the Experimental Example-2 structure with a copper (metal foil 110) thickness of 100 micrometers was further measured using a DAGE 4000 weld strength tester manufactured by Nordson, and the results are shown in Table 4. It should be noted that items not measured are indicated by the symbol "-".

[Table 4] Copper foil thickness (micrometers) Whether the chip is broken or not Joint thrust (grams) 20 Partial rupture 831 40 Unbroken 1320 60 Unbroken 1584 80 Unbroken 1692 100 Unbroken 1845

Table 4 confirms that when the copper (metal foil 110) thickness is 20 micrometers, the thickness is insufficient to effectively block or reduce the load on the wafer 102 from the thick copper wire (interconnect conductor 112), resulting in partial breakage of the wafer 102 after ultrasonic wire bonding. However, when the copper thickness is greater than or equal to 40 micrometers, no wafer 102 breaks after ultrasonic wire bonding, and the structure in Experimental Example-2 with a copper (metal foil 110) thickness of 100 micrometers exhibits high bonding thrust.

Furthermore, if the nano-twin crystal structure in the above-mentioned Experimental Example-2 structure is replaced with an equiaxed coarse-grained thin film, the silver sintering layer is prone to cracking or peeling during ultrasonic wire bonding performance testing, regardless of the thickness of the copper foil, which is between 20 and 100 micrometers, resulting in the detachment of the coarse copper wire.

In summary, some embodiments of this disclosure offer several advantages. This disclosure provides a packaging structure with a nano-twin crystal structure and a method for manufacturing the same. Due to the excellent atomic diffusion capability of the nano-twin crystal surface, the wafer and metal foil can be sintered and bonded at low temperatures, avoiding wafer damage caused by extremely high thermal stress. Furthermore, low-temperature sintering reduces the porosity of the sintered layer and increases its strength, thereby improving the electrical and thermal conductivity of the sintered layer, as well as the bonding strength between the wafer and the metal foil. Alternatively, it can prevent these pores from coalescing into cracks that lead to sintered layer peeling. Moreover, the high hardness of the nano-twin crystal structure can prevent wafer breakage during ultrasonic wire bonding.

The above outlines the components of several embodiments to facilitate a better understanding of the viewpoints of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

100: Package Structure 102: Chip 102F: Surface 1021: Solder Pad 1022: Dielectric Layer 104: Adhesion Layer 106: First Metal Thin Film 108: Sintering Layer 110: Metal Foil 110S: Surface 112: Interconnect Conductor 1121, 1122: Terminals 120: Bonding Process 200: Package Structure 206: Second Metal Thin Film 302: Carrier 304, 304a, 304b: Copper Solder Pads A, B: Solder Joints

The various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, according to industry standard practice, the components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the invention. It should also be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting its scope; this disclosure is equally applicable to other embodiments. Figures 1 through 3 are cross-sectional views illustrating the formation of the package structure at different process stages according to some embodiments of this disclosure. Figure 4 is a partial cross-sectional view illustrating the package structure according to some embodiments of this disclosure. Figures 5 and 6 are cross-sectional views illustrating the formation of the package structure at different process stages according to other embodiments of this disclosure. Figure 7 is a partial cross-sectional view of a packaging structure according to other embodiments of this disclosure. Figure 8 is a cross-sectional view of an experimental structure obtained using a scanning electron microscope according to an example of this disclosure. Figure 9 is a partial cross-sectional metallographic image of an experimental structure obtained using a focused ion beam microscope according to an example of this disclosure. Figure 10 is a photograph of a packaging structure according to an example of this disclosure.

100: Packaging Structure

102: Chip

1021: Welding Pad

1022: Dielectric layer

104: Adhesive layer

106: First Metal Thin Film

108: Sintered Layer

110: Metal Foil

112: Interconnect conductor

1121, 1122: End

302: Carrier Board

304, 304a, 304b: Copper welding pads

A, B: Soldering points

Claims (23)

A packaging structure includes: a wafer, comprising: a solder pad disposed on a surface of the wafer, wherein the solder pad comprises aluminum or copper; and a dielectric layer disposed on the same layer as the solder pad, wherein the dielectric layer comprises silicon dioxide or polyimide; a first metal film disposed above the wafer, wherein the first metal film has a first nanocrystalline structure; a sintering layer disposed on the first metal film and in direct contact with the first metal film; a metal foil disposed on the sintering layer; and an interconnect conductor disposed on the metal foil and electrically connected to the wafer. The packaging structure as described in claim 1, wherein the first metal film comprises silver, copper, or a silver-copper alloy. The packaging structure as described in claim 1, wherein the thickness of the first metal film is from 0.5 micrometers to 20 micrometers. The packaging structure as described in claim 1, wherein the first nanocrystalline structure has a parallel arrangement of grain boundaries with a spacing of 1 nanometer to 50 nanometers, and in a cross-sectional metallographic image of the first metal film, the parallel arrangement of grain boundaries accounts for more than 50% of the total grain boundaries. The packaging structure as described in claim 1, wherein the porosity of the sintered layer is less than 10%. The packaging structure as described in claim 1, wherein the chip includes a power integrated circuit chip, and the power integrated circuit chip includes a silicon chip, a silicon carbide chip, or a gallium nitride chip. The packaging structure as described in claim 1 further includes an adhesive layer located between the first metal film and the wafer, and the adhesive layer includes tungsten, titanium, chromium or an alloy thereof, and the thickness of the adhesive layer is from 0.1 micrometer to 0.9 micrometer. The packaging structure as described in claim 1, wherein the sintered layer comprises silver, copper, or a silver-copper composite. The packaging structure as described in claim 1, wherein the metal foil comprises silver, copper, or a silver-copper alloy, and the thickness of the metal foil is greater than 20 micrometers. The packaging structure as described in claim 1, wherein the interconnect conductor system is selected from the group consisting of: aluminum wire, aluminum strip, copper wire, copper strip, aluminized copper wire, aluminized copper strip, silver alloy wire, and silver alloy strip. The packaging structure as described in claim 1 further includes a second metal film disposed between the sintered layer and the metal foil, wherein the second metal film has a second nanocrystalline structure. The packaging structure as described in claim 1 further includes a substrate located beneath the wafer and having a copper solder pad, wherein one end of the interconnect conductor is electrically connected to the wafer via the metal foil, and the other end is electrically connected to the substrate via the copper solder pad. A method for manufacturing a packaging structure includes: providing a wafer, wherein the wafer includes: a solder pad disposed on a surface of the wafer, wherein the solder pad includes aluminum or copper; and a dielectric layer disposed co-layered with the solder pad, wherein the dielectric layer includes silicon dioxide or polyimide; forming a first metal film above the wafer, wherein the first metal film has a first nanocrystalline structure; performing a bonding process to bond a metal foil to the first metal film through a sintering layer, wherein the first metal film is in direct contact with the sintering layer; and bonding an interconnect conductor to the metal foil using an ultrasonic wire bonding method, wherein the interconnect conductor is electrically connected to the wafer. A method for manufacturing a packaging structure as described in claim 13, wherein the first metal film is formed by sputtering, vapor deposition or electroplating. The method of manufacturing the packaging structure as described in claim 13, wherein performing the bonding process includes: firstly, disposing a sintering material on the first metal film; and bonding the metal foil to the sintering material, and performing a sintering process to form the sintering material as the sintering layer. The method of manufacturing the packaging structure as described in claim 15, wherein the sintering material is a sintering paste comprising silver powder or copper powder, or a sintered preform formed by sintering silver powder or copper powder. The method of manufacturing the packaging structure as described in claim 15, wherein the sintering process is performed continuously for 5 to 60 minutes at a temperature of 150°C to 240°C. A method for manufacturing a packaging structure as described in claim 15, wherein the sintering process includes applying a compressive stress of 0 to 30 MPa to the packaging structure. A method for manufacturing a packaging structure as described in claim 15, wherein the sintering process is performed in a vacuum or atmosphere. The method of manufacturing a package structure as described in claim 13 further includes patterning the metal foil, the sintering layer, and the first metal film to expose a portion of the surface of the wafer before bonding the interconnect conductor to the metal foil. A method of manufacturing a package structure as described in claim 20, wherein the patterning exposes the dielectric layer. The method of manufacturing the packaging structure as described in claim 13 further includes forming a second metal film on the surface of the metal foil facing the wafer before performing the bonding process, wherein the second metal film has a second nanocrystalline structure. The method of manufacturing a package structure as described in claim 13, wherein the interconnect conductor is electrically connected to the metal foil above the chip by ultrasonic vibration.