TWI910861B - Package structure and method of manufacturing the same - Google Patents

Abstract

A package structure includes a carrier having a carrier pad; a chip, disposed over the carrier, having a chip pad; and a metal pressure-resistant layer having a nano-twinned structure disposed over the chip bond pad. The metal pressure-resistant layer is electrically connected to the carrier pad. The nano-twinned structure is evenly distributed within the metal pressure-resistant layer, or the nano-twinned structure is concentrated in an upper region of the metal pressure-resistant layer in a stepped or floating manner and distribution of crystal orientation in another region of the metal pressure-resistant layer is disorderly.

Description

Packaging structure and manufacturing method

This invention relates to packaging technology, and in particular to a packaging structure having a metal compression-resistant layer and a method for manufacturing the same.

The inverter in the motor control unit of an electric vehicle is the most important key component for converting electrical energy into kinetic energy. The most important part affecting the power conversion efficiency is the power electronic module. The voltage/current specifications of automotive motor power module components reach 600V/450A, which is much higher than that of general power modules and consumer integrated circuits (ICs). They also need to pass various reliability tests of automotive-grade AEC-Q101. Therefore, the threshold for their packaging technology and materials is extremely high.

Power module packaging involves bonding a surface-metallized substrate to a metal heat dissipation base plate, then fixing the power IC chip onto the substrate, a process known as die bonding. Next, interconnection is performed between the solder pads on the power IC chip and the solder pads on the substrate. Conventional interconnection technology uses thick aluminum wire or strip with a diameter of 200 micrometers (μm) or more for ultrasonic wire bonding to connect the thick aluminum wire or strip to the solder pads on the power IC chip. However, the melting point of thick aluminum wire or strip is relatively low (e.g., below 700°C), which is insufficient to meet the requirements of power modules with higher current and higher voltage.

In recent years, the packaging industry has begun to experiment with using thick copper wire or strip, or thick silver wire or strip. These materials not only have better electrical and thermal conductivity than thick aluminum wire or strip, but also superior strength and reliability. However, the hardness of thick copper wire, copper strip, thick silver wire, and silver strip is much higher than that of thick aluminum wire or strip, which often causes power IC chips to crack during ultrasonic wire bonding, a problem that urgently needs to be solved in power module packaging.

One embodiment of this disclosure relates to a packaging structure including a carrier substrate, a wafer, and a metal pressure resist layer. The carrier substrate has carrier pads. The wafer is disposed above the carrier substrate and has wafer pads. The metal pressure resist layer is disposed above the wafer pads and has a nano-twinned (NT) structure. The metal pressure resist layer is electrically connected to the carrier pads. The nano-twinned structure is uniformly distributed within the metal pressure resist layer, or the nano-twinned structure is concentrated in the upper region of the metal pressure resist layer in a stepped or floating manner, and the remaining regions of the metal pressure resist layer are composed of disordered grains.

Another aspect of this disclosure relates to a method for manufacturing a packaging structure, comprising the following steps: providing a wafer having a wafer pad; forming a metal compression layer having a nanocrystalline structure above the wafer pad, wherein the nanocrystalline structure is uniformly distributed within the nanocrystalline structure, or the nanocrystalline structure is concentrated in a stepped or floating manner in the upper region of the metal compression layer and the remaining region of the metal compression layer is composed of disordered grains; providing a carrier plate having a substrate pad; bonding the wafer to the carrier plate; and electrically connecting the metal compression layer and the substrate pad.

The following disclosure provides numerous embodiments or examples for implementing different elements of the provided object. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For instance, if the description mentions that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where additional elements are formed between the first and second elements so that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference numerals and/or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and/or configurations discussed.

The following describes some variations of the embodiments. In embodiments with different diagrams and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or deleted in other embodiments of the method.

Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

The terminology used herein is for the purpose of illustrating specific embodiments only and is not intended to limit the concepts of the invention. Unless an expression has a clearly distinct meaning in the context, the singular form of an expression also encompasses the plural form. In this specification, it should be understood that terms such as “comprising,” “having,” and “including” are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may be present or added.

The following describes some embodiments of the present invention, in which additional steps may be provided before, during, and/or after the multiple stages described in these embodiments. Some of the said stages may be substituted or omitted in different embodiments. The packaging structure may add additional components. Some of the said components may be substituted or omitted in different embodiments. Although some of the embodiments discussed are performed in a particular order, these steps may still be performed in another logically sound order.

The use of thick copper wire, copper strip, thick silver wire, and silver strip for ultrasonic wire bonding often results in the breakage of power IC chips. One solution is to sinter a copper plate with silver onto the solder pad surface of the power IC chip to block the external load of the ultrasonic wire bonding. However, silver sintering requires a temperature above 250°C, which generates extremely high thermal stress during the process, causing damage to the power IC chip. Furthermore, the sintered silver paste contains a large number of pores, thus reducing the overall conductivity and thermal conductivity of the power module. In addition, the manufacturing cost is also higher.

Another solution is to plate a copper conductive layer with a thickness of nearly 10 micrometers onto the solder pad surface of the power IC chip to block the external load of ultrasonic wire bonding. However, the conventional copper conductive layer has a disordered grain arrangement and is relatively soft, so its stress-blocking effect is limited. Therefore, when using thick copper wire, copper strip, thick silver wire, or silver strip for ultrasonic wire bonding, a large load needs to be applied, and the power IC chip is still very easy to break. In particular, silicon carbide compound semiconductor chips are extremely brittle and more prone to breakage than ordinary silicon chips.

This disclosure provides a packaging structure with a metal pressure-resistant layer. The metal pressure-resistant layer disposed above the wafer, due to its nanocrystalline structure, can effectively enhance the atomic diffusion reaction of the metal wire or ribbon during ultrasonic wire bonding and accelerate the formation of the bonding interface. Therefore, it can reduce the load during ultrasonic wire bonding to prevent wafer breakage. Furthermore, the nanocrystalline structure has high hardness, which can further protect the underlying wafer from breakage when using thick copper wire, copper ribbon, thick silver wire, or silver ribbon for ultrasonic wire bonding. In particular, the atomic diffusion ability at the interface between the conventional disordered copper conductive layer and the interconnect conductor is poor, which affects the interface bonding effect. When using thick copper wire, copper strip, thick silver wire or silver strip for ultrasonic wire bonding, a larger load must be applied, which is also a major cause of wafer breakage.

Figures 1 through 4 are partial cross-sectional views illustrating the formation of the packaging structure 100 at different process stages, based on some embodiments disclosed herein.

Referring to Figure 1, a wafer 102 with a die pad 108 is provided. Specifically, the die pad 108 is located on one side of the crystal plane 102F of the wafer 102. In some embodiments, the die pad 108 is disposed on the same layer as a dielectric layer 110. For example, the die pad 108 and the dielectric layer 110 are part of a redistribution layer (RDL) in the wafer 102, the die pad 108 is formed in the topmost dielectric layer 110, and the surface of the die pad 108 is substantially coplanar (e.g., flush) with the dielectric layer 110. In some embodiments, the wafer 102 is not provided with a die pad 108.

In some embodiments, chip 102 may include a power integrated circuit (IC) chip, but this disclosure is not limited thereto. In other embodiments, chip 102 is a chip for other purposes, such as a driver IC chip or a control IC chip. In some embodiments, the power IC chip may include a first type of semiconductor material (e.g., silicon (Si) or germanium (Ge)), a third type of semiconductor material (e.g., silicon carbide (SiC) or gallium nitride (GaN)), or a fourth type of semiconductor material (e.g., _gallium oxide ( _Ga₂O₃ )).

In some embodiments, the chip bonding pad 108 may include or be an aluminum bonding pad or a copper bonding pad, and its surface may be plated with nickel, gold, palladium, the above-mentioned alloys, the above-mentioned stacked layers or other suitable metal materials as needed to help protect the copper pads from corrosion and/or join with other components. In some embodiments, the dielectric layer 110 may include or be silicon dioxide, silicon nitride, silicon oxynitride, polyimide, or other suitable dielectric materials.

In some embodiments, the wafer 102 may optionally include a back-chip adhesive layer 104 and a back-chip reactive layer 106 disposed on one side of the back-chip back 102B. The back-chip adhesive layer 104 is disposed between the wafer 102 and the back-chip reactive layer 106 to provide better adhesion between the wafer 102 and the back-chip reactive layer 106. In some embodiments, the material of the back-chip adhesive layer 104 may include titanium, chromium, tungsten titanium, or other combinations thereof, or other suitable adhesive materials. The thickness of the back-chip adhesive layer 104 may be 0.05 to 1 micrometer. In some embodiments, the back-chip adhesive layer 104 may be formed on one side of the back-chip back 102B of the wafer 102 by sputtering, evaporation, or electroplating.

In some embodiments, the back-chip reactive layer 106 can serve as a metal layer for bonding and/or thermal conductivity, such as nickel, copper, silver, tin, or combinations thereof, alloys thereof, or other suitable metal materials. In some embodiments, the thickness of the back-chip reactive layer 106 can be 0.3 to 10 micrometers. In some embodiments, the back-chip reactive layer 106 can be formed on one side of the back-chip 102B of the wafer 102 (e.g., on the back-chip adhesive layer 104) by a back-chip metallization process. The wafer is then die-bonded to the copper pads above the substrate using solder, conductive adhesive, or sintering paste.

Referring to Figure 2, a metal resistive layer 124 is disposed on the wafer pad 108 of the wafer 102, and the metal resistive layer 124 is electrically connected to the wafer pad 108. Therefore, the wafer pad 108 is disposed between the wafer 102 and the metal resistive layer 124, such that the metal resistive layer 124 is electrically connected to the wafer 102 through the wafer pad 108. The metal resistive layer 124 has a nanocrystalline structure, and the thickness of the metal resistive layer 124 is 2 to 20 micrometers. In some embodiments, an adhesion layer 122 may be formed on the wafer pad 108 as needed before forming the metal resistive layer 124 to increase the bonding strength between the wafer 102 and the metal resistive layer 124. In other words, the adhesion layer 122 is sandwiched between the wafer 102 and the metal resistive layer 124. In some embodiments, the adhesion layer 122 may also provide a lattice buffering effect to prevent the nanocrystalline structure in the metal resistive layer 124 from being affected by the crystal orientation of the wafer 102. In some embodiments, the adhesion layer 122 may include or be tungsten, titanium, chromium, or alloys thereof. In some embodiments, the thickness of the adhesion layer 122 may be 0.05 to 3 micrometers (e.g., 0.1 to 0.5 micrometers). It should be understood that the thickness of the adhesive layer 122 can be appropriately adjusted according to the actual application, and this disclosure is not limited thereto. In some embodiments, the adhesive layer 122 may be formed by sputtering, vapor deposition or electroplating.

In some embodiments, a metal compression layer 124 having a nanocrystalline structure is formed over the wafer pad 108 (or adhesion layer 122, if present). In some embodiments, the nanocrystalline structure has a plurality of parallel grain boundaries spaced 1 to 50 nanometers apart (e.g., 2 to 10 nanometers). In one embodiment, the spacing between the parallel grain boundaries is any rational number from 1 to 50 nanometers, such as 1 nanometer, 2 nanometers, 5 nanometers, 10 nanometers, 15 nanometers, 20 nanometers, 24 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, and 50 nanometers. In the cross-sectional metallographic diagram of the metal compressive layer 124, multiple parallel grain boundary regions occupy more than 20% of the metal compressive layer (e.g., any rational number between 20% and 100%, such as 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 100%), and the nano-grain density in the region above the metal compressive layer 124 must be at least 80% and less than 100% (e.g., any rational number between 80% and 99%, such as 80%, 85%, 90%, 95%, 99%). That is, the nanocrystalline structure inside the metal compressive layer 124 can be uniformly distributed, or the nanocrystalline structure can be concentrated in the upper region of the metal compressive layer 124 in a stepped or floating manner, while the remaining regions of the metal compressive layer remain as disordered grains. In some embodiments, the configuration of the nanocrystalline structure inside the metal compressive layer 124 can be determined by cross-sectional images. In detail, based on the cross-sectional image of the metal compressive layer 124, if the entire nano-twin layer is a twin structure, then the nano-twin structure inside the metal compressive layer 124 is determined to be uniformly distributed; if the nano-twin layer has a gradually distributed twin structure from the bottom to the surface in the upper region of the metal compressive layer 124, then the metal compressive layer 124... The internal nanocrystalline structure is determined to be concentrated in a stepped manner in the upper region of the metal compression layer 124; if only island-shaped nanocrystalline structures are disposed on the surface of the upper region of the metal compression layer 124, then the internal nanocrystalline structure of the metal compression layer 124 is determined to be concentrated in a floating manner in the upper region of the metal compression layer 124. In some embodiments, the metal compression layer 124 with nanocrystalline structure can be used to prevent the wafer 102 from breaking during ultrasonic wire bonding, which will be explained in detail later with reference to Figure 4.

Twin structures are formed when the accumulated strain energy within the material drives atoms in certain regions to uniformly shear to lattice positions mirror-symmetrical to the unsheared atoms within the grain. Twins include annealing twins, mechanical twins, and the nano-twins of this invention. The mutually symmetrical interface is called the twin boundary. Twins mainly occur in face-centered cubic (FCC) or hexagonal closed-packed (HCP) crystalline materials with the tightest lattice arrangement. Besides the tightest lattice arrangement condition, materials with lower stacking fault energy are generally more prone to twin formation. The main feature of the nano-twin of the present invention is that multiple nano-thickness nano-twin grains are stacked in parallel, and the nano-twin interfaces of each nano-twin grain have a (111) crystal orientation.

The twin grain boundaries are coherent crystalline structures, belonging to the low-energy Σ3 and Σ9 special grain boundaries. The crystal orientation is (111) plane. Compared to the high-angle grain boundaries formed by general annealing and recrystallization, the interfacial energy of the twin grain boundaries is about 5% of that of general high-angle grain boundaries. Due to the lower interfacial energy of the twin grain boundaries, they can avoid becoming pathways for oxidation, sulfidation, and chloride ion corrosion. Therefore, they exhibit better oxidation resistance and corrosion resistance. In addition, the symmetrical lattice arrangement of these twin grains has less obstruction to electron transport. Therefore, they exhibit better electrical and thermal conductivity. Because the twin grain boundaries block the movement of differential packings, the material can still maintain high strength. This combination of high strength and high conductivity has been proven in copper thin films.

Regarding high-temperature stability, due to the lower interfacial energy of twin grain boundaries, they are more stable than typical high-angle grain boundaries. Twin grain boundaries themselves are not easily moved at high temperatures and also exert a locking effect on the high-angle grain boundaries surrounding them, preventing these high-angle grain boundaries from moving. Therefore, the overall grain structure does not exhibit significant grain growth at high temperatures, thus maintaining the material's high-temperature strength. Regarding the reliability of current carrying, the diffusion rate of atoms through or across low-energy twin grain boundaries is lower. When using electronic products, the movement of atoms within the wire accompanied by high-density current is also more difficult. This solves the electromigration problem that often occurs in wires when current is carried. Reports have confirmed that twin crystals can suppress electromigration in copper thin films.

Furthermore, the nano-twin structure also has many advantages. For example, the strength of nano-twin thin films can be increased by about 10 times compared to ordinary disordered grain metals, while the conductivity remains unchanged, which is beneficial for improving the electrical properties of ultrasonic bonding interconnect packages. The hardness of nano-twin structure films is also higher than that of ordinary disordered grain films, which can prevent wafer breakage during ultrasonic bonding. In addition, the nano-twin structure has a high density of (111) crystal orientations, and it is known that the atomic diffusion rate of (111) crystal orientations is 3 to 5 orders of magnitude higher than that of (100) or (110) crystal orientations. Therefore, nano-twin metals have extremely high atomic diffusion capabilities, which also helps in the formation of ultrasonic bonding interfaces.

In some embodiments, the metal compressive layer 124 may include or be silver, copper, nickel, palladium, or gold. In some embodiments, the metal compressive layer 124 is composed of a nanocrystalline structure with a thickness of 2 to 20 micrometers (e.g., 4 micrometers, 8 micrometers, or 15 micrometers). When the thickness of the metal pressure-resistant layer 124 is less than 2 micrometers, it cannot effectively reduce the load during ultrasonic wire bonding to avoid the breakage of the wafer 102, and the nano-twin crystal layer with its (111) preferred crystal orientation is insufficient to provide a fast diffusion path for atoms at the ultrasonic bonding interface; when the thickness of the metal pressure-resistant layer 124 is greater than 20 micrometers, the metal pressure-resistant layer 124 is easily peeled off from the adhesive layer 122 on the wafer 102, especially when cutting wafers covered by the metal pressure-resistant layer, the metal pressure-resistant layer is more likely to peel off, and the production time of the covered metal pressure-resistant layer is too long and the cost is also high.

In some embodiments, the metallic tempered layer 124 can be formed by sputtering, vapor deposition, or electroplating. According to some embodiments, sputtering employs single-barrel sputtering or multi-barrel co-plating. The sputtering power supply can be, for example, direct current (DC), DC pulse, radio frequency (RF), high-power impulse magnetron sputtering (HIPIMS), etc. The sputtering power of the metallic tempered layer 124 can be, for example, from about 100W to about 500W. The sputtering process temperature is room temperature, but the sputtering temperature rises by about 50°C to about 200°C. The deposition rate of the metallic anti-compression layer 124 can be, for example, from about 0.5 nm/s to about 3 nm/s. The sputtering background pressure is less than 1 x ^10⁻⁵ torr, and the operating pressure can be, for example, from about 1 x ^10⁻³ torr to 1 x ^10⁻² torr. The argon flow rate is about 10 sccm to about 20 sccm. The stage speed can be, for example, from about 5 rpm to about 20 rpm. A bias voltage of about -100V to about -200V is applied to the substrate during the sputtering process, wherein applying an appropriate bias voltage to the substrate during the sputtering process is a key means of forming high-density nanotwins. It should be understood that the above sputtering process parameters can be appropriately adjusted according to the actual application, and this disclosure is not limited thereto.

According to other embodiments, the metallic compressive layer 124 can be formed by vapor deposition. The background pressure of the vapor deposition process is less than 1 x ^10⁻⁵ torr, the operating pressure can be, for example, about 1 x ^10⁻⁴ torr to about 5 x ^10⁻⁴ torr, and the argon flow rate can be about 2 sccm to about 10 sccm. The stage speed can be, for example, about 5 rpm to about 20 rpm. The deposition rate of the metallic compressive layer 124 can be, for example, about 1 nm/s to about 5.0 nm/s. In addition to applying ion bombardment to the metal pressure-resistant layer 124 during the vapor deposition process, the voltage is approximately 10V to approximately 300V and the current is approximately 0.1A to approximately 1.0A. Applying ion bombardment to the metal pressure-resistant layer during the vapor deposition process is a key method for forming high-density nanocrystals. It should be understood that the above vapor deposition process parameters can be appropriately adjusted according to actual applications, and this disclosure is not limited thereto.

According to other embodiments, the metal pressure-resistant layer 124 can be formed by electroplating. The electroplating process requires stirring the electroplating solution at a high speed of 500 to 1000 rpm, which is a key means of forming high-density nanocrystals.

Referring to Figure 3, a carrier board 142 is provided having carrier pads 144a and 144b. In some embodiments, carrier pads 144a and 144b are disposed on the carrier board 142 and spaced apart from each other. For simplicity, only one carrier pad 144b is shown in the figure, but this disclosure is not limited thereto. In other embodiments, when the chip 102 has a plurality of chip pads 108, a plurality of spaced carrier pads 144b may also be disposed on the carrier board 142, each corresponding to the plurality of chip pads 108. For simplicity, carrier plate washers 144a and 144b are sometimes collectively referred to as carrier plate washers 144.

In some embodiments, the carrier 142 may include a printed circuit board ceramic substrate, a leadframe, or an insulated metal substrate (IMS) (or insulated metal baseplate (IMB)). The ceramic substrate may comprise aluminum oxide ( _Al₂O₃ ), aluminum nitride (AlN), or silicon nitride ( _Si₃N₄ ). In some embodiments, the carrier pad ₁₄₄ is part of a patterned _circuit diagram and is disposed on surface 142F of the carrier 142. In some embodiments, the carrier pads 144a and 144b comprise or are made of copper. The substrate pads 144a and 144b are disposed on the substrate 142 by direct bonded copper (DBC), direct plated copper (DPC), or active metal brazing (AMB).

In some embodiments, the carrier plate 142 may optionally include protective films 146a and 146b respectively disposed on the surfaces of carrier plate bonding pads 144a and 144b above the carrier plate, as shown in the figure. Protective film 146a is disposed on carrier plate bonding pad 144a above the carrier plate, and protective film 146b is disposed on carrier plate bonding pad 144b above the carrier plate. The thickness of each carrier plate bonding pad 144a and 144b is approximately 0.5 to 1 millimeter (mm), for example, 0.635 mm. For simplicity, protective films 146a and 146b may sometimes be collectively referred to as protective film 146. Protective film 146 is used to prevent the carrier plate bonding pad 144 from oxidizing or corroding due to contact with air in a normal environment. In some embodiments, the protective film 146 may include or be a metal film. The metal film may include or be nickel (Ni), nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), silver (Ag), or nickel/silver (Ni/Ag), or the metal film may have a nanocrystalline structure. In some embodiments, the protective film 146 may have a thickness ranging from 0.1 to 100 micrometers, depending on the metal film. In some embodiments, the encapsulation structure 100 may not have a protective film 146.

Referring to Figure 4, the wafer 102 is bonded to the substrate 142. For example, the wafer 102 is bonded to the substrate solder pad 144a (or protective film 146a, if present) of the substrate 142 via a back die reactive layer 106 located on one side of the back die 102B. In some embodiments, die bonding such as eutectic bonding, adhesive bonding, solder bonding, or sintering bonding can be used to bond the wafer 102 to the substrate 142, but this disclosure is not limited thereto.

In some embodiments, ultrasonic wire bonding is used to electrically connect the metal withstand layer 124 and the substrate pad 144b to each other via an interconnect conductor 162, such that one end 1621 of the interconnect conductor 162 is electrically connected to the chip pad 108 via the metal withstand layer 124, and the other end 1622 is electrically connected to the substrate pad 144b. In this way, the chip 102 can be electrically connected to the substrate 142 via the chip pad 108, the metal withstand layer 124, the interconnect conductor 162, and the substrate pad 144b. Specifically, one end 1621 of the interconnect conductor material is first ultrasonically wire-bonded to the metal pressure-resistant layer 124 to form a first solder joint A. Then, the other end 1622 of the interconnect conductor material is ultrasonically wire-bonded to the substrate solder pad 144b to form a second solder joint B. In some embodiments, after forming the second solder joint B, the interconnect conductor material is cut off to form an interconnect conductor 162 having the first solder joint A and the second solder joint B.

In some embodiments, ultrasonic bonding is performed under process conditions of 50 to 300 milliwatts (mW) of ultrasonic vibration power, 100 to 150 millisieverts (ms) of bonding time, and 200 to 1000 millineutons (cN) of load (e.g., 400 to 600 cN) to bond metal wires or strips to the metal compression layer 124, and the wafer 102 does not crack. In some embodiments of this disclosure, unless specifically defined, the term "load" refers to the strength applied to the weld joint during the ultrasonic bonding process.

In detail, because the surface of the metal compressive layer 124 has a nano-twin structure with a high density (111) crystalline orientation of over 80%, it can more effectively enhance the atomic diffusion reaction with the metal wire or strip during ultrasonic wire bonding and accelerate the formation of the bonding interface. Therefore, the load of ultrasonic wire bonding can be significantly reduced, effectively preventing the wafer 102 from cracking. In addition, the nano-twin structure has high hardness, which can further protect the wafer 102 underneath from cracking when using thick copper wire, copper strip, thick silver wire, or silver strip for ultrasonic wire bonding. In some embodiments, the load can be reduced by more than 30% compared to using a coarse-grained metal.

In some embodiments, the interconnect conductor 162 is used to provide signal and power transmission between the chip 102 and the substrate 142, and may also serve a heat dissipation function. In some embodiments, the interconnect conductor 162 is selected from the following family: coarse aluminum wire, aluminum strip, coarse copper wire, copper strip, aluminized coarse copper wire, aluminized copper strip, silver alloy coarse wire, and silver alloy strip. In some embodiments disclosed herein, unless specifically defined, the term "strip" refers to a continuous strip of thin material that is generally flat, has a thickness of 10 micrometers to 500 micrometers, and a width that is 2 to 200 times the thickness but generally not more than 5 millimeters (mm). The term "thick wire" refers to a continuous long wire with a diameter of approximately 100 micrometers or more, which is much larger than the diameter of the thin wires used in general IC or LED hot-pressing wire bonding, which is less than 25.4 micrometers.

As shown in Figure 4, this disclosure provides a packaging structure 100, including a carrier 142 having a carrier pad 144b, a wafer 102 disposed above the carrier 142 and having a wafer pad 108, a metal pressure-resistant layer 124 disposed above the wafer pad 108 and having a nano-twin crystal structure, and an interconnect conductor 162. One end of the interconnect conductor 162 is electrically connected to the wafer pad 108 via the metal pressure-resistant layer 124, and the other end is electrically connected to the carrier pad 144b.

The following describes some experimental examples of the packaging structures disclosed herein, as well as the test results of comparative examples.

Comparative example 1 : SiC/Cr/Cu Structure

Figure 5 shows a cross-sectional metallographic view of a SiC/Cr/Cu structure obtained using focused ion beam (FIB) according to some embodiments. The SiC/Cr/Cu structure is an example of a package structure 100 similar to that in Figure 4, but in which a coarse-grained metal layer 124 is replaced by a metal resist layer (i.e., without a nanocrystalline structure; not shown). Specifically, the wafer 102 is silicon carbide (SiC), the adhesive layer 122 is chromium (Cr), and the metal resist layer 124 is replaced by a coarse-grained copper (Cu) layer with a thickness of 4 micrometers.

Comparative example 2 : SiC/Cr/Ni/Ag Structure

Figure 6 shows a cross-sectional metallographic view of a SiC/Cr/Ni/Ag structure obtained using focused ion beam (FIB) according to some embodiments. The SiC/Cr/Ni/Ag structure is an example of a package structure 100 similar to that in Figure 4, but in which the metal pressure-resistant layer 124 is replaced by a coarse-grained metal layer (i.e., without a nanocrystalline structure; not shown). Specifically, the wafer 102 is silicon carbide (SiC), the adhesive layer 122 is chromium (Cr/Ni), and the metal pressure-resistant layer 124 is replaced by a coarse-grained silver (Ag) layer with a thickness of 4 micrometers.

Experimental examples 1 : SiC/Cr/nt-Cu Structure

Figure 7 shows a cross-sectional metallographic image of the SiC/Cr/nt-Cu structure obtained using focused ion beam (FIB) based on some experimental examples. The SiC/Cr/nt-Cu structure is an example of the package structure 100 in Figure 4, wherein the wafer 102 is silicon carbide (SiC), the adhesive layer 122 is chromium (Cr), and the metal compression layer 124 is copper nano-twinned (nt-Cu) with a nano-twinned (nt) structure.

Experimental examples 2 : SiC/Cr/nt-Ag Structure

Figure 8 shows a cross-sectional metallographic image of the SiC/Cr/nt-Ag structure obtained using focused ion beam (FIB) based on some experimental examples. The SiC/Cr/nt-Ag structure is an example of the package structure 100 in Figure 4, wherein the wafer 102 is silicon carbide (SiC), the adhesive layer 122 is chromium (Cr), and the metal compression layer 124 is silver nano-twinned (nt-Ag) with a nano-twinned (nt) structure.

[ Ultrasonic bonding of copper strip ]

The silicon carbide wafers with metal compressive layers in Comparative Examples 1-2 and Experimental Examples 1-2 were ultrasonically wire-bonded using copper strip (1.5 mm wide and 0.15 mm thick). The results showed that at an ultrasonic wire bonding power of 200 mW and a load below 300 cN, neither the silicon carbide wafers with metal compressive layers in Comparative Examples 1-2 nor those in Experimental Examples 1-2 cracked. However, the metal compressive layer wafers with disordered grains in Comparative Examples 1-2 could not be bonded to the copper strip. In Experimental Examples 1-2, the nano-twin metal compression layer wafers could be bonded to the copper strip. When the ultrasonic wire bonding load was increased to 500 cN, although the silicon carbide wafers of both Comparative Examples 1-2 and Experimental Examples 1-2 could be bonded to the copper strip, most of the metal compression layer wafers with disordered grains in Comparative Examples 1-2 cracked, while none of the nano-twin metal compression layer wafers in Experimental Examples 1-2 cracked. The second bonding point was also successfully bonded to the bonding pad of the substrate 142. The ultrasonic bonding results of the copper strip to the copper and silver metal compression layer wafers in Experimental Examples 1-2 were similar.

[ Thick copper wire ultrasonic bonding ]

The silicon carbide wafers with metal compressive layers in Comparative Examples 1-2 and Experimental Examples 1-2 were ultrasonically wire bonded using thick copper wire (380 mm in diameter). The results showed that at an ultrasonic wire bonding power of 85.5 mW and a load of 300 cN, none of the silicon carbide wafers with metal compressive layers in either Comparative Examples 1-2 or Experimental Examples 1-2 cracked. However, most of them showed poor bonding or failed to bond with the thick copper wire. Even when the load was increased to 500 cN, most wafers still did not crack. However, Comparative Examples 1-2 showed some cracking. The randomly grained metal compression layer wafers bonded poorly or not at all with the coarse copper wire. In contrast, most of the nano-twin metal compression layer wafers in Examples 1-2 could bond with the coarse copper wire. When the ultrasonic wire bonding load was increased to 800 cN, although the silicon carbide wafers of the metal compression layers in Comparative Examples 1-2 and Experimental Examples 1-2 could bond with the coarse copper wire, most of the randomly grained metal compression layer wafers in Comparative Examples 1-2 cracked, and a few of the nano-twin metal compression layer wafers in Experimental Examples 1-2 also showed cracks. The ultrasonic bonding results of the coarse copper wire with the copper and silver metal compression layer wafers in Examples 1-2 were similar.

Based on the results of ultrasonic wire bonding of copper strip and thick copper wire, it can be confirmed that in the experimental example (using metal compression layer 124 with nano-twin crystal structure), a load of 500 cN is sufficient to complete the bonding of copper strip and thick copper wire to metal compression layer 124 during ultrasonic wire bonding, and the wafer 102 does not crack. In contrast, the comparative example (using a disordered grain metal layer without a nanocrystalline structure) could achieve bonding under a 500cN load during ultrasonic wire bonding of copper strips, but there was already a risk of wafer breakage. For the disordered grain metal layer wafer in the comparative example, ultrasonic bonding with coarse copper wire required an increased load of 800cN to complete the bonding, but wafer 102 still broke severely. From the above results of ultrasonic wire bonding of copper strips and coarse copper wires, it is clear that the metal compressive layer 124 with a nanocrystalline structure can complete bonding under a lower load and/or prevent wafer 102 from breaking during ultrasonic wire bonding.

The disclosed embodiments have several advantageous features. The metal pressure-resistant layer disposed above the wafer, due to its nanocrystalline structure, can effectively enhance the atomic diffusion reaction of the metal wires or strips during ultrasonic wire bonding and accelerate the formation of the bonding interface. Therefore, it can reduce the load during ultrasonic wire bonding to prevent wafer breakage. Furthermore, the nanocrystalline structure has high hardness, which can further protect the underlying wafer from breakage when using thick copper wires, copper strips, thick silver wires, or silver strips for ultrasonic wire bonding.

The above outlines the components of several embodiments to facilitate a better understanding of the viewpoints of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

100: Package Structure 102: Chip 102B: Chip Back 102F: Chip Face 104: Chip Back Adhesion Layer 106: Chip Back Reactive Layer 108: Chip Pad 110: Dielectric Layer 122: Adhesion Layer 124: Metal Compression Layer 142: Carrier Board 142F: Surface Mount 144/144a/144b: Carrier Board Pad 146/146a/146b: Protective Film 162: Interconnect Conductor 1621: One End 1622: The Other End A: First Solder Joint B: Second Solder Joint

The various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the invention. It should also be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting its scope; this disclosure is equally applicable to other embodiments. Figures 1 through 4 are partial cross-sectional views illustrating the formation of the package structure at different process stages according to some embodiments of this disclosure. Figure 5 is a cross-sectional metallographic image of a SiC/Cr/Cu structure obtained using focused ion beam chromatography according to some embodiments. Figure 6 shows a cross-sectional metallographic image of a SiC/Cr/Ni/Ag structure obtained using focused ion beam analysis, according to some embodiments. Figure 7 shows a cross-sectional metallographic image of a SiC/Cr/nt-Cu structure obtained using focused ion beam analysis, according to some embodiments. Figure 8 shows a cross-sectional metallographic image of a SiC/Cr/nt-Ag structure obtained using focused ion beam analysis, according to some embodiments.

Domestic Storage Information (Please record in order of storage institution, date, and number) None International Storage Information (Please record in order of storage country, institution, date, and number) None

100: Packaging Structure

102: Chip

104: Crystal Back Adhesion Layer

106: Back-side reaction layer

108: Chip Pads

110: Dielectric layer

122: Adhesive Layer

124: Metallic compressive layer

142: Carrier Plate

144/144a/144b: Carrier Plate Welding Pads

146/146a/146b: Protective film

162: Inline Conductor

1621: One end

1622: The Other End

A: First solder joint

B: Second solder joint

Claims (10)

A packaging structure includes: a carrier substrate having a carrier substrate pad; a die disposed above the carrier substrate and having a die substrate pad; and a metal pressure-resistant layer disposed directly above the die substrate pad and having a first nanocrystalline structure; an interconnect conductor having one end electrically connected to the metal pressure-resistant layer and the other end electrically connected to the carrier substrate pad; wherein the metal pressure-resistant layer is electrically connected to the carrier substrate pad; and The first nano-twin crystal structure is uniformly distributed within the metal compression layer, or the first nano-twin crystal structure is concentrated in a stepped or floating manner in an upper region of the metal compression layer, and the remaining regions of the metal compression layer are disordered grains. The packaging structure as described in claim 1, wherein the carrier includes a printed circuit board or a ceramic substrate. The packaging structure as described in claim 1 further includes a protective film disposed on the substrate solder pad, wherein the protective film includes a metal film and the metal film has a second nanocrystalline structure. The packaging structure as described in claim 1, wherein the thickness of the metal pressure-resistant layer is 2 to 20 micrometers. The packaging structure of claim 1, wherein the first nanocrystalline structure has a plurality of parallel-arranged crystal boundaries, and the spacing between the crystal boundaries is 1 to 50 nanometers. As in the packaging structure of claim 1, in a cross-sectional metallographic image of the metal compression layer, a parallel-arranged twin grain boundary region occupies more than 20% of the metal compression layer, and the nano-twin density in the upper region of the metal compression layer is at least 80%. The packaging structure as described in claim 1 further includes a dielectric layer disposed on the same layer as the die pad, an upper surface of the die pad being coplanar with an upper surface of the dielectric layer, and the metal pressure-resistant layer being disposed above the dielectric layer. A method of manufacturing a packaging structure includes: providing a wafer having a wafer pad; forming a metal compression layer having a nanocrystalline structure directly above the wafer pad, wherein the nanocrystalline structure is uniformly distributed within the metal compression layer, or the nanocrystalline structure is concentrated in a stepped or floating manner in an upper region of the metal compression layer and the remaining region of the metal compression layer is composed of disordered grains; providing a carrier plate having a substrate pad; bonding the wafer to the carrier plate; and electrically connecting the metal compression layer and the substrate pad with an interconnect conductor. The method of manufacturing the packaging structure as described in claim 8 further includes: forming an adhesive layer between the metal compression layer and the chip pad. The method of manufacturing the packaging structure as described in claim 8, wherein the nano-twin structure has a plurality of parallel-arranged twin boundaries, and the spacing between the twin boundaries is 1 to 50 nanometers.