TWM672838U - Package structure - Google Patents

Abstract

A package structure includes a chip; a first metal film disposed over the chip; a first sintered layer disposed on and in direct contact with the first metal film; and a conductive sheet disposed on the first sintered layer and electrically connected to the chip through the first metal film. The package structure further includes a carrier, a second metal film disposed on the carrier, and a second sintered layer disposed on and in direct contact with the second metal film. The conductive sheet is disposed on the second sintered layer and electrically connected to the chip through the second metal film. The chip and the carrier of the package structure are connected to each other through the conductive sheet. Each of the first and second metal film include a nano-twinned structure.

Description

Package structure

The present invention relates to packaging technology, and more particularly to a packaging structure having a nanocrystalline structure to assist in sintering and bonding interconnects within a conductive sheet.

The inverter in an electric vehicle's motor control unit is the most critical component for converting electrical energy into kinetic energy. The power electronics module is the most crucial component influencing electrical energy conversion efficiency. The voltage and current of automotive motor power modules are significantly higher than those of conventional power modules and consumer integrated circuits (ICs). Furthermore, these modules must pass various automotive-grade AEC-Q101 reliability tests, placing extremely high demands on packaging technology and materials.

Interconnect technology is a technique in which a conductive material is used to connect the chip and substrate in electronic packaging. For interconnects between the pads on a power IC chip and the copper conductive layer of a ceramic substrate or printed circuit board, a conductive sheet can be used. In existing technology, this conductive sheet is typically made of a solder-tin alloy. However, due to the extremely low melting point of solder-tin alloy, this limits the operating temperature of the power IC chip. Therefore, while existing packaging structures generally meet the requirements, they are not completely satisfactory and still require further improvement.

One aspect of the present disclosure relates to a package structure. The package structure includes a chip, a first metal film disposed above the chip, a first sintered layer disposed on and in direct contact with the first metal film, and a conductive sheet disposed on the first sintered layer and electrically connected to the chip via the first metal film. The first metal film has a first nanocrystalline structure.

The following disclosure provides numerous embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the present inventive embodiments. Of course, these are merely examples and are not intended to limit the present inventive embodiments. For example, a description referring to a first element formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements so that they are not in direct contact. In addition, the present inventive embodiments may refer to reference numbers and/or letters repeatedly in various examples. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and/or configurations discussed.

The following describes some variations of the embodiments. Similar reference numerals are used to designate similar elements throughout the various figures and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, or after the method, and that some of the described steps may be replaced or deleted in other embodiments of the method.

Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used to facilitate describing the relationship of one component or components to another component or components in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or in other orientations, spatially relative adjectives are interpreted based on that orientation.

The terms used herein are intended only to illustrate specific embodiments and are not intended to limit the present inventive concept. Unless the context clearly indicates a different meaning, expressions used in the singular also encompass expressions in the plural. Throughout this specification, it should be understood that terms such as "comprise," "have," and "include" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed herein, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or be added.

The following describes some embodiments of the present invention. Additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or eliminated in different embodiments. Additional components may be added to the package structure. Some of the components may be replaced or eliminated in different embodiments. Although some embodiments are discussed as performing steps in a specific order, these steps may also be performed in another logical order.

A known solution to the aforementioned shortcomings of using solder-tin alloy for the conductive sheet is to use silver or copper sintering paste for bonding. However, the inventors of this novel invention have discovered that this sintering paste typically needs to be sintered at temperatures exceeding 250°C to achieve the bond strength of the package structure that meets currently accepted industry standards (e.g., greater than 20 MPa). Furthermore, during the cooling process after sintering to room temperature, the difference in thermal expansion coefficients between the conductive sheet and the power IC chip creates extremely high thermal stress, which can easily damage the power IC chip. In particular, fracture of the power IC chip's aluminum pad is the most common failure mode. Furthermore, after sintering, the sintering paste contains a large number of voids, which reduces the electrical and thermal conductivity of the entire power module. Furthermore, the numerous voids in the sintered layer can easily connect to form cracks, potentially causing delamination at the bonding interface with the power IC chip, thereby reducing the bonding strength. The present disclosure aims to provide a package structure and its manufacturing method to address these and other issues.

To this end, the present disclosure provides a package structure having a nano-twinned (NT) structure and a method for manufacturing the same. Due to the excellent atomic high diffusion ability of the nano-twinned structure surface, it can assist in completing sintering bonding and achieving internal connections between the chip and the conductive sheet at low temperatures (for example, below 240°C), thereby avoiding chip damage caused by extremely high thermal stress. In addition, the porosity of the sintered layer can be reduced and its strength can be increased, thereby improving the conductivity and thermal conductivity of the package structure, as well as the bonding strength between the chip and the conductive sheet, so that the bonding strength of the package structure after low-temperature sintering can reach the current industry-accepted standards. Furthermore, these holes can be prevented from connecting into cracks, causing the sintered layer to peel off.

FIG. 1 to FIG. 3 are cross-sectional views illustrating different stages of a process for forming a package structure 100 according to some embodiments of the present disclosure.

Referring to FIG. 1 , a chip 102 is provided. In some embodiments, chip 102 may comprise a power integrated circuit (IC) chip, but the present disclosure is not limited thereto. In other embodiments, chip 102 is a chip for other purposes, such as a driver IC chip or a control IC chip. The power IC chip may comprise a silicon chip, a silicon carbide chip, or a gallium nitride chip, but the present disclosure is not limited thereto.

In some embodiments, chip 102 may include a redistribution layer (RDL). To simplify the diagram, the RDL layer is shown as only the top-most pads (e.g., pad 1021) and dielectric layer (e.g., dielectric layer 1022), but the present disclosure is not limited thereto. The RDL layer may include other components, such as metallization layers and vias, as is known in the art. As shown in FIG. 1 , the RDL layer includes a pad 1021 disposed on the surface 102F of chip 102, and a dielectric layer 1022 disposed on the same layer as the pad 1021. The pad 1021 is formed in the topmost dielectric layer 1022, and the surface of the pad 1021 is substantially coplanar (e.g., flush) with the dielectric layer 1022. It should be noted that although only one pad 1021 is shown in the figure, the present disclosure is not limited thereto. The number, shape, and configuration of the pads 1021 can be set according to design requirements and separated from each other by the dielectric layer 1022. In some embodiments, the pad 1021 may include or be aluminum, copper, or other suitable metal materials. The dielectric layer 1022 may include or be silicon oxide, polyimide, or other suitable dielectric materials.

Next, an adhesive layer 104 is optionally formed on the wafer 102. Adhesion layer 104 can provide improved bonding strength between the wafer 102 and the subsequently formed first metal film 106. Furthermore, adhesion layer 104 acts as a lattice buffer. If the first metal film 106 is formed directly on the wafer 102, the first nanostructure of the first metal film 106 may be affected by the crystal orientation of the wafer 102. In some embodiments, the material of adhesion layer 104 may include or be tungsten (W), titanium (Ti), tungsten-titanium (W-Ti), chromium (Cr), alloys thereof, or other suitable adhesive materials. The thickness of adhesion layer 104 may be 0.1 micron to 0.9 micron. It should be understood that the thickness of the adhesive layer 104 can be appropriately adjusted according to actual applications, and the present disclosure is not limited thereto. The adhesive layer 104 can be formed on the surface 102F of the chip 102 by sputtering, evaporation, or electroplating.

Still referring to FIG. 1 , a first metal film 106 is formed over the wafer 102 (or the adhesion layer 104, if present). The first metal film 106 has a first nanocrystalline structure. The first nanocrystalline structure has parallel-aligned crystalline boundaries with a spacing of 1 nm to 50 nm (e.g., 20 to 30 nm). Generally, the smaller the spacing of the parallel-aligned crystalline boundaries, the higher the hardness of the first metal film 106. In a cross-sectional metallographic image of the first metal film 106, the parallel-aligned crystalline boundaries account for more than 50% (e.g., more than 65%, more than 75%, more than 85%, or more than 95%) of the total grain boundaries. It should be noted that the first nanocrystalline structure of the first metal film 106 can be uniformly or step-wise distributed in the first metal film 106, or the first nanocrystalline structure can be concentrated in the region of the first metal film 106 adjacent to the first sintered layer 108 (shown in FIG. 2 ) to be formed later, while the remaining portion remains as random grains, and the thickness of the region accounts for 10% to 100% of the total thickness of the first metal film 106. The first nanocrystalline structure located at the interface between the first metal film 106 and the first sintered layer 108 (shown in FIG. 2 ) to be formed later has a high density (111) crystalline orientation of atoms with high diffusion ability, thereby facilitating low-temperature bonding between the first metal film 106 and the first sintered layer 108.

Twin structures form when accumulated strain energy within a material drives the uniform shearing of atoms in a certain region to positions that are mirror-symmetrical with the unsheared atoms within the grain. Twins are classified into three types: annealing twins, mechanical twins, and nano-twins. The interface between these symmetrical twins is the twin boundary.

Twins primarily occur in face-centered cubic (FCC) or hexagonal closed-packed (HCP) crystalline materials with the densest lattice arrangement. In addition to the densest lattice arrangement, materials with smaller stacking fault energies are generally more likely to form twins. The main feature of the nano-twins developed in this study is that twin grains with a thickness of multiple nanometers are stacked in parallel, and the twin interfaces of each twin grain have a (111) crystal orientation.

Twin grain boundaries are coherent crystal structures and belong to the low-energy Σ3 and Σ9 special grain boundaries. The crystal orientation is the {111} plane. Compared with the high-angle grain boundaries formed by general annealing recrystallization, the interface energy of twin grain boundaries is about 5% of that of general high-angle grain boundaries. Due to the lower interface energy of twin grain boundaries, they can avoid becoming paths for oxidation, sulfidation and chloride ion corrosion. Therefore, they exhibit better oxidation resistance and corrosion resistance. In addition, the symmetrical lattice arrangement of this twin crystal has less resistance to electron transmission. Therefore, they exhibit better electrical and thermal conductivity. Because the twin grain boundaries hinder the movement of dislocations, the material can still maintain high strength. This characteristic of both high strength and high conductivity has been confirmed in copper thin films.

In terms of high-temperature stability, due to their lower interfacial energy, twin grain boundaries are more stable than typical high-angle grain boundaries. Twin grain boundaries themselves are less mobile at high temperatures and also lock the surrounding high-angle grain boundaries, preventing them from moving. Consequently, the overall grain size exhibits no significant grain growth at high temperatures, maintaining the material's high-temperature strength. Regarding reliability when current is applied, the diffusion rate of atoms through or across low-energy twin grain boundaries is lower. The high current density associated with the movement of atoms within the wire during use in electronic products also makes it more difficult. This solves the electromigration problem that often occurs when current is applied to wires. In copper thin films, it has been reported that polycrystalline can suppress the electrical migration of materials.

The properties of the nanocrystal structure provide numerous benefits for package structure 100. For example, the excellent atomic diffusion capability of the nanocrystal surface allows the subsequent sintering of chip 102 and conductive sheet 112 at low temperatures (shown in FIG. 4 ), thus preventing chip damage caused by extreme thermal stress. Furthermore, the porosity of the first sintered layer 108 can be reduced, thereby increasing its strength. This will be explained in detail later in conjunction with FIG. 4 .

In some embodiments, the first metal film 106 having a nanocrystalline structure may include or be silver, copper, or alloys thereof (e.g., a silver-copper alloy). The thickness of the first metal film 106 is between 1 micron and 10 microns (e.g., 3 microns, 5 microns, or 7 microns). If the thickness of the first metal film 106 is less than 1 micron, the high atomic diffusion capability of the nanocrystalline structure cannot be realized. On the other hand, if the thickness of the first metal film 106 is greater than 10 microns, the first metal film 106 may easily peel off from the wafer 102 (or the adhesive layer 104, if present), especially when cutting the wafer 102 covered by the first metal film 106. Furthermore, forming a thicker first metal film 106 requires longer processing time and increases processing costs.

In some embodiments, the first metal film 106 can be formed by sputtering, evaporation, or electroplating. In some embodiments, sputtering is performed using a single-gun sputtering process or a multi-gun co-plating process. The sputtering power source can be, for example, direct current (DC), pulsed DC, radio frequency (RF), or high-power impulse magnetron sputtering (HIPIMS). The sputtering power for the first metal film 106 can be, for example, approximately 100 W to approximately 500 W. The sputtering process temperature is room temperature, but the temperature rises by approximately 50°C to approximately 200°C during the sputtering process. The deposition rate of the first metal film 106 can be, for example, about 0.5 nm/s to about 3 nm/s. The sputtering background pressure can be less than ^1x10-5 torr, and the operating pressure can be, for example, about ^1x10-3 torr to ^1x10-2 torr. The argon flow rate can be about 10 sccm to about 20 sccm. The stage rotation speed can be, for example, about 5 rpm to about 20 rpm. Preferably, a bias voltage of about -100 V to about -500 V (e.g., -150 V or -300 V) can be applied to the substrate during the sputtering process to form high-density nanocrystals. If the bias voltage is less than -100 V or greater than -500 V, the nanocrystal density of the sputtered metal film will be less than 50%, and low-temperature sintering bonding effect cannot be achieved.

According to other embodiments, the first metal film 106 can be formed by evaporation. In some embodiments, the background pressure of the evaporation process is less than ^1x10-5 torr, the operating pressure can be, for example, approximately ^1x10-4 torr to approximately ^5x10-4 torr, and the argon flow rate can be approximately 2 sccm to approximately 10 sccm. The stage rotation speed can be, for example, approximately 5 rpm to approximately 20 rpm. The deposition rate of the first metal film 106 can be, for example, approximately 1 nm/s to approximately 5.0 nm/s. Preferably, during the evaporation process, ion bombardment can be applied to the first metal film 106 at a voltage of approximately 10 V to approximately 300 V (e.g., 100 V or 200 V) and a current of approximately 0.1 A to approximately 1.0 A (e.g., 0.3 A or 0.8 A) to form high-density nanocrystals. If the ion impact voltage is lower than 10V or higher than 300V, or the current is lower than 0.1A or higher than 1.0A, the nanocrystal density of the deposited metal film will be less than 50%, and low-temperature sintering bonding will not be achieved.

Referring to FIG. 2 , a first sintering paste 1080 is applied to the first metal film 106 . This first sintering paste 1080 is subsequently used to form a first sintering layer 108 (shown in FIG. 4 ) after a sintering process as shown in FIG. The first sintering layer 108 is used to provide a better bonding force between the first metal film 106 and the conductive sheet 112 (shown in FIG. 4 ), thereby preventing the conductive sheet 112 from peeling off the surface of the first metal film 106 . In some embodiments, the first sintering paste 1080 (which forms the first sintering layer 108 after the sintering process) may include silver, copper, or a silver-copper composite. The first sintering paste 1080 may include silver powder or copper powder. Specifically, the first sintering paste 1080 is composed of silver or copper powder and additives (such as a solder flux and an adhesive). In some embodiments, the first sintering paste 1080 is fluid and plastic before sintering, thereby helping to elastically control the overall height of the conductive sheet 112, thereby ensuring a tight bond between the conductive sheet 112, the chip 102, and the carrier 302.

Next, the first sintering paste 1080 and the first metal film 106 may be patterned to expose a portion of the surface 102F of the chip 102. In embodiments where a dielectric layer 1022 is present, the patterning exposes the dielectric layer 1022. As previously described, the redistribution layer may include a plurality of isolated bond pads 1021. Therefore, the patterned first metal film 106 is positioned directly above the bond pads 1021 and isolated from each other to prevent undesirable electrical connections between the bond pads 1021. In some embodiments, the patterning process may include a lithography process and an etching process. For example, a photoresist pattern (e.g., consistent with the pattern of the bonding pad 1021) is first defined on the unpatterned first sinter paste 1080. The photoresist pattern is then used as a mask to etch the first sinter paste 1080, the first metal film 106, and the adhesive layer 104 (if present). In some embodiments, the lithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying, but the present disclosure is not limited thereto. The etching process may include a dry etching process, a wet etching process, reactive ion etching (RIE), ashing, and/or other etching methods, but the present disclosure is not limited thereto.

Referring to FIG. 3 , a chip 102 is placed on a carrier 302 having copper pads 304a and 304b. Copper pads 304a and 304b are spaced apart from each other. To simplify the diagram, the carrier 302 is shown with only one copper pad 304a corresponding to the chip 102, but the present disclosure is not limited thereto. In other embodiments, the carrier 302 may have multiple spaced-apart copper pads 304a corresponding to the number of chips 102. For simplicity, the copper pads 304a and 304b may sometimes be collectively referred to as copper pads 304.

In some embodiments, carrier 302 may include a printed circuit board (PCB) or a ceramic substrate. The ceramic substrate may include _aluminum oxide ( _Al2O3 ), aluminum nitride (AlN), or silicon nitride ( _Si3N4 ). In some embodiments, copper pad 304 is part of a patterned circuit pattern and is disposed on the surface _of carrier 302. In some embodiments, copper pad 304 may include or be copper. Copper pad 304 is disposed on carrier 302 using eutectic direct bonding (DBC), direct plated copper (DPC), or active metal brazing (AMB). The thickness of copper pad 304 is 0.5 to 1 mm, for example, approximately 0.6 mm.

In some embodiments, a protective film (not shown) may be included above the copper pad 304, and the chip 102 is bonded to the protective film. The protective film is used to prevent the copper pad 304 from oxidation or corrosion due to contact with air under normal conditions. The protective layer may include or be an organic solderability preservative (OSP) or a metal film. The metal film may include or be nickel (Ni), nickel/gold (Ni/Au), or nickel/palladium/gold (Ni/Pd/Au). The thickness of the protective film is 0.1 microns to 100 microns.

Still referring to FIG. 3 , in some embodiments, the chip 102 is bonded to the carrier 302. For example, the chip 102 is bonded to the copper pads 304a (or a protective film, if present) of the carrier 302. The chip 102 can be bonded to the copper pads 304a of the carrier 302 by a die bonding method such as gold-silicon eutectic bonding, adhesive bonding, solder bonding, or sintering bonding, but the present disclosure is not limited thereto.

In some embodiments, a second metal film 206 is formed on the copper pad 304b (or the protective film, if present). The second metal film 206 has a second nanocrystalline structure. The material, thickness, and formation method of the second metal film 206, as well as the internal structure of the second nanocrystalline structure, can be the same or similar to the first metal film 106 and its first nanocrystalline structure described in FIG1 . For the sake of brevity, these details are not further described here. As shown in FIG3 , the chip 102 and the second metal film 206 are spaced apart and disposed above the carrier 302. Specifically, the chip 102 and the second metal film 206 are disposed on the separated copper pads 304a and 304b, respectively. It should be noted that because the second metal film 206 and the copper pad 304b (metal material) have excellent bonding strength, an adhesive layer between them (e.g., the adhesive layer 104 between the chip 102 and the first metal film 106) can be omitted, but the present disclosure is not limited to this. In other embodiments, an adhesive layer can be provided between the second metal film 206 and the copper pad 304b as needed to further enhance the bonding strength between the two.

In some embodiments, a second sintering paste 2080 is applied to the second metal film 206. This second sintering paste 2080 is subsequently used to form a second sintering layer 208 (shown in FIG. 4 ) after a sintering process as shown in FIG. The second sintering layer 208 is used to provide a better bonding force between the second metal film 206 and the conductive sheet 112 (shown in FIG. 4 ), thereby preventing the conductive sheet 112 from peeling off the surface of the second metal film 206. In some embodiments, the material, form, and formation method of the second sintering paste 2080 can be referenced to the first sintering paste 1080 described in FIG. 2 , and for the sake of brevity, these details will not be repeated here. In some embodiments, the second sintering paste 2080 is fluid and plastic before sintering, thereby helping to elastically control the overall height of the conductive sheet 112, thereby ensuring that the conductive sheet 112, the chip 102, and the carrier 302 can be tightly bonded.

FIG4 is a partial cross-sectional view of the package structure 100 according to some embodiments of the present disclosure.

Referring to FIG. 4 , a bonding process is performed to bond the conductive sheet 112 to the first metal film 106 through the first sintered layer 108, thereby electrically connecting the conductive sheet 112 to the chip 102. Furthermore, the conductive sheet 112 is bonded to the second metal film 206 through the second sintered layer 208, thereby electrically connecting the chip 102 to the carrier 302. In other words, the chip 102 is electrically connected to the carrier 302 via the conductive sheet 112. In some examples, the conductive sheet 112 may include or be a metal material, such as silver, copper, or alloys thereof (e.g., a silver-copper alloy), or other suitable conductive materials. The thickness of the conductive sheet 112 may be 5 to 100 microns (e.g., 10 to 50 microns). In some embodiments, the conductive sheet 112 may include a surface treatment layer (not shown) covering its surface. The surface treatment layer is used to prevent the conductive sheet 112 from rusting (sulfurization or oxidation) due to contact with air under normal conditions. The surface treatment layer may include an organic solderability preservative (OSP) or a metal film such as Ni, Ni/Pd, Ni/Au, Ni/Pd/Au, or bare copper.

In detail, the bonding process may include placing the conductive sheet 112 and performing a sintering process. For example, as shown in FIG4 , first, the first end 1121 of the conductive sheet 112 is bonded to the first metal film 106 through the first sintering layer 108. At the same time, the second end 1122 of the conductive sheet 112 is bonded to the second metal film 206 through the second sintering layer 208. In some embodiments, the conductive sheet 112 may be a flat structure or a non-flat structure, and the specific form may be set according to design requirements. For example, when the first sintering layer 108 is at a higher level and the second sintering layer 208 is at a lower level, the conductive sheet 112 may have multiple turning points to facilitate bonding, as shown in FIG4 .

Next, a sintering process is performed to form the first sintering paste 1080 and the second sintering paste 2080 into the first sintering layer 108 and the second sintering layer 208, respectively, and complete the internal connection between the chip 102 and the carrier 302. In some embodiments, the sintering process can be performed under vacuum, a protective atmosphere (e.g., an inert gas, a reducing gas, or a combination thereof), or atmospheric air. The sintering process can be performed at a temperature of 100°C to 300°C (e.g., 150°C to 240°C) for 5 to 60 minutes. If the temperature is below 100°C, the sintering reaction may be incomplete, and if the temperature is above 300°C, the thermal stress generated may cause damage to the chip 102. Sintering bonding can be completed within the above time. If heating is continued for a long time (for example, more than 60 minutes), the chip 102 may be damaged. In addition, the sintering process may include applying a compressive stress of 0 to 30 MPa to the package structure 100 to help improve the bonding effect.

In this way, the first end 1121 of the conductive sheet 112 can be electrically connected to the chip 102 via the first metal film 106, and the second end 1122 of the conductive sheet 112 can be electrically connected to the carrier 302 via the second metal film 206. It should be noted that because the conductive sheet 112 has already interconnected the chip 102 and the carrier 302, the conventional wire bonding process can be omitted to avoid cracking of the chip 102 due to the applied load during the wire bonding process. As shown in Figure 4, the first sintered layer 108 is disposed between the first metal film 106 and the first end 1121 of the conductive sheet 112 and is in direct contact with the first metal film 106, while the second sintered layer 208 is disposed between the second metal film 206 and the second end 1122 of the conductive sheet 112 and is in direct contact with the second metal film 206.

The package structure 100 disclosed herein comprises a first metal film 106 (including a first nanocrystalline structure) and a second metal film 206 (including a second nanocrystalline structure). Due to the high diffusion capacity of the atoms in the high-density (111) crystal orientation on the surfaces of the first and second nanocrystalline structures, the conductive sheet 112 can be sintered and bonded to the chip 102 and the carrier 302 at a low temperature below 240°C through the first sintering layer 108 and the second sintering layer 208, respectively, to avoid damage to the chip 102 caused by extremely high thermal stress. This thermal stress is caused by the difference in thermal expansion coefficient between the conductive sheet 112 and the chip 102.

Furthermore, after sintering, the porosity of the first sintered layer 108 and the second sintered layer 208 can be less than approximately 10% (e.g., less than approximately 3%) and their strength can be enhanced (e.g., the bonding strength is greater than approximately 20 MPa). This improves the electrical and thermal conductivity of the package structure 100, as well as the bonding strength between the conductive sheet 112, the chip 102, and the carrier 302. This allows the bonding strength of the package structure 100 after low-temperature sintering to meet currently accepted industry standards. Furthermore, this prevents these voids from connecting into cracks, which could cause the first sintered layer 108 and the second sintered layer 208 to crack or peel. Unless otherwise defined, the term "porosity" refers to the ratio of the total cross-sectional area of pores to the cross-sectional area of the first sintered layer 108 and the second sintered layer 208, where the cross-sectional area is calculated by analyzing cross-sectional images obtained using a scanning electron microscopy (SEM) image using commercial software (e.g., Fiji ImageJ software).

As shown in FIG. 4 , the package structure 100 disclosed herein includes a chip 102, a first metal film 106 disposed above the chip 102 and having a first nanocrystalline structure, a first sintered layer 108 disposed on the first metal film 106 and in direct contact with the first metal film 106, and a conductive sheet 112 disposed on the first sintered layer 108 and electrically connected to the chip 102 via the first metal film 106.

It should be understood that after the bonding process is completed, subsequent packaging processes can be performed according to actual needs to complete the production of the package structure 100. Since it is not related to the focus of this disclosure, it will not be described in detail here.

The following describes the test results of some experimental examples of the packaging structures disclosed in this disclosure.

Experimental example: SiC/Ti/nt-Ag/Ag/Cu structure

Figure 5 shows a cross-sectional image of an experimental example structure obtained using a scanning electron microscopy (SEM) according to an experimental example of the present disclosure. The experimental example SiC/Ti/nt-Ag/Ag/Cu structure is an example of the package structure 100 shown in Figure 4. Specifically, a 0.1-micron thick titanium (adhesion layer 104) and silver nano-twinned (NT) crystals (first metal film 106) were sequentially sputter-deposited on a silicon carbide (wafer 102). Subsequently, a copper sheet (conductive sheet 112) was bonded to the silver nano-twinned (first metal film 106) via a silver sintering paste (first sintering layer 108).

[ Porosity and bond strength measurements ]

The experimental example structure was pre-sintered (at 100°C for 10 minutes). A compressive stress of 15 MPa was then applied to the structure and the sintering temperature was maintained at 250°C for 60 minutes to complete the sintering process (i.e., the sintered paste formed a sintered layer). Next, cross-sectional images of the experimental example structure obtained using SEM were analyzed using Fiji ImageJ software to calculate the porosity. The bond strength (also known as shear strength) was measured using a DAGE 4000 bond tester manufactured by Nordson. The results showed that the porosity of the silver sintered layer (first sintered layer 108) was approximately 2.3%, and the bond strength reached approximately 51.7 MPa.

In summary, some embodiments of the present disclosure provide some benefits. The present disclosure provides a packaging structure having a nanocrystalline structure and a method for manufacturing the same. Due to the excellent atomic high diffusion ability of the surface of the nanocrystalline structure, it can assist the chip and the conductive sheet to complete sintering bonding at low temperature and achieve internal connection, so as to avoid chip damage caused by extremely high thermal stress. In addition, the porosity of the sintered layer can be reduced and its strength can be improved, thereby improving the conductivity and thermal conductivity of the packaging structure, as well as the bonding strength between the chip and the conductive sheet, so that the bonding strength of the packaging structure after low-temperature sintering can reach the current industry-accepted standards. Furthermore, these holes can be prevented from connecting into cracks and causing the sintered layer to peel off.

The above overview of several embodiments is provided to facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that they can design or modify other processes and structures based on the present invention to achieve the same objectives and/or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

100: Package structure 102: Chip 102F: Surface 1021: Pad 1022: Dielectric layer 104: Adhesive layer 106: First metal film 108: First sintering layer 1080: First sintering paste 112: Conductive sheets 1121, 1122: Terminals 206: Second metal film 208: Second sintering layer 2080: Second sintering paste 302: Carrier 304, 304a, 304b: Copper pads

The following will describe in detail various aspects of the present disclosure with the help of the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the components of the present invention. It should also be noted that the accompanying figures only illustrate typical embodiments of the present disclosure and should not be considered as limiting its scope. The present disclosure can also be applied to other embodiments. Figures 1 to 3 are cross-sectional views of the packaging structure formed at different stages of the manufacturing process according to some embodiments of the present disclosure. Figure 4 is a partial cross-sectional view of the packaging structure according to some embodiments of the present disclosure. Figure 5 is a cross-sectional view of the experimental example structure obtained using a scanning electron microscope according to an experimental example of the present disclosure.

100:Packaging structure

102: Chip

1021: Welding pad

1022: Dielectric layer

104: Adhesive layer

106: First Metal Film

108: First sintered layer

112: Conductive sheet

1121, 1122: End

206: Second metal film

208: Second sintered layer

302: Carrier Board

304, 304a, 304b: Copper pads

Claims (10)

A package structure includes: a chip; a first metal film disposed above the chip, wherein the first metal film has a first nanocrystalline structure; a first sintered layer disposed on and in direct contact with the first metal film; and a conductive sheet disposed on the first sintered layer and electrically connected to the chip via the first metal film. The package structure as described in claim 1, wherein the first metal film includes silver, copper or an alloy thereof, and the thickness of the first metal film is 1 micron to 10 microns. The package structure as described in claim 1, wherein the first nanocrystalline structure has a parallel-arranged twin grain boundary, the spacing between the parallel-arranged twin grain boundaries is 1 nm to 50 nm, and in a cross-sectional metallographic image of the first metal film, the parallel-arranged twin grain boundaries account for more than 50% of the total grain boundaries. The package structure of claim 1, wherein the first sintered layer has a porosity of less than about 10%. The package structure as described in claim 1, wherein the chip includes a power integrated circuit chip, and the power integrated circuit chip includes a silicon chip, a silicon carbide chip or a gallium nitride chip. The package structure as described in claim 1, wherein the chip further includes: a pad disposed on an upper surface of the chip; and a dielectric layer disposed on the same layer as the pad. The packaging structure as described in claim 1 further includes an adhesive layer located between the first metal film and the chip, wherein the adhesive layer includes tungsten, titanium, chromium or an alloy thereof, and the thickness of the adhesive layer is 0.1 micron to 0.9 micron. The package structure as described in claim 1, wherein the conductive sheet comprises silver, copper or a silver-copper alloy, and the thickness of the conductive sheet is 10 microns to 100 microns. The package structure as described in claim 1 further includes a carrier located under the chip, wherein a first end of the conductive sheet is electrically connected to the chip, and a second end of the conductive sheet is electrically connected to the carrier. The packaging structure as described in claim 9 further includes: a second metal film, which is spaced apart from the chip and is arranged above the carrier, wherein the second metal film has a second nanocrystalline structure; a second sintered layer, which is arranged between the second metal film and the second end of the conductive sheet and is in direct contact with the second metal film, wherein the conductive sheet is electrically connected to the carrier via the second metal film.