TWM672839U - Pre-sintered sheet structure - Google Patents

Abstract

A pre-sintered sheet structure is provided. The pre-sintered sheet structure includes at least a pre-sintered sheet and at least a nano-twinned layer disposed on the pre-sintered sheet. The pre-sintered sheet structure further includes a metal conductive sheet disposed on one side of the pre-sintered sheet, opposite to the nano-twinned layer.

Description

Pre-sintered sheet structure

The present invention relates to a sintering method for die bonding and interconnect bonding technology, and more particularly to a pre-sintered wafer structure suitable for die bonding and interconnect bonding.

The inverter in an electric vehicle's motor control unit is the most critical component for converting electrical energy into kinetic energy. The power electronics module is the most crucial component influencing electrical energy conversion efficiency. Automotive motor power modules have voltage and current specifications of 600V/450A, significantly higher than those of conventional power modules and consumer electronic integrated circuits (ICs). Furthermore, they must pass various automotive-grade AEC-Q101 reliability tests, placing extremely high demands on packaging technology and materials.

Power module packaging involves bonding a surface-metallized ceramic substrate or printed circuit board (PCB) to a metal heat sink, then securing a power IC chip to the ceramic substrate or PCB. This is known as die bonding. Generally, the ceramic substrate or PCB surface has a copper conductive layer. Die bonding uses a solder-tin alloy, limiting the operation of the resulting power module chip to temperatures below the solder melting point and resulting in poor strength and reliability. Silver or copper sintering pastes are now becoming increasingly popular.

After the power module package completes the die bonding between the chip and the substrate, it is necessary to interconnect the pads on the power IC chip and the copper conductive layer of the ceramic substrate or printed circuit board to provide signal and power transmission. Ultrasonic bonding is usually performed using thick aluminum wire or aluminum strip. However, the melting point of thick aluminum wire or aluminum strip is relatively low (for example, below 700°C), the strength is low, and the reliability is poor. Based on this, the packaging industry currently tends to use thick copper wire, copper strip, thick silver wire, and silver strip with higher hardness and strength for ultrasonic wire bonding. However, when using thick copper wire, copper strip, thick silver wire, and silver strip for ultrasonic wire bonding, it often causes the power IC chip to crack. Known solutions include: using silver sintering to bond a copper plate to the pads above the chip as a stress-resistant metal layer (die-top metallization) to buffer the applied load of ultrasonic wire bonding; and also using silver sintering to connect the chip to a copper conductive layer on a ceramic substrate or printed circuit board. Another method for interconnecting power modules is to use a metal conductive sheet directly sintered to the pads above the chip and the copper electrodes on the ceramic substrate (clip bonding).

However, whether in the interconnect packaging process involving sintering die bonding, ultrasonic bonding of the metal layer above the chip, or sintering copper plates, the high temperatures required for sintering (e.g., above 250°C) generate thermal stress, creating a significant risk of damage. A sintered layer porosity greater than 15% results in poor electrical and thermal conductivity, and bond strength is generally less than 25 MPa. Furthermore, when using sintering paste for die bonding or interconnects, it is prone to overflow during pressurized sintering, making it difficult to easily control the thickness of the sintered layer. These are pressing challenges facing power module packaging.

In one embodiment, a pre-sintered sheet structure is provided. The pre-sintered sheet structure includes at least one pre-sintered sheet and at least one nanocrystalline layer disposed on the pre-sintered sheet.

The following invention provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are directly in contact, and it may also include an embodiment in which additional elements are formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeatedly reference numbers and/or letters in various examples. Such repetition is for the purpose of brevity and clarity and is not intended to indicate the relationship between the different embodiments and/or configurations discussed.

The following describes some variations of the embodiments. Similar reference numerals are used to designate similar elements throughout the various figures and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, or after the method, and that some of the described steps may be replaced or deleted in other embodiments of the method.

Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used to facilitate describing the relationship of one component or components to another component or components in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, spatially relative adjectives used therein will also be interpreted based on the rotated orientation.

The terms used herein are intended only to illustrate specific embodiments and are not intended to limit the present inventive concept. Unless the context clearly indicates a different meaning, expressions used in the singular also encompass expressions in the plural. Throughout this specification, it should be understood that terms such as "comprise," "have," and "include" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed herein, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or be added.

The following describes some embodiments of the present invention. Additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or eliminated in different embodiments. Additional components may be added to the package structure. Some of the components may be replaced or eliminated in different embodiments. Although some embodiments are discussed as performing steps in a specific order, these steps may also be performed in another logical order.

In recent years, automotive high-power module packaging has begun using silver or copper sintering pastes for die-bonding. However, the authors of this case discovered that because the sintering temperature of silver or copper sintering pastes is approximately 250°C or higher, the thermal stress generated can easily damage the power module. Furthermore, the resulting sintered layer has a porosity greater than 15%, which can reduce electrical and thermal conductivity and result in a bond strength of less than 25 MPa. Furthermore, the authors of this case discovered that during die-bonding, the sintering paste easily overflows during the pressurized sintering process, making it difficult to easily control the thickness of the sintered layer.

Interconnect technology is a technique used in electronic packaging to connect the chip and substrate using a conductive material. For interconnects between the pads on the power IC chip and the copper conductive layer of a ceramic substrate or printed circuit board, thick metal wire or ribbon with a thickness of 200 microns (μm) or greater is primarily used. Ultrasonic bonding is used to bond the thick metal wire or ribbon to the pads on the chip, resulting in low cost and high production efficiency. However, conventional thick aluminum wire or ribbon, due to its low melting point (e.g., below 700°C), cannot meet the higher current and voltage requirements of power modules.

In recent years, the packaging industry has begun experimenting with thick copper wire or copper ribbon, or thick silver wire or silver ribbon. These materials not only offer superior electrical and thermal conductivity compared to thick aluminum wire or aluminum ribbon, but also offer superior strength and reliability. However, thick copper wire, copper ribbon, thick silver wire, and silver ribbon are all much harder than thick aluminum wire or aluminum ribbon, resulting in frequent cracking of power IC chips during ultrasonic wire bonding.

One known solution (U.S. Patent No. 8164176B2) involves depositing a copper film thicker than 10 microns on the power IC chip to cushion the load applied during ultrasonic wire bonding of thick copper wire or copper strip, thereby preventing chip cracking. However, the inventors of this application discovered that depositing a copper film thicker than 10 microns on the chip surface can easily cause peeling between the film and the chip, leading to failure of ultrasonic wire bonding of thick copper wire or copper strip.

Another known solution involves sintering silver to bond a copper plate to the pads of the power IC chip, creating a stress-resistant layer to block the applied load of ultrasonic wire bonding. However, the authors of this case discovered that silver sintering requires temperatures exceeding 250°C. The difference in thermal expansion coefficients between the copper plate and the chip creates extremely high thermal stress, leading to damage to the power chip and module. Fracture of the chip's aluminum pad is the most common failure mode. Furthermore, the sintered silver paste contains numerous voids, reducing electrical and thermal conductivity and bonding strength. In particular, the numerous voids in the sintered layer near the chip can form cracks, easily leading to delamination at the bonding interface.

Another known solution (U.S. Patent US10347566B2) is to silver-sinter a thick copper plate (Cu clip bonding) on top of the chip and then directly connect this thick copper plate to the copper pad on the ceramic substrate using silver sintering. However, the inventors of this case found that since the sintering temperature is above approximately 250°C, the thermal stress generated can easily cause damage to the power module. In addition, the porosity of the sintered layer obtained after sintering is greater than 15%, making the bonding strength less than 25MPa. In addition, during the internal wiring process, the sintering paste easily overflows during the pressure sintering process, and the thickness of the sintered layer cannot be easily controlled. The purpose of this invention is to provide a pre-sintered sheet structure and a manufacturing method thereof to solve at least one of the above problems.

To this end, the present invention provides a pre-sintered sheet structure having a nano-twinned (NT) structure and a manufacturing method thereof. By pre-forming into a pre-sintered sheet structure through a pre-sintering process, and then applying this pre-sintered sheet structure to solid crystal bonding and internal connection bonding, the problem of overflow due to pressure sintering can be avoided, and the thickness of the sintered layer can be easily controlled. In addition, due to the excellent atomic high diffusion ability of the surface of the nano-twinned structure, the process temperature of the formal sintering process can be reduced, thereby completing the sintering bonding at a low temperature to avoid chip damage caused by extremely high thermal stress. In addition, low-temperature sintering can reduce the porosity of the sintered layer and increase its strength, thereby improving the conductivity, thermal conductivity and bonding strength of the sintered layer.

1A and 1B are cross-sectional views of a pre-fired sheet structure 10 at different stages of the manufacturing process according to the first embodiment of the present invention.

As shown in FIG1A , at least one pre-sintered sheet 100 is provided. In some embodiments, the thickness of the pre-sintered sheet 100 may be between 10 μm and 100 μm. The pre-sintered sheet 100 may contain silver particles or copper particles. The method for forming the pre-sintered sheet 100 includes, for example, applying a sintering material on a carrier, performing a pre-sintering process on the sintered material to pre-form the pre-sintered sheet, and peeling the pre-sintered sheet from the carrier to obtain the pre-sintered sheet 100. In some embodiments, the carrier is, for example, a glass plate, a ceramic plate, or a metal plate. The sintering material may be a sintering paste including metal powder (e.g., silver powder or copper powder). Specifically, the sintering paste may be composed of metal powder and additives (e.g., flux and binder). In some embodiments, the particle size of the metal powder may be from about 0.1 micron to about 50 microns, or from about 0.1 micron to about 10 microns, or from about 0.1 micron to about 1 micron. In some embodiments, the method of applying the sintering material is, for example, rotary coating, slurry coating (Docter blade plating), or cylindrical nozzle spraying. In some embodiments, the pre-sintering process is performed at a temperature of, for example, about 50°C to about 150°C for 1 minute to 30 minutes. In addition, the pre-sintering process may include applying a compressive stress of 0 to 30 MPa to the sintered material. The pre-sintering process can be used to sinter out additives such as flux and adhesive contained in the sintered material, and the metal powder in the sintered material has not been sintered or is slightly sintered after the pre-sintering process. In some embodiments, FIG11A is a partial cross-sectional view obtained using a scanning electron microscopy (SEM) according to an experimental example of the present invention, showing the structure of a silver (Ag) pre-sintered sheet. The silver pre-sintered sheet is an example of the pre-sintered sheet 100 of FIG1A.

As shown in FIG1B , at least one nanocrystalline layer 110 is formed on the pre-sintered wafer 100. In this manner, a pre-sintered wafer structure 10 is obtained. The nanocrystalline structure of the nanocrystalline layer 110 has parallel-aligned nanocrystalline boundaries, with the spacing between the parallel-aligned nanocrystalline boundaries ranging from 1 nm to 50 nm (e.g., 2 nm to 10 nm). Generally speaking, the smaller the spacing between the parallel-aligned nanocrystalline boundaries, the higher the hardness of the nanocrystalline layer 110. In a cross-sectional metallographic image of the nanocrystalline layer 110, the parallel-aligned nanocrystalline boundaries account for more than 50% (e.g., more than 60%, more than 70%, more than 80%, or more than 90%) of the total grain boundaries. It should be noted that the nano-membrane structure of the nano-membrane layer 110 can be uniformly or step-wise distributed in the nano-membrane layer 110, or the nano-membrane structure can be concentrated in the region of the nano-membrane layer 110 adjacent to the pre-sintered sheet 100, while the remaining portion is still a random grain, and the thickness of the region accounts for 10% to 100% of the total thickness of the nano-membrane layer 110. The nano-membrane structure at the interface between the nano-membrane layer 110 and the pre-sintered sheet 100 has a high density (111) crystal orientation and a high diffusion ability of atoms, thus helping to reduce the process temperature of the subsequent formal sintering process, thereby completing the sintering bonding at a low temperature. This part will be explained in detail later in the text with reference to Figure 7.

Twin structures form when accumulated strain energy within a material drives the uniform shearing of atoms in a region to positions that are mirror-symmetrical with the unsheared atoms within the grain. Twins are classified into three types: annealing twins, mechanical twins, and nano-twins. The interface between these symmetrical twins is the twin boundary.

Twins primarily occur in materials with the densest lattice arrangement, face-centered cubic (FCC) or hexagonal closed-packed (HCP). In addition to the densest lattice arrangement, materials with smaller stacking fault energies are generally more likely to form twins. The main characteristic of the nano-twins developed in this study is that twin grains with a thickness of multiple nanometers are stacked in parallel, and the twin interfaces of each twin grain have a (111) crystal orientation.

Twin grain boundaries are coherent crystal structures and belong to the low-energy Σ3 and Σ9 special grain boundaries. The crystal orientation is the {111} plane. Compared with the high-angle grain boundaries formed by general annealing recrystallization, the interface energy of twin grain boundaries is about 5% of that of general high-angle grain boundaries. Due to the lower interface energy of twin grain boundaries, they can avoid becoming paths for oxidation, sulfidation and chloride ion corrosion. Therefore, they exhibit better oxidation resistance and corrosion resistance. In addition, the symmetrical lattice arrangement of this twin crystal has less resistance to electron transmission. Therefore, they exhibit better electrical and thermal conductivity. Because the twin grain boundaries hinder the movement of dislocations, the material can still maintain high strength. This characteristic of both high strength and high conductivity has been confirmed in copper thin films.

In terms of high-temperature stability, due to their lower interfacial energy, twin grain boundaries are more stable than typical high-angle grain boundaries. Twin grain boundaries themselves are less mobile at high temperatures and also lock the surrounding high-angle grain boundaries, preventing them from moving. Consequently, the overall grain size exhibits no significant grain growth at high temperatures, maintaining the material's high-temperature strength. Regarding reliability when current is applied, the diffusion rate of atoms through or across low-energy twin grain boundaries is lower. When using electronic products, the high current density associated with the movement of atoms within the wire is also more difficult. This solves the electromigration problem that often occurs when current is applied to wires. In copper thin films, it has been reported that polycrystalline can suppress the electrical migration of materials.

In some embodiments, the nanocrystalline layer 110 may include or be silver, copper, or a silver-copper alloy. The thickness of the nanocrystalline layer 110 may be approximately 0.1 micrometers to approximately 100 micrometers (e.g., approximately 0.1 micrometers to approximately 20 micrometers, or approximately 0.1 micrometers to approximately 10 micrometers). When the thickness of the nanocrystalline layer 110 is within this range, it can effectively block the load during ultrasonic wire bonding, thereby preventing chip cracking.

In some embodiments, the nanocrystalline layer 110 can be formed by sputtering, evaporation, or electroplating. According to some embodiments, the sputtering is performed using a single-gun sputtering process or a multi-gun co-plating process. The sputtering power source can be, for example, direct current (DC), pulsed DC, radio frequency (RF), high-power impulse magnetron sputtering (HIPIMS), etc. The sputtering power of the nanocrystalline layer 110 can be, for example, about 100W to about 500W. The sputtering process temperature is room temperature, but the sputtering process temperature will rise by about 50°C to about 200°C. The deposition rate of the nanocrystal layer 110 can be, for example, approximately 0.5 nm/s to approximately 3 nm/s. The sputtering background pressure can be less than 1×10 ⁻⁵ torr, and the operating pressure can be, for example, approximately 1×10 ⁻³ torr to 1×10 ⁻² torr. The argon flow rate can be approximately 10 sccm to approximately 20 sccm. The stage rotation speed can be, for example, approximately 5 rpm to approximately 20 rpm. Preferably, a bias voltage of approximately -100 V to approximately -500 V (e.g., -150 V or -300 V) can be applied to the substrate during the sputtering process to form high-density nanocrystals. If the bias voltage is lower than -100V or higher than -500V, the nanocrystal density of the sputtered metal film will be less than 50%, and low-temperature sintering bonding will not be achieved.

According to other embodiments, the nanocrystalline layer 110 can be formed on the pre-sintered wafer 100 by evaporation. In some embodiments, the background pressure of the evaporation process is less than 1× ^10⁻⁵ torr, the operating pressure can be, for example, approximately 1× ^10⁻⁴ torr to approximately 5× ^10⁻⁴ torr, and the argon flow rate can be approximately 2 sccm to approximately 10 sccm. The stage rotation speed can be, for example, approximately 5 rpm to approximately 20 rpm. The deposition rate of the nanocrystalline layer 110 can be, for example, approximately 1 nm/s to approximately 5.0 nm/s. Preferably, during the evaporation process, ion impact can be applied to the nanocrystal layer 110 at a voltage of approximately 10V to approximately 300V (e.g., 100V or 200V) and a current of approximately 0.1A to approximately 1.0A (e.g., 0.3A or 0.8A) to form high-density nanocrystals. If the ion impact voltage is lower than 10V or higher than 300V, or the current is lower than 0.1A or higher than 1.0A, the nanocrystal density of the evaporated metal film will be less than 50%, and low-temperature sintering bonding will not be achieved.

According to some other embodiments, the nanocrystal layer 110 can be formed by electroplating. Preferably, the plating solution is stirred at a speed of 500 rpm to 3000 rpm (e.g., 1000 rpm or 2000 rpm) during the electroplating process to form high-density nanocrystals. If the plating solution is stirred at a speed lower than 500 rpm or higher than 3000 rpm, the nanocrystal density of the sputtered metal film will be less than 50%, and low-temperature sintering bonding will not be achieved.

As shown in FIG1B , the pre-sintered wafer structure 10 includes at least one pre-sintered wafer 100 and at least one nanocrystalline layer 110 disposed on the pre-sintered wafer 100. In some embodiments, the pre-sintered wafer structure 10 can be used for die-bonding a chip or interconnecting a substrate. The pre-sintered wafer structure 10 having the pre-sintered wafer 100 can avoid the problem of sintering material overflow during the main sintering (e.g., pressure sintering), thereby easily controlling the thickness of the sintered layer obtained after the main sintering. This will be explained in detail later in conjunction with FIG7 . In some embodiments, FIG. 11B is a partial cross-sectional view of a pre-fired silver sheet structure having a silver nanocrystalline layer formed on one side thereof, obtained using a scanning electron microscope, according to an experimental example of the present invention. This pre-fired sheet structure is an example of the pre-fired sheet structure 10 of FIG. 1B .

In some embodiments, the pre-sintered wafer 100 has a first surface 100a and a second surface 100b, wherein the first surface 100a may be the surface closer to the wafer side in subsequent applications (e.g., as shown in Figures 7 to 10), and the second surface 100b is opposite to the first surface 100a. The nanocrystalline layer 110 may be disposed on the first surface 100a of the pre-sintered wafer 100. In other embodiments, the nanocrystalline layer 110 may also be disposed on the second surface 100b of the pre-sintered wafer 100. In other words, the nanocrystalline layer 110 may be disposed on only one side of the pre-sintered wafer 100, but the present invention is not limited thereto. In other embodiments, nanocrystalline layers may be disposed on both opposite surfaces 110a/100b of the pre-sintered sheet 100 according to actual application requirements (e.g., as shown in FIG. 2 ).

Figure 2 is a partial cross-sectional view of a pre-fired wafer structure 20 according to a second embodiment of the present invention. It should be noted that identical or similar components to those in the previous embodiment will retain the same reference numerals, and their details will not be repeated. Pre-fired wafer structure 20 differs from pre-fired wafer structure 10 in that a second nanocrystal layer 210 is further disposed on the second surface 100b of pre-fired wafer 100.

In some embodiments, as shown in FIG. 2 , after forming a nanomesh layer 110 (or referred to as the first nanomesh layer 110) on the first surface 100a of the pre-sintered sheet 100, a second nanomesh layer 210 is formed on the second surface 100b of the pre-sintered sheet 100. In this way, a pre-sintered sheet structure 20 can be obtained. In other embodiments, the second nanomesh layer 210 can be formed first, followed by the first nanomesh layer 110, but the present invention is not limited thereto. In some embodiments, the thickness of the second nanomesh layer 210 can be from about 0.1 microns to about 100 microns, or from about 0.5 microns to about 20 microns (e.g., 1 micron, 4 microns, 8 microns, 10 microns, or 15 microns). If the thickness of the second nanocrystalline layer 210 is within the above range, it can effectively block the load during ultrasonic wire bonding to prevent chip cracking. The second nanocrystalline layer 210 can include the same or similar materials and structures as the first nanocrystalline layer 110. For the sake of simplicity, its detailed description is omitted here.

The pre-sintered wafer structure 20 of this embodiment includes a pre-sintered wafer 100, a first nanocrystalline layer 110, and a second nanocrystalline layer 210. In some embodiments, the first nanocrystalline layer 110 is disposed on the first surface 100a of the pre-sintered wafer 100, while the second nanocrystalline layer 210 is disposed on the second surface 100b of the pre-sintered wafer 100. In some embodiments, the pre-sintered wafer structure 20 can be used for die bonding a chip or for interconnect bonding to a carrier. The pre-sintered wafer structure 20 includes the pre-sintered wafer 100, thereby avoiding the problem of sintered material overflow during the main sintering (e.g., pressure sintering), thereby easily controlling the thickness of the sintered layer obtained after the main sintering. In some embodiments, FIG12 is a partial cross-sectional view of a pre-fired silver sheet structure having silver nanocrystalline layers disposed on opposite sides thereof, obtained using a scanning electron microscope, according to an experimental example of the present invention. This pre-fired sheet structure is an example of the pre-fired sheet structure 20 of FIG2 .

Figures 3A and 3B are cross-sectional views of a pre-fired sheet structure 30 at different stages of the manufacturing process according to a third embodiment of this invention. In this embodiment, the pre-fired sheet structure 30 also includes a metal conductive sheet 300. It should be noted that the same or similar components as those in the previous embodiments will be designated by the same reference numerals, and their details will not be repeated.

As shown in FIG3A , a metal conductive sheet 300 is provided. In some embodiments, the thickness of the metal conductive sheet 300 may be about 10 microns to about 100 microns. In some embodiments, the metal conductive sheet 300 is, for example, a copper sheet, a nickel sheet, a silver sheet, or a gold foil.

Next, the pre-sintered sheet 100 is bonded to the metal conductive sheet 300. In some embodiments, the pre-sintered sheet 100 can be bonded to the metal conductive sheet 300 using a coating process and a pre-sintering process. For example, a sintering material can be applied to the surface of the metal conductive sheet 300 through a coating process, and then a pre-sintering process is performed to pre-shape the sintered material into the pre-sintered sheet 100. In this way, the pre-sintered sheet 100 can be bonded to the surface of the metal conductive sheet 300. The sintering material, coating process and/or pre-sintering process may adopt the same or similar materials and/or methods as the sintering material, coating method and/or pre-sintering process described above, and their detailed description is omitted here for the sake of simplicity.

As shown in FIG3B , a nanocrystalline layer 110 is formed on the side of the pre-sintered wafer 100 opposite the metal conductive sheet 300. In this manner, a pre-sintered wafer structure 30 is obtained. In this embodiment, the pre-sintered wafer structure 30 differs from the pre-sintered wafer structure 10 in that the pre-sintered wafer structure 30 further includes a metal conductive sheet 300 disposed on the side of the pre-sintered wafer 100 opposite the nanocrystalline layer 110. In other words, while the nanocrystalline layer 110 is disposed on the first surface 100a of the pre-sintered wafer 100, the metal conductive sheet 300 can be disposed on the second surface 100b of the pre-sintered wafer 100, but the present invention is not limited thereto.

The pre-sintered sheet structure 30 of this embodiment can be used for die-bonding a chip or bonding interconnects to a carrier. The pre-sintered sheet structure 30 includes a pre-sintered sheet 100, which prevents overflow of sintered material during the main sintering process (e.g., pressurized sintering), thereby easily controlling the thickness of the sintered layer obtained after the main sintering process. Furthermore, the pre-sintered sheet structure 30 also includes a nanocrystalline layer 110 and a metal conductive sheet 300, which can be used to block or reduce the applied load during interconnect bonding (e.g., ultrasonic wire bonding), thereby preventing problems such as chip cracking. In some embodiments, FIG13 is a partial cross-sectional view of a pre-fired sheet structure, obtained using a scanning electron microscope, obtained according to an experimental example of the present invention, in which a silver pre-fired sheet and a silver nanocrystalline layer are sequentially disposed on a copper plate. This pre-fired sheet structure is an example of the pre-fired sheet structure 30 of FIG3B .

Figures 4A and 4B illustrate cross-sectional views of a pre-sintered sheet structure 40 at various stages of the fabrication process according to a fourth embodiment of this invention. In this embodiment, pre-sintered sheet structure 40 includes both pre-sintered sheets and nanocrystalline layers formed on both sides of the metal conductive sheet 300. It should be noted that identical or similar components to those in the previous embodiments will retain the same reference numerals, and their details will not be repeated.

As shown in FIG4A , a metal conductive sheet 300 is provided. Subsequently, a pre-sintered sheet 100 (or referred to as a first pre-sintered sheet 100 ) and a second pre-sintered sheet 400 are bonded to opposite sides of the metal conductive sheet 300 (e.g., a first side 300 a and a second side 300 b ). In some embodiments, the first pre-sintered sheet 100 is bonded to the first side 300 a of the metal conductive sheet 300 , while the second pre-sintered sheet 400 is bonded to the second side 300 b of the metal conductive sheet 300 . In some embodiments, the thickness of the second pre-sintered sheet 400 may be between 10 microns and 100 microns. The second pre-sintered sheet 400 may comprise the same or similar material as the first pre-sintered sheet 100 ; a detailed description thereof is omitted for simplicity.

In some embodiments, a coating process and a pre-sintering process can be used to bond the first pre-sintered sheet 100 to the first side 300a of the metal conductive sheet 300, and the second pre-sintered sheet 400 to the second side 300b. For example, after forming the first pre-sintered sheet 100 on the first side 300a of the metal conductive sheet 300, the first pre-sintered sheet 100 and the metal conductive sheet 300 can be flipped (i.e., with the second side 300b facing upward), and the second pre-sintered sheet 400 can be formed on the second side 300b using the same or similar coating process and pre-sintering process.

As shown in FIG4B , a nanocrystalline layer 110 (or third nanocrystalline layer 110 ) is formed on the side of the first pre-sintered sheet 100 opposite the metal conductive sheet 300 , and a fourth nanocrystalline layer 410 is formed on the side of the second pre-sintered sheet 400 opposite the metal conductive sheet 300 . In this way, a pre-sintered sheet structure 40 is obtained. In this embodiment, the difference between the pre-sintered sheet structure 40 and the pre-sintered sheet structure 30 is that the pre-sintered sheet structure 40 further includes a second pre-sintered sheet 400 and a fourth nanocrystalline layer 410, which are disposed on a side of the metal conductive sheet 300 opposite to the first pre-sintered sheet 100 (e.g., the second side 300b).

The pre-sintered sheet structure 40 of this embodiment can be used for die-bonding a chip or bonding interconnects to a carrier. The pre-sintered sheet structure 40 comprises a first pre-sintered sheet 100 and a second pre-sintered sheet 400. This prevents overflow of sintered material during the main sintering process (e.g., pressurized sintering), thereby easily controlling the thickness of the sintered layer obtained after the main sintering process. Furthermore, the pre-sintered sheet structure 40 further includes a metal conductive sheet 300, which can be used to block or reduce the applied load during interconnect bonding (e.g., ultrasonic wire bonding), thereby preventing problems such as chip cracking.

Figures 5A and 5B are cross-sectional views of a pre-fired sheet structure 50 at various stages of the fabrication process according to a fifth embodiment of this invention. In this embodiment, pre-fired sheet structure 50 differs from pre-fired sheet structure 30 in that nanocrystalline layer 110 is sandwiched between pre-fired sheet 100 and metal conductive sheet 300. It should be noted that identical or similar components to those in the previous embodiments will retain the same reference numerals, and their details will not be repeated.

As shown in Figures 5A and 5B, a nanometer-sized crystal layer 110 can be first formed on a metal conductive sheet 300. Subsequently, a pre-sintered sheet 100 can be bonded to the side of the nanometer-sized crystal layer 110 opposite the metal conductive sheet 300. In this way, a pre-sintered sheet structure 50 can be obtained. The method for forming the nanometer-sized crystal layer and/or the method for bonding the pre-sintered sheet can be the same or similar to the method for forming the nanometer-sized crystal layer and the method for bonding the pre-sintered sheet described above. For the sake of simplicity, a detailed description thereof is omitted here.

The pre-sintered sheet structure 50 of this embodiment can be used for die-bonding a chip or bonding interconnects to a carrier. The pre-sintered sheet structure 50 includes a pre-sintered sheet 100, which prevents overflow of sintered material during the main sintering process (e.g., pressurized sintering), thereby easily controlling the thickness of the sintered layer obtained after the main sintering process. Furthermore, the pre-sintered sheet structure 50 also includes a metal conductive sheet 300, which can be used to block or reduce the applied load during interconnect bonding (e.g., ultrasonic wire bonding), thereby preventing problems such as chip cracking. In some embodiments, FIG14 is a partial cross-sectional view, obtained using a scanning electron microscope, of a pre-baked structure comprising a silver nanocrystalline layer and a silver pre-baked structure sequentially disposed on a copper plate, according to an experimental example of the present invention. This pre-baked structure is an example of the pre-baked structure 50 of FIG5B .

Figures 6A and 6B illustrate cross-sectional views of a pre-baked sheet structure 60 at various stages of the manufacturing process according to a sixth embodiment of this invention. Unlike pre-baked sheet structure 50, pre-baked sheet structure 60 does not include metal conductive sheet 300. It should be noted that components identical or similar to those in the previous embodiment will retain the same reference numerals, and their details will not be repeated.

As shown in FIG6A , a nanocrystalline layer 110 can be formed on a carrier 302. In some embodiments, the carrier 302 is, for example, a glass plate, a ceramic plate, or a metal plate. The method for forming the nanocrystalline layer can be the same or similar to the method for forming the nanocrystalline layer described above, and a detailed description thereof is omitted for simplicity.

As shown in FIG6B , the pre-sintered sheet 100 is bonded to the side of the nanomesh layer 110 opposite the carrier 302, and then the carrier 302 is debonded to obtain a pre-sintered sheet structure 60. In some embodiments, the pre-sintered sheet 100 can be bonded to the nanomesh layer 110 using a coating process and a pre-sintering process. For example, a sintering material can be coated on the surface of the nanomesh layer 110 through a coating process, and then a pre-sintering process is performed to pre-shape the sintered material into the pre-sintered sheet 100. In this way, the pre-sintered sheet 100 can be bonded to the surface of the nanomesh layer 110. The sintering material, coating process and/or pre-sintering process may adopt the same or similar materials and/or methods as the sintering material, coating method and/or pre-sintering process described above, and their detailed description is omitted here for the sake of simplicity.

In some embodiments, after forming the pre-fired sheet structure 60, another nano-membrane layer may be selectively formed on a side of the pre-fired sheet 100 opposite the nano-membrane layer 110, thereby obtaining a pre-fired sheet structure having nano-membrane layers on opposite sides of the pre-fired sheet 100, such as the pre-fired sheet structure 20 shown in FIG. 2 .

It should be understood that although the above examples illustrate the production of pre-fired sheet structures 10-60 from a single piece, in other embodiments, a large-scale pre-fired sheet structure may be produced first, and then, based on actual application requirements, pre-fired sheet structures of the desired size may be obtained through cutting processes (e.g., laser cutting, diamond blade cutting, etc.).

The following describes the application of the pre-fired wafer structure of the present invention in die bonding or interconnect bonding. Figures 7 to 10 are partial cross-sectional views of the pre-fired wafer structure in various applications according to some embodiments of the present invention.

FIG7 illustrates a partial cross-sectional view of a die-bonding structure 500 using a pre-sintered sheet structure 10. As shown in FIG7 , the pre-sintered sheet structure 10 can be used for die-bonding between a carrier 502 and a wafer 510, thereby forming the die-bonding structure 500. For example, a method for forming the die-bonding structure 500 may include placing the pre-sintered sheet structure 10 between the carrier 502 and the wafer 510 and performing a main sintering process to form a sintered sheet structure 10′. The wafer 510 may then be bonded to the carrier 502 via the sintered sheet structure 10′. In some embodiments, the die-bonding structure 500 may include a carrier 502, a sintered layer 100′ on the carrier 502, a nanocrystalline layer 110 on the sintered layer 100′, and a chip 510 on the nanocrystalline layer 110.

In some embodiments, the formal sintering process can be used to further sinter the metal powder that has not been sintered or is slightly sintered in the pre-sintered sheet 100 to form a sintered layer 100', thereby obtaining a sintered sheet structure 10'. Due to the presence of the nanocrystalline layer 110, the process temperature of the formal sintering process can be lowered, and the sintering bonding can be completed at a low temperature, thereby avoiding damage to the chip 510. In some embodiments, the sintered layer 100' may include or be silver, copper, or a silver-copper composite. In some embodiments, the formal sintering process is performed at a temperature of, for example, above about 200°C (for example, above about 250°C, or at about 150°C to about 300°C) for 5 minutes to 60 minutes. Furthermore, the main sintering process may include applying a compressive stress of 0 to 30 MPa to the pre-sintered sheet structure 10. Since the pre-sintered sheet structure 10 is already substantially solid and non-fluid, even if compressive stress is applied, overflowing can be avoided.

In some embodiments, the sintered layer 100' can act as a buffer to prevent interfacial cracking caused by direct bonding between the nanocrystalline layer 110 and the carrier 502, effectively improving the reliability of the packaged product. Because the pre-sintered sheet structure 10 has the nanocrystalline layer 110 formed on a single surface of the pre-sintered sheet 100, the porosity of the sintered layer 100' can be reduced to below 5% (e.g., below 3%) after sintering, and the bonding strength can be increased to above 30 MPa (e.g., approximately 40 MPa to approximately 50 MPa). In this way, the electrical and thermal conductivity of the sintered layer 100' and the bonding strength between the carrier 502 and the chip 510 can be improved. Alternatively, these pores can be prevented from connecting into cracks, which may cause the sintered layer 100' to crack or peel. Unless otherwise specified, the term "porosity" refers to the ratio of the total cross-sectional area of the pores to the cross-sectional area of the sintered layer 100'. The cross-sectional area is a value calculated by analyzing cross-sectional images obtained using a scanning electron microscopy (SEM) using commercial software (e.g., Fiji ImageJ software).

In some embodiments, carrier 502 may comprise a metal heat sink, which may comprise aluminum or copper. In other embodiments, carrier 502 may comprise a printed circuit board (PCB) coated with a copper circuit layer and a protective layer, or a ceramic substrate coated with a copper circuit layer and a protective layer. In some embodiments, the protective layer is located on the copper circuit layer to prevent rusting (sulfurization or oxidation) of the copper circuit layer from contact with air under normal conditions. In one embodiment, the protective layer may comprise an organic solderability preservative (OSP) or a metal film such as Ni, Ni/Pd, Ni/Au, or Ni/Pd/Au. In one embodiment, the ceramic substrate may include aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), or silicon nitride (Si ₃ N ₄ ).

In some embodiments, chip 510 may comprise a power IC chip, but the present invention is not limited thereto. In other embodiments, chip 510 is a chip for other purposes, such as a driver IC chip or a control IC chip. The power IC chip may comprise a silicon chip, a silicon carbide chip, or a gallium nitride chip, but the present invention is not limited thereto.

In some embodiments, before placing the pre-fired wafer structure 10, an adhesive layer 520 may be optionally formed on the surface of the wafer 510, and the wafer 510 may be bonded to the pre-fired wafer structure 10 via the adhesive layer 520. The adhesive layer 520 can provide better bonding strength between the wafer 510 and the nanocrystalline layer 110. In addition, the adhesive layer 520 has a lattice buffering effect. If the wafer 510 is directly bonded to the nanocrystalline layer 110, the nanocrystalline structure of the nanocrystalline layer 110 may be affected by the crystal orientation of the wafer 510. In some embodiments, the material of the adhesive layer 520 may include or be tungsten, titanium, chromium, alloys thereof, or other suitable adhesive materials. The thickness of the adhesive layer 520 is, for example, 0.1 micrometers to 0.9 micrometers. It should be understood that the thickness of the adhesive layer 520 can be appropriately adjusted according to the actual application, and the present invention is not limited thereto. The adhesive layer 520 can be formed on the surface of the chip 510 by sputtering, evaporation, or electroplating.

In some embodiments, FIG15 is a partial cross-sectional view of a die-bonding structure using a pre-sintered wafer structure to bond a silicon wafer, obtained using a scanning electron microscope, according to an experimental example of the present invention. This die-bonding structure is an example of the die-bonding structure 500 of FIG7 .

It is worth noting that although FIG. 7 illustrates an embodiment in which the pre-fired chip structure 10 is applied to die bonding, in other embodiments, one of the pre-fired chip structures 20 to 60 may be used instead of the pre-fired chip structure 10 (for example, as shown in FIG. 8 ).

FIG8 illustrates a partial cross-sectional view of a die-bonding structure 600 using a pre-sintered sheet structure 20. As shown in FIG8 , the pre-sintered sheet structure 20 can be used for die-bonding between a carrier 502 and a wafer 510, thereby forming the die-bonding structure 600. For example, a method for forming the die-bonding structure 600 may include placing the pre-sintered sheet structure 20 between the carrier 502 and the wafer 510 and performing a main sintering process to form a sintered sheet structure 20′. The wafer 510 may then be bonded to the carrier 502 via the sintered sheet structure 20′. In this embodiment, the difference from the die-bonding structure 500 is that in the die-bonding structure 600, a second nanocrystalline layer 210 is further interposed between the sintering layer 100' and the carrier 502.

FIG9 illustrates a partial cross-sectional view of a package structure 700 employing a pre-sintered sheet structure 10. As shown in FIG9 , the pre-sintered sheet structure 10 can be used to bond interconnects between a chip 510 and a carrier 702, thereby forming the package structure 700. For example, a method for forming the package structure 700 may include placing the chip 510 on a copper pad 704a of the carrier 702, and sequentially placing the pre-sintered sheet structure 10 and the metal foil 710 on the chip 510. A formal sintering process is then performed to form the sintered sheet structure 10′, such that the metal foil 710 can be bonded to the chip 510 via the sintered sheet structure 10′. An internal connection bonding process (e.g., ultrasonic bonding process) can be used to bond the internal connection conductor 720 to the metal foil 710 and the copper pad 704b of the carrier 702. Then, subsequent packaging processes can be performed according to actual needs to complete the production of the package structure 700.

In some embodiments, interconnect conductor 720 is used to provide signal and power transmission between chip 510 and carrier 702 and may also serve as a heat sink. Interconnect conductor 720 is selected from the group consisting of: thick aluminum wire, thick aluminum ribbon, thick copper wire, thick copper ribbon, aluminized thick copper wire, aluminized thick copper ribbon, thick silver alloy wire, and thick silver alloy ribbon. Unless otherwise specified, the term "ribbon" refers to a generally flat, continuous, long sheet having a thickness of 10 to 500 microns and a width of 2 to 200 times its thickness, but typically no greater than 5 millimeters (mm). The term "thick wire" refers to a long, continuous, circular wire with a diameter of approximately 100 microns or more. This is significantly larger than the thin wire used in conventional IC or light-emitting diode (LED) hot-press wire bonding (less than 25.4 microns in diameter).

In some embodiments, one end 722 of the interconnect conductor 720 is electrically and physically connected to the chip 510 via the metal foil 710, while the other end 724 is electrically and physically connected to the carrier 702 via the copper pad 704b. In this way, the chip 510 can be electrically connected to the carrier 702 via the sintered sheet structure 10', the metal foil 710, the interconnect conductor 720, and the copper pad 704b. Specifically, one end 722 of the interconnect conductor material is first bonded to the metal foil 710 using ultrasonic wire bonding to form a first bond A. Then, the other end 724 of the interconnect conductor material is bonded to the copper pad 704b using ultrasonic wire bonding to form a second bond B. After forming the second bonding point B, the interconnect conductor material can be cut to form an interconnect conductor 720 having a first bonding point A and a second bonding point B. Using ultrasonic bonding for interconnection can avoid the generation of bonding gaps or unbonded parts, making the package structure 700 highly reliable.

In some embodiments, ultrasonic wire bonding is performed under process conditions of an ultrasonic vibration power of 50 to 300 milliwatts (mW), a bonding time of 100 to 150 milliseconds (ms), a contact load of 100 to 800 millinewtons (cN) (e.g., 200 to 600 millinewtons), and a bonding load of 200 to 1000 millinewtons (e.g., 300 to 800 millinewtons) to form a first bond A and a second bond B. In some embodiments of the present invention, unless otherwise defined, the term "load" refers to the intensity applied to the bond points (e.g., first bond A and second bond B) during the ultrasonic wire bonding process. It is worth noting that in this embodiment of the invention, the metal foil 710 and the sintered sheet structure 10' block or reduce the load on the chip 510 during ultrasonic wire bonding of the interconnect conductor 720, so that the chip 510 does not crack.

In some embodiments, the carrier 702 may include a printed circuit board or a ceramic substrate. The printed circuit board and the ceramic substrate may be made of the same or similar materials as the printed circuit board and the ceramic substrate described above, and their detailed description is omitted here for the sake of simplicity. In some embodiments, the copper pads 704a and 704b (hereinafter collectively referred to as copper pads 704) are part of a patterned circuit pattern and are disposed on the surface of the carrier 702. In some embodiments, the copper pads 704 include or are copper. The copper pads 704 are disposed on the carrier 702 using eutectic reaction direct bonding (direct bonded copper, DBC), direct electroplating bonding (direct plated copper, DPC) or active metal brazing (active metal brazing, AMB). In some embodiments, the chip 510 is bonded to the copper pad 704a of the carrier 702 by, for example, a die bonding method such as gold-silicon eutectic bonding, adhesive bonding, solder bonding, or sintering bonding, but the present invention is not limited thereto.

In some embodiments, as shown in FIG9 , the chip 510 may further include a pad 512 disposed on a surface of the chip 510 and a dielectric layer 514 disposed on the same layer as the pad 512. For example, the pad 512 and the dielectric layer 514 are part of a redistribution layer (RDL) in the chip 510. The pad 512 is formed in the topmost dielectric layer 514, and the surface of the pad 512 is substantially coplanar (e.g., flush) with the dielectric layer 514. In some embodiments, the pad 512 may include or be aluminum, copper, or other suitable metal materials. The dielectric layer 514 may include or be silicon dioxide, polyimide, or other suitable dielectric materials.

In some embodiments, the metal foil 710 may include or be silver, copper, or a silver-copper alloy. The thickness of the metal foil 710 is greater than 20 microns (e.g., greater than 100 microns). It should be understood that the thickness of the metal foil 710 can be appropriately adjusted based on the actual application, and the present invention is not limited thereto, as long as the metal foil 710 does not significantly deform during the sintering bonding process, thereby affecting subsequent processing.

In some embodiments, FIG16 is a partial cross-sectional view, obtained using a scanning electron microscope, of a package structure formed by applying a pre-baked wafer structure to an interconnect bonding silicon carbide wafer according to an experimental example of the present invention. This package structure is an example of the package structure 700 of FIG9 .

FIG10 illustrates a partial cross-sectional view of a package structure 800 employing a pre-sintered tab structure 10. In some embodiments, the package structure 800 of FIG10 is similar to the package structure 700 of FIG9 , except that the package structure 800 utilizes two sintered tab structures 10′ to bond the ends of a metal conductive sheet 810 to the chip 510 and the carrier 702, respectively. For example, one end of the metal conductive sheet 810 may be bonded to the chip 510 via a sintered tab structure 10′, while the other end may be bonded to the copper pad 704b of the carrier 702 via another sintered tab structure 10′. The remaining process details are as previously described and are not further described here. In some embodiments, the metal conductive sheet 810 may comprise or be a thick copper sheet. In other embodiments, the metal conductive sheet 810 may include the same or similar material as the metal foil 710, and a detailed description thereof is omitted for simplicity.

In summary, some embodiments of the present invention provide some benefits. The present invention provides a pre-sintered sheet structure having a nanocrystalline structure and a method for manufacturing the same. By pre-forming the pre-sintered sheet structure through a pre-sintering process and then applying the pre-sintered sheet structure to die bonding and internal wiring bonding, the problem of overflow due to pressure sintering can be avoided, and the thickness of the sintered layer can be easily controlled. In addition, due to the excellent atomic high diffusion ability of the nanocrystalline structure surface, the process temperature of the formal sintering process can be reduced, thereby completing the sintering bonding at a low temperature to avoid chip damage caused by extremely high thermal stress. In addition, low-temperature sintering can reduce the porosity of the sintered layer and increase its strength, thereby improving the electrical conductivity, thermal conductivity and bonding strength of the sintered layer.

The above overview of several embodiments is provided to facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that they can design or modify other processes and structures based on the present invention to achieve the same objectives and/or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

10, 20, 30, 40, 50, 60: Pre-sintered wafer structure 10', 20': Sintered wafer structure 100: Pre-sintered wafer 100': Sintered layer 100a: First surface 100b: Second surface 110: Nanocrystalline layer 210: Second nanocrystalline layer 300: Metal conductive sheet 300a: First side 300b: Second side 302, 502, 702: Carrier 400: Second pre-sintered wafer 410: Fourth nanocrystalline layer 500, 600: Die-bonding structure 510: Chip 512: Pad 514: Dielectric layer 520: Adhesive layer 700, 800: Package structure 704, 704a, 704b: Copper pad 710: Metal foil 720: Inner conductor 722, 724: Terminal 810: Metal conductive pads A, B: Bonding point

The following will describe in detail various aspects of the present invention with the help of the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various components are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. It should also be noted that the accompanying drawings only illustrate typical embodiments of the present invention and should not be considered as limiting its scope. The present invention can also be applied to other embodiments. Figures 1A to 1B are cross-sectional views of the formation of a pre-fired sheet structure at different stages of the process according to the first embodiment of the present invention. Figure 2 is a partial cross-sectional view of the pre-fired sheet structure according to the second embodiment of the present invention. Figures 3A and 3B are cross-sectional views showing the formation of a pre-baked sheet structure including a metal conductive sheet at different stages of the manufacturing process according to the third embodiment of the present invention. Figures 4A and 4B are cross-sectional views showing the formation of a pre-baked sheet structure at different stages of the manufacturing process according to the fourth embodiment of the present invention. Figures 5A and 5B are cross-sectional views showing the formation of a pre-baked sheet structure at different stages of the manufacturing process according to the fifth embodiment of the present invention. Figures 6A and 6B are cross-sectional views showing the formation of a pre-baked sheet structure at different stages of the manufacturing process according to the sixth embodiment of the present invention. Figures 7 to 10 are partial cross-sectional views showing the pre-baked sheet structure in various applications according to some embodiments of the present invention. FIG11A, FIG11B, and FIG12 to FIG16 are partial cross-sectional views obtained using a scanning electron microscope of a pre-fired sheet structure and its application according to some embodiments of the present invention.

10: Pre-sintered sheet structure

100: Pre-sintering

100a: First surface

100b: Second surface

110: Nanocrystalline layer

Claims (11)

A pre-sintered sheet structure includes: at least one pre-sintered sheet; and at least one nanocrystalline layer disposed on the pre-sintered sheet. The pre-sintered sheet structure as described in claim 1, wherein the at least one nanocrystalline layer comprises: a first nanocrystalline layer disposed on a first surface of the pre-sintered sheet; and a second nanocrystalline layer disposed on a second surface of the pre-sintered sheet opposite to the first surface. The pre-sintered sheet structure as described in claim 1 further includes a metal conductive sheet disposed on a side of the pre-sintered sheet opposite to the nanocrystalline layer. The pre-sintered sheet structure as described in claim 3, wherein the at least one pre-sintered sheet includes a first pre-sintered sheet and a second pre-sintered sheet, and the metal conductive sheet is sandwiched between the first pre-sintered sheet and the second pre-sintered sheet, and the at least one nanocrystalline layer includes: a third nanocrystalline layer disposed on a side of the first pre-sintered sheet opposite to the metal conductive sheet; and a fourth nanocrystalline layer disposed on a side of the second pre-sintered sheet opposite to the metal conductive sheet. The pre-sintered sheet structure as described in claim 3, wherein the metal conductive sheet includes a copper sheet, a nickel sheet, a silver sheet, or a gold foil. The pre-fired sheet structure as described in claim 3, wherein the thickness of the metal conductive sheet is 10 microns to 100 microns. The pre-sintered sheet structure as described in claim 1, wherein the pre-sintered sheet comprises silver particles or copper particles. The pre-fired sheet structure as described in claim 1, wherein the thickness of the pre-fired sheet is 10 microns to 100 microns. The pre-sintered sheet structure of claim 1, wherein the nanocrystalline layer comprises silver, copper, or a silver-copper alloy. The pre-fired sheet structure as claimed in claim 1, wherein the thickness of the nanocrystalline layer is 0.1 micrometer to 100 micrometers. The pre-sintered sheet structure as described in claim 1, wherein the nanocrystalline layer includes a parallel twin grain boundary, the spacing between the parallel twin grain boundaries is 1 nm to 50 nm, and in a cross-sectional metallographic image of the nanocrystalline layer, the parallel twin grain boundaries account for more than 50% of the total grain boundaries.