TWI891352B - Power supply device supporting power delivery - Google Patents

Abstract

A power supply device supporting PD (Power Delivery) includes a bridge rectifier, a first capacitor, a boost inductor, a first power switch element, a first output stage circuit, a transformer, a second power switch element, a second output stage circuit, a voltage divider circuit, and a detection and control circuit. The first power switch element selectively couples the boost inductor to a ground voltage according to a first driving voltage. The transformer includes a main coil and a secondary coil. The second power switch element selectively couples the main coil to the ground voltage according to a second driving voltage. The detection and control circuit includes a PD IC (Integrated Circuit). The detection and control circuit generates the first driving voltage and the second driving voltage according to an external voltage and a divided voltage.

Description

Power supply supporting power transmission

The present invention relates to a power supply, and more particularly to a power supply that supports Power Delivery (PD).

Power supplies are essential components in laptop computers. However, when the system is operating under heavy load, the battery in the device may not be properly charged. This necessitated a new solution to overcome the challenges faced by existing technologies.

In a preferred embodiment, the present invention provides a power supply supporting power transmission, comprising: a bridge rectifier generating a rectified potential based on a first input potential and a second input potential; a first capacitor storing the rectified potential; a boost inductor receiving the rectified potential; a first power switch selectively coupling the boost inductor to a ground potential based on a first drive potential; a first output stage circuit coupled to the boost inductor and generating an intermediate potential; and a transformer comprising a main coil and a secondary coil, wherein the main coil is configured to receive the intermediate potential, and the secondary coil is configured to receive the intermediate potential. The secondary coil is configured to generate an induced potential; a second power switch selectively couples the primary coil to the ground potential based on a second driving potential; a second output stage circuit generates an output potential based on the induced potential and a first control potential; a voltage divider circuit generates a divided voltage based on a second control potential and the output potential; and a detection and control circuit includes a power transmission integrated circuit, wherein the detection and control circuit generates the first driving potential, the second driving potential, the first control potential, and the second control potential based on an external potential and the divided voltage.

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the ground potential. is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor is coupled to the first node to store the rectified potential, and the second terminal of the first capacitor is coupled to the ground potential; wherein the boost inductor has a first terminal and a second terminal, the first terminal of the boost inductor is coupled to the first node to receive the rectified potential, and the second terminal of the boost inductor is coupled to a second node.

In some embodiments, the first power switch includes a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is configured to receive the first driving potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the second node.

In some embodiments, the first output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to a third node to output the intermediate potential; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the third node, and the second terminal of the second capacitor is coupled to the ground potential.

In some embodiments, the transformer further includes a built-in excitation inductor. The main coil has a first end and a second end. The first end of the main coil is coupled to the third node to receive the intermediate potential, and the second end of the main coil is coupled to a fourth node. The excitation inductor has a first end and a second end. The first end of the excitation inductor is coupled to the third node, and the second end of the excitation inductor is coupled to the fourth node. The secondary coil has a first end and a second end. The first end of the secondary coil is coupled to a fifth node to output the induced potential, and the second end of the secondary coil is coupled to a common node.

In some embodiments, the second power switch includes a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is configured to receive the second driving potential, the first terminal of the second transistor is coupled to the ground potential, and the second terminal of the second transistor is coupled to the fourth node.

In some embodiments, the second output stage circuit includes: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fifth node to receive the induced potential, and the cathode of the sixth diode is coupled to a sixth node; a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the sixth node, and the second terminal of the third capacitor is coupled to the common node; and a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the first control potential, the first terminal of the third transistor is coupled to an output node to selectively output the output potential, and the second terminal of the third transistor is coupled to the sixth node.

In some embodiments, the voltage divider circuit includes: a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the second control potential, the first terminal of the fourth transistor is coupled to a seventh node, and the second terminal of the fourth transistor is coupled to the output node to receive the output potential; a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the seventh node, and the second terminal of the first resistor is coupled to an eighth node to output the divided potential; and a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the eighth node, and the second terminal of the second resistor is coupled to the common node.

In some embodiments, the detection and control circuit further includes: a first microcontroller generating the first driving potential; and a second microcontroller generating the second driving potential; wherein the power transmission integrated circuit has a CC (Configuration The power transmission integrated circuit includes a first microcontroller (MCU) and a second microcontroller (MCU) configured to output a first control voltage at a high logic level. The first microcontroller outputs a switching voltage to the communication pin of the power transmission integrated circuit. The power transmission integrated circuit further controls the second microcontroller to increase a duty cycle of the second drive voltage, causing the output voltage to rise to a maximum output value.

In some embodiments, the detection and control circuit further includes an AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the AND gate is used to receive the external potential, the second input terminal of the AND gate is used to receive the first control potential, and the output terminal of the AND gate is used to output a logic potential; wherein in response to the logic potential having a high logic level, the second microcontroller further outputs the second control potential also having a high logic level.

100,200: Power supply

110,210: Bridge rectifier

120,220: First power switch

130,230: First output stage circuit

140,240: Transformer

141,241: Main Loop

142,242: Secondary coil

150,250: Second power switch

160,260: Second output stage circuit

170,270: Voltage divider circuit

180,280: Detection and control circuits

190,290: Power Transmission Integrated Circuit

282: First Microcontroller

284: Second microcontroller

286: Jimen

292: CC foot position

294: Communication Footprints

C1: First capacitor

C2: Second capacitor

C3: The third capacitor

D1: First diode

D2: Second diode

D3: The third diode

D4: Fourth Diode

D5: Fifth Diode

D6: Sixth Diode

DT: Working cycle

LM: Magnetizing Inductor

LU: Boost Inductor

M1: First transistor

M2: Second transistor

M3: The third transistor

M4: Fourth transistor

N1: First Node

N2: Second Node

N3: Third Node

N4: Fourth Node

N5: Fifth Node

N6: Node 6

N7: Seventh Node

N8: Node 8

NCM: Common Node

NIN1: First input node

NIN2: Second input node

NOUT: output node

R1: First resistor

R2: Second resistor

TS: Specific time point

VC1: First control voltage

VC2: Second control voltage

VD: voltage divider potential

VE: intermediate potential

VG1: First driving potential

VG2: Second driving potential

VIN1: First input potential

VIN2: Second input potential

VL: logical potential

VMAX: Maximum output value

VN: Notification voltage

VOUT: output voltage

VR: Rectification potential

VS: Induction potential

VSS: Ground potential

VT: Indicator potential

VW: Switching potential

VX: External potential

Figure 1 is a schematic diagram of a power supply according to one embodiment of the present invention.

Figure 2 shows a circuit diagram of a power supply according to one embodiment of the present invention.

Figure 3 shows a signal waveform diagram of a power supply according to an embodiment of the present invention.

To make the purpose, features, and advantages of the present invention more clearly understood, specific embodiments of the present invention are given below, along with accompanying drawings for detailed description.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in name as a way to distinguish components, but rather use differences in the functions of the components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open-ended terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

FIG1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be used in a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG1 , the power supply 100 includes a bridge rectifier 110, a first capacitor C1, a boost inductor LU, a first power switch 120, a first output stage circuit 130, a transformer 140, a second power switch 150, a second output stage circuit 160, a voltage divider circuit 170, and a detection and control circuit 180. It should be noted that, although not shown in FIG1 , the power supply 100 may further include other components, such as a voltage regulator and/or a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR based on a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage having any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50 Hz or 60 Hz, and the root mean square (RMS) value of the AC voltage can be between 90 V and 264 V, but is not limited thereto. The first capacitor C1 can be used to store the rectified potential VR. The boost inductor LU can be used to receive the rectified potential VR. The first power switch 120 can selectively couple the boost inductor LU to a ground potential VSS (e.g., 0 V) based on a first drive potential VG1. For example, if the first drive potential VG1 has a high logic level (i.e., a logic "1"), the first power switch 120 may couple the boost inductor LU to the ground potential VSS (i.e., the first power switch 120 may function as a short circuit). Conversely, if the first drive potential VG1 has a low logic level (i.e., a logic "0"), the first power switch 120 will not couple the boost inductor LU to the ground potential VSS (i.e., the first power switch 120 may function as an open circuit). The first output stage circuit 130 is coupled to the boost inductor LU, wherein the first output stage circuit 130 may be configured to generate an intermediate potential VE.

Transformer 140 includes a primary coil 141 and a secondary coil 142. Primary coil 141 may be located on one side of transformer 140, while secondary coil 142 may be located on the opposite side. Primary coil 141 is configured to receive an intermediate potential VE, and in response, secondary coil 142 is configured to generate an induced potential VS. Second power switch 150 selectively couples primary coil 141 to ground potential VSS based on a second drive potential VG2. For example, if the second drive potential VG2 has a high logic level, the second power switch 150 can couple the main winding 141 to the ground potential VSS (i.e., the second power switch 150 can function as a short-circuit). Conversely, if the second drive potential VG2 has a low logic level, the second power switch 150 does not couple the main winding 141 to the ground potential VSS (i.e., the second power switch 150 can function as an open-circuit). The second output stage circuit 160 can generate an output potential VOUT based on the sense potential VS and a first control potential VC1. For example, the output potential VOUT can be a DC potential with a potential level between 18V and 22V, but is not limited thereto.

The voltage divider circuit 170 generates a divided voltage VD based on a second control voltage VC2 and the output voltage VOUT. The detection and control circuit 180 includes a power delivery integrated circuit (PDIC) 190. The detection and control circuit 180 generates the aforementioned first drive voltage VG1, second drive voltage VG2, first control voltage VC1, and second control voltage VC2 based on an external voltage VX and the divided voltage VD. For example, the external voltage VX may come from a system (not shown), but the present invention is not limited thereto. According to actual measurement results, even when used to drive a system operating in a heavy-load mode, the power supply 100 of the present invention can still automatically adjust and optimize its output voltage VOUT, thereby effectively improving overall output stability and operating efficiency.

The following embodiments will introduce the detailed structure and operation of the power supply 100. It must be understood that these figures and descriptions are for illustrative purposes only and are not intended to limit the scope of the present invention.

FIG2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG2 , the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first capacitor C1, a boost inductor LU, a first power switch 220, a first output stage circuit 230, a transformer 240, a second power switch 250, a second output stage circuit 260, a voltage divider circuit 270, and a detection and control circuit 280. The first input node NIN1 and the second input node NIN2 of the power supply 200 can receive a first input potential VIN1 and a second input potential VIN2, respectively, from an external input power source (not shown). The output node NOUT of the power supply 200 can be used to output an output potential VOUT to a system (not shown), such as a laptop computer.

Bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. First diode D1 has an anode and a cathode. The anode of first diode D1 is coupled to first input node NIN1, while the cathode of first diode D1 is coupled to first node N1 to output a rectified potential VR. Second diode D2 has an anode and a cathode. The anode of second diode D2 is coupled to second input node NIN2, while the cathode of second diode D2 is coupled to first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS (e.g., 0V), and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first node N1 to store the rectified potential VR, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

The boost inductor LU has a first terminal and a second terminal, wherein the first terminal of the boost inductor LU is coupled to the first node N1 to receive the rectified potential VR, and the second terminal of the boost inductor LU is coupled to a second node N2.

The first power switch 220 includes a first transistor M1. For example, the first transistor M1 can be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the first transistor M1 is configured to receive a first drive potential VG1. The first terminal of the first transistor M1 is coupled to the ground potential VSS. The second terminal of the first transistor M1 is coupled to the second node N2.

The first output stage circuit 230 includes a fifth diode D5 and a second capacitor C2. The fifth diode D5 has an anode and a cathode. The anode of the fifth diode D5 is coupled to the second node N2, while the cathode of the fifth diode D5 is coupled to a third node N3 to output an intermediate potential VE. The second capacitor C2 has a first terminal and a second terminal. The first terminal of the second capacitor C2 is coupled to the third node N3, while the second terminal of the second capacitor C2 is coupled to the ground potential VSS.

The transformer 240 includes a main coil 241 and a secondary coil 242, wherein the transformer 240 may further include a built-in excitation inductor LM. The excitation inductor LM may be an inherent component generated during the manufacture of the transformer 240 and is not an external independent component. The main coil 241 and the excitation inductor LM may both be located on the same side of the transformer 240 (e.g., the primary side), while the secondary coil 242 may be located on the opposite side of the transformer 240 (e.g., the secondary side, which may be isolated from the primary side). In detail, the main coil 241 has a first end and a second end, wherein the first end of the main coil 241 is coupled to the third node N3 to receive the intermediate potential VE, and the second end of the main coil 241 is coupled to a fourth node N4. The magnetizing inductor LM has a first terminal and a second terminal. The first terminal of the magnetizing inductor LM is coupled to the third node N3, while the second terminal of the magnetizing inductor LM is coupled to the fourth node N4. The secondary coil 242 has a first terminal and a second terminal. The first terminal of the secondary coil 242 is coupled to a fifth node N5 to output an induced potential VS, while the second terminal of the secondary coil 242 is coupled to a common node NCM. For example, the common node NCM can provide a common potential, which can be considered another ground potential and can be the same as or different from the aforementioned ground potential VSS.

The second power switch 250 includes a second transistor M2. For example, the second transistor M2 can be an N-type metal oxide semiconductor field effect transistor. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the second transistor M2 is configured to receive a second drive potential VG2. The first terminal of the second transistor M2 is coupled to the ground potential VSS. The second terminal of the second transistor M2 is coupled to the fourth node N4.

The second output stage circuit 260 includes a third transistor M3, a sixth diode D6, and a third capacitor C3. For example, the third transistor M3 can be an N-type metal oxide semiconductor field effect transistor. The sixth diode D6 has an anode and a cathode. The anode of the sixth diode D6 is coupled to the fifth node N5 to receive the induced potential VS, and the cathode of the sixth diode D6 is coupled to the sixth node N6. The third capacitor C3 has a first terminal and a second terminal. The first terminal of the third capacitor C3 is coupled to the sixth node N6, and the second terminal of the third capacitor C3 is coupled to the common node NCM. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the third transistor M3 is configured to receive a first control potential VC1. The first terminal of the third transistor M3 is coupled to the output node NOUT, and the second terminal of the third transistor M3 is coupled to the sixth node N6. In some embodiments, the second output stage circuit 260 can be configured to selectively output the aforementioned output potential VOUT. For example, if the first control voltage VC1 has a high logic level, the third transistor M3 will be enabled, and the second output stage circuit 260 will normally output the aforementioned output voltage VOUT. Conversely, if the first control voltage VC1 has a low logic level, the third transistor M3 will be disabled, and the second output stage circuit 260 will stop outputting the aforementioned output voltage VOUT.

The voltage divider circuit 270 includes a fourth transistor M4, a first resistor R1, and a second resistor R2. For example, the fourth transistor M4 can be an N-type metal oxide semiconductor field effect transistor. The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fourth transistor M4 is used to receive a second control potential VC2. The first terminal of the fourth transistor M4 is coupled to a seventh node N7, and the second terminal of the fourth transistor M4 is coupled to the output node NOUT to receive the output potential VOUT. The first resistor R1 has a first terminal and a second terminal. The first terminal of the first resistor R1 is coupled to the seventh node N7, and the second terminal of the first resistor R1 is coupled to the eighth node N8. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the eighth node N8, and the second end of the second resistor R2 is coupled to the common node NCM. In some embodiments, the eighth node N8 of the voltage divider circuit 270 can be used to selectively output a divided voltage VD. For example, if the second control potential VC2 has a low logic level, the fourth transistor M4 is disabled, and the voltage divider circuit 270 does not output any divided voltage. Conversely, if the second control potential VC2 has a high logic level, the fourth transistor M4 is enabled, and the voltage divider circuit 270 outputs the aforementioned divided voltage VD. In some embodiments, if the common potential at the common node NCM is set to 0V, the aforementioned divided voltage VD can be calculated according to the following equation (1): Where "VD" represents the level of the divided voltage VD, "VOUT" represents the level of the output voltage VOUT, "R1" represents the resistance value of the first resistor R1, and "R2" represents the resistance value of the second resistor R2.

The detection and control circuit 280 includes a first microcontroller unit (MCU) 282, a second microcontroller 284, an AND gate 286, and a power transmission integrated circuit 290. The operating principle of the circuit can be described in the following embodiment.

The first microcontroller 282 can be used to generate a first drive potential VG1. The second microcontroller 284 can be used to generate a second drive potential VG2. For example, the first drive potential VG1 and the second drive potential VG2 can each be a pulse width modulation (PWM) potential, but the present invention is not limited thereto.

The power transmission integrated circuit 290 is coupled to the first microcontroller 282 and the second microcontroller 284. The power transmission integrated circuit 290 has a configuration channel pin (hereinafter referred to as the "CC pin") 292 and a communication pin 294. In some embodiments, the power supply 200 may support the USB (Universal Serial Bus) Type-C specification. For example, when the power supply 200 is coupled to a system terminal, the power transmission integrated circuit 290 may output a fixed current to the CC pin 292. If CC pin 292 receives an indication voltage VT from the system, power transmission integrated circuit 290 notifies second microcontroller 284, causing second microcontroller 284 to output a first control voltage VC1 with a high logic level. Power supply 200 then normally outputs the aforementioned output voltage VOUT, the voltage level of which can be adjusted based on different requirements.

In some embodiments, if the system is operating in a heavy-duty mode, an external potential VX may be applied to the first microcontroller 282 to notify the power supply 200. In response to the high logic level of the external potential VX, the first microcontroller 282 may output a switching potential VW to the communication pin 294 of the power transmission integrated circuit 290. The power transmission integrated circuit 290 then controls the second microcontroller 284 to increase the duty cycle DT of the second drive potential VG2, causing the output potential VOUT of the power supply 200 to rise to a maximum output value VMAX. For example, the duty cycle DT of the second drive voltage VG2 may originally be between 45% and 65%. If the second microcontroller 284 increases the duty cycle DT of the second drive voltage VG2 to between 85% and 90%, the power supply 200 can generate an output voltage VOUT having a maximum output value VMAX, but the present invention is not limited to this. Furthermore, the power transmission integrated circuit 290 can also transmit a notification voltage VN to the system via the CC pin 292 in advance to inform the system that the output voltage VOUT is about to be increased. In other embodiments, after the output voltage VOUT has been increased to the maximum output value VMAX, the second microcontroller 284 may also notify the power transmission integrated circuit 290 so that the power transmission integrated circuit 290 can set an overvoltage protection (OVP) mechanism corresponding to the maximum output value VMAX.

AND gate 286 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of AND gate 286 can be used to receive an external potential VX, the second input terminal of AND gate 286 can be used to receive a first control potential VC1, and the output terminal of AND gate 286 can be used to output a logic potential VL to the second microcontroller 284. For example, if both the external potential VX and the first control potential VC1 are at a high logic level, AND gate 286 will output a logic potential VL having a high logic level. Conversely, if either the external potential VX or the first control potential VC1 is at a low logic level, AND gate 286 will output a logic potential VL having a low logic level.

In response to the logic voltage VL having a high logic level, the second microcontroller 284 outputs a second control voltage VC2 also having a high logic level. At this point, the fourth transistor M4 is enabled, and the voltage divider circuit 270 outputs the divided voltage VD to the first microcontroller 282. The divided voltage VD can be considered a completion confirmation signal. When the first microcontroller 282 receives the divided voltage VD within a correct range, the detection and control circuit 280 determines that all adjustment and optimization processes have been successful. In some embodiments, the correct range of the divided voltage VD is between 2.5V and 5V, but is not limited thereto. In other embodiments, the correct range can be adjusted based on different requirements.

FIG3 shows a signal waveform diagram of a power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time (s) and the vertical axis represents potential level (V). Please refer to FIG2 and FIG3 together to understand the operating principle of the present invention. Initially, the external potential VX can be maintained at a low logic level. At a specific time point TS, the detection and control circuit 280 detects that the external potential VX switches from a low logic level to a high logic level, indicating that the system may be operating in a heavy load mode and requires stronger driving capability. Therefore, the power supply 200 quickly increases the output potential VOUT to its maximum output value VMAX. In addition, the second control potential VC2 also rises to a high logic level after a specific time point TS to confirm that all adjustments and optimization processes have been completed.

This invention proposes a novel power supply that supports power transmission. Based on actual measurement results, this power supply design effectively improves overall output stability, making it suitable for use in a wide variety of devices.

It is important to note that the voltage, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers may adjust these settings according to different needs. The power supply of the present invention is not limited to the conditions illustrated in Figures 1-3. The present invention may include only one or more features of any one or more of the embodiments in Figures 1-3. In other words, not all illustrated features must be implemented simultaneously in the power supply of the present invention. Although the embodiments of the present invention use metal oxide semiconductor field-effect transistors (MOSFETs), the present invention is not limited to this. Those skilled in the art may use other types of transistors, such as junction field-effect transistors (JFETs) or fin field-effect transistors (FFETs), without affecting the effectiveness of the present invention.

In this specification and the scope of the patent application, ordinal numbers, such as "first," "second," "third," etc., do not have a sequential relationship with each other and are only used to distinguish two different components with the same name.

Although the present invention is disclosed above with reference to preferred embodiments, these are not intended to limit the scope of the present invention. Anyone skilled in the art may make modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Power supply

110: Bridge rectifier

120: First power switch

130: First output stage circuit

140: Transformer

141: Main coil

142: Secondary coil

150: Second power switch

160: Second output stage circuit

170: Voltage divider circuit

180: Detection and control circuit

190: Power Transmission Integrated Circuit

C1: First capacitor

LU: Boost Inductor

VC1: First control voltage

VC2: Second control voltage

VD: voltage divider potential

VE: intermediate potential

VG1: First driving potential

VG2: Second driving potential

VIN1: First input potential

VIN2: Second input potential

VOUT: output voltage

VR: Rectification potential

VS: Induction potential

VSS: Ground potential

VX: External potential

Claims (10)

A power supply supporting power transmission includes: a bridge rectifier generating a rectified potential based on a first input potential and a second input potential; a first capacitor storing the rectified potential; a boost inductor receiving the rectified potential; a first power switch selectively coupling the boost inductor to a ground potential based on a first drive potential; a first output stage circuit coupled to the boost inductor and generating an intermediate potential; a transformer including a primary coil and a secondary coil, wherein the primary coil is configured to receive the intermediate potential, and the secondary coil is configured to generate an induced potential; A second power switch selectively couples the main coil to the ground potential based on a second drive potential; A second output stage circuit generates an output potential based on the sensed potential and a first control potential; A voltage divider circuit generates a divided voltage based on a second control potential and the output potential; and A detection and control circuit includes a power transmission integrated circuit, wherein the detection and control circuit generates the first drive potential, the second drive potential, the first control potential, and the second control potential based on an external potential and the divided voltage. The power supply of claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; the first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the first node to store the rectified potential, and the second terminal of the first capacitor is coupled to the ground potential; The boost inductor has a first end and a second end. The first end of the boost inductor is coupled to the first node to receive the rectified potential, and the second end of the boost inductor is coupled to a second node. The power supply of claim 2, wherein the first power switch comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is configured to receive the first drive potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the second node. The power supply of claim 2, wherein the first output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to a third node to output the intermediate potential; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the third node, and the second terminal of the second capacitor is coupled to the ground potential. A power supply as described in claim 4, wherein the transformer further has a built-in excitation inductor, the main coil having a first end and a second end, the first end of the main coil being coupled to the third node to receive the intermediate potential, the second end of the main coil being coupled to a fourth node, the excitation inductor having a first end and a second end, the first end of the excitation inductor being coupled to the third node, the second end of the excitation inductor being coupled to the fourth node, the secondary coil having a first end and a second end, the first end of the secondary coil being coupled to a fifth node to output the induced potential, and the second end of the secondary coil being coupled to a common node. The power supply of claim 5, wherein the second power switch comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is configured to receive the second drive potential, the first terminal of the second transistor is coupled to the ground potential, and the second terminal of the second transistor is coupled to the fourth node. The power supply of claim 5, wherein the second output stage circuit comprises: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fifth node to receive the induced potential, and the cathode of the sixth diode is coupled to a sixth node; a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the sixth node, and the second terminal of the third capacitor is coupled to the common node; and A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the first control potential, the first terminal of the third transistor is coupled to an output node to selectively output the output potential, and the second terminal of the third transistor is coupled to the sixth node. The power supply of claim 7, wherein the voltage divider circuit comprises: a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is configured to receive the second control potential, the first terminal of the fourth transistor is coupled to a seventh node, and the second terminal of the fourth transistor is coupled to the output node to receive the output potential; a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the seventh node, and the second terminal of the first resistor is coupled to an eighth node to output the divided potential; and a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the eighth node, and the second terminal of the second resistor is coupled to the common node. The power supply as claimed in claim 1, wherein the detection and control circuit further comprises: a first microcontroller generating the first drive potential; and a second microcontroller generating the second drive potential; wherein the power transmission integrated circuit has a CC (Configuration Channel) pin and a communication pin, and if the CC pin receives an indication potential from a system terminal, the power transmission integrated circuit notifies the second microcontroller, causing the second microcontroller to output the first control potential at a high logic level; In response to the external potential having a high logic level, the first microcontroller further outputs a switching potential to the communication pin of the power transmission integrated circuit, and the power transmission integrated circuit further controls the second microcontroller to increase a duty cycle of the second drive potential, so that the output potential rises to a maximum output value. The power supply as claimed in claim 9, wherein the detection and control circuit further comprises: An AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the AND gate is configured to receive the external potential, the second input terminal of the AND gate is configured to receive the first control potential, and the output terminal of the AND gate is configured to output a logic potential; In response to the logic potential having a high logic level, the second microcontroller further outputs the second control potential also having a high logic level.