TW202218300A - Boost converter for reducing total harmonic distortion - Google Patents

Abstract

A boost converter for reducing total harmonic distortion includes a bridge rectifier, a boost inductive circuit, a discharge circuit, a first power switch element, a second power switch element, a PWM (Pulse Width Modulation) IC (Integrated Circuit), a first transformer, a second transformer, and an output stage circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The boost inductive circuit is coupled through the discharge circuit to a ground voltage. The first transformer includes a first main coil and a first secondary coil. The first secondary coil generates a first induced voltage. The second transformer includes a second main coil and a second secondary coil. The second secondary coil generates a second induced voltage. The output stage circuit generates an output voltage according to the first induced voltage and the second induced voltage.

Description

Boost Converter for Total Harmonic Distortion Reduction

The present invention relates to a boost converter, in particular to a boost converter capable of reducing total harmonic distortion.

The operating frequency of conventional boost converters is usually set to 65kHz. If a higher operating frequency needs to be used, the boost converter often suffers a larger Total Harmonic Distortion because the output diode has an unsatisfactory reverse current recovery characteristic. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a boost converter for reducing total harmonic distortion, comprising: a bridge rectifier that generates a rectified potential according to a first input potential and a second input potential; a boost inductor a circuit for receiving the rectified potential; a discharge circuit, wherein the boost inductance circuit is coupled to a ground potential through the discharge circuit; a first transformer including a first main coil and a first secondary coil, wherein the first A secondary coil is used to generate a first induced potential; a second transformer includes a second main coil and a second secondary coil, wherein the second secondary coil is used to generate a second induced potential; a first a power switch for selectively coupling the boost inductor circuit to the ground potential through the first main coil according to a pulse width modulation potential; a second power switch for the pulse width modulation potential to selectively couple the boost inductor circuit to the ground potential through the second main coil; a pulse width modulation integrated circuit to generate the pulse width modulation potential; and an output stage circuit to generate the pulse width modulation potential according to the first An induced potential and the second induced potential generate an output potential.

In order to make the objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are given in the following, and are described in detail as follows in conjunction with the accompanying drawings.

Certain terms are used throughout the specification and claims to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may refer to the same element by different nouns. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The words "including" and "including" mentioned in the entire specification and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means. Second device.

FIG. 1 shows a schematic diagram of a boost converter 100 according to an embodiment of the present invention. For example, the boost converter 100 may be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in FIG. 1, the boost converter 100 includes: a bridge rectifier 110, a boost inductor circuit 120, a discharge circuit 130, a first power switch 140, a second power switch 150, a pulse width The modulation integrated circuit 160 , a first transformer 170 , a second transformer 180 , and an output stage circuit 190 . It should be noted that, although not shown in FIG. 1, the boost converter 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2. Both the first input potential VIN1 and the second input potential VIN2 can come from an external input power source, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be about 50Hz or 60Hz, and the RMS value of the AC voltage can be from 90V to 264V, but it is not limited thereto. The boost inductor circuit 120 can receive the rectified potential VR, wherein the boost inductor circuit 120 is coupled to a ground potential VSS (eg, 0V) through the discharge circuit 130 . The first transformer 170 includes a first primary coil 171 and a first secondary coil 172 , wherein the first primary coil 171 can be located on one side of the first transformer 170 , and the first secondary coil 172 can be located on the opposite side of the first transformer 170 . side. The first power switch 140 can selectively couple the boost inductor circuit 120 to the ground potential VSS via the first main coil 171 according to a PWM potential VM. For example, if the PWM potential VM is at a high logic level, the first power switch 140 can couple the boost inductor circuit 120 to the ground potential VSS through the first main coil 171 (ie, the first power The switch 140 can be approximated as a short circuit); on the contrary, if the PWM potential VM is at a low logic level, the first power switch 140 will not couple the boost inductor circuit 120 through the first main coil 171 to ground potential VSS (ie, the first power switch 140 can approximate an open path). In response to the first primary coil 171, the first secondary coil 172 can be used to generate a first induced potential VS1. The second transformer 180 includes a second primary coil 181 and a second secondary coil 182 , wherein the second primary coil 181 can be located on one side of the second transformer 180 , and the second secondary coil 182 can be located on the opposite side of the second transformer 180 . side. The second power switch 150 can selectively couple the boost inductor circuit 120 to the ground potential VSS via the second main coil 181 according to the PWM potential VM. For example, if the PWM potential VM is at a high logic level, the second power switch 150 can couple the boost inductor circuit 120 to the ground potential VSS through the second main coil 181 (ie, the second power The switch 150 can be approximated as a short-circuit path); on the contrary, if the PWM potential VM is at a low logic level, the second power switch 150 will not couple the boost inductor circuit 120 through the second main coil 181 to ground potential VSS (ie, the second power switch 150 can approximate an open path). In response to the second primary coil 181, the second secondary coil 182 can be used to generate a second induced potential VS2. The PWM integrated circuit 160 can generate the PWM potential VM. The output stage circuit 190 can generate an output potential VOUT according to the first sensing potential VS1 and the second sensing potential VS2. For example, the output potential VOUT may be approximately a DC potential, and its level may be approximately 400V, but it is not limited thereto. Under this design, the boost inductor circuit 120 and the discharge circuit 130 can jointly form a damping circuit to provide the function of buffer discharge. According to the actual measurement results, even if the PWM potential VM has a relatively high operating frequency (for example, much higher than 65 kHz in the conventional design), the design method of the present invention can still greatly reduce the speed of the boost converter 100 The total harmonic distortion, while improving the power factor of the overall circuit.

The following embodiments will introduce the detailed structure and operation of the boost converter 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 shows a schematic diagram of a boost converter 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the boost converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a boost inductor circuit 220, A discharge circuit 230 , a first power switch 240 , a second power switch 250 , a PWM integrated circuit 260 , a first transformer 270 , a second transformer 280 , and an output stage circuit 290 . The first input node NIN1 and the second input node NIN2 of the boost converter 200 can respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power source, and the output node NOUT of the boost converter 200 It can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The boost inductor circuit 220 includes a first inductor L1 and a second inductor L2. The first end of the first inductor L1 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first inductor L1 is coupled to a second node N1. A first inductor current IL1 may flow through the first inductor L1. The first end of the second inductor L2 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the second inductor L2 is coupled to a third node N3. A second inductor current IL2 can flow through the second inductor L2.

The first power switch 240 includes a first transistor M1. For example, the first transistor M1 can be an N-type MOSFET. The control terminal of the first transistor M1 is used for receiving a pulse width modulation potential VM, the first terminal of the first transistor M1 is coupled to a fourth node N4, and the second terminal of the first transistor M1 is coupled to the second node N2. The PWM potential VM can be used to adjust the duty cycle of the first power switch 240 . For example, if the PWM potential VM is at a high logic level, the first transistor M1 will be enabled; on the contrary, if the PWM potential VM is at a low logic level, the first transistor M1 will be turned on Disabled.

The second power switch 250 includes a second transistor M2. For example, the second transistor M2 can be an N-type MOSFET. The control terminal of the second transistor M2 is used for receiving the PWM potential VM, the first terminal of the second transistor M2 is coupled to a fifth node N5, and the second terminal of the second transistor M2 is connected to a fifth node N5. is coupled to the third node N3. The PWM potential VM can be used to adjust the duty cycle of the second power switch 250 . For example, if the PWM potential VM is at a high logic level, the second transistor M2 will be enabled; on the contrary, if the PWM potential VM is at a low logic level, the second transistor M2 will be turned on Disabled.

The PWM integrated circuit 260 can generate the PWM potential VM. For example, the PWM potential VM can be maintained at a fixed potential when the boost converter 200 is initialized, and a periodic clock waveform can be provided after the boost converter 200 enters a normal use stage.

The discharge circuit 230 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a fifth diode D5. The first end of the first resistor R1 is coupled to the second node N2, and the second end of the first resistor R1 is coupled to a sixth node N6. The first end of the second resistor R2 is coupled to the sixth node N6, and the second end of the second resistor R2 is coupled to the third node N3. In some embodiments, both the first resistor R1 and the second resistor R2 have relatively large resistance values (eg, at least 1 MΩ or more). The first end of the first capacitor C1 is coupled to a seventh node N7, and the second end of the first capacitor C1 is coupled to the sixth node N6. The anode of the fifth diode D5 is coupled to the seventh node N7, and the cathode of the fifth diode D5 is coupled to an eighth node N8. The first end of the third resistor R3 is coupled to the eighth node N8, and the second end of the third resistor R3 is coupled to the ground potential VSS.

The first transformer 270 includes a first primary coil 271 and a first secondary coil 272 , wherein the first primary coil 271 can be located on one side of the first transformer 270 , and the first secondary coil 272 can be located on the opposite side of the first transformer 270 . side. The first end of the first main coil 271 is coupled to the fourth node N4, and the second end of the first main coil 271 is coupled to the ground potential VSS. The first end of the first sub-coil 272 is coupled to a ninth node N9, and the second end of the first sub-coil 272 is coupled to a tenth node N10 to output a first induced potential VS1.

The second transformer 280 includes a second primary winding 281 and a second secondary winding 282 , wherein the second primary winding 281 can be located on one side of the second transformer 280 , and the second secondary winding 282 can be located on the opposite side of the second transformer 280 . side. The second main coil 281 has a first end and a second end, wherein the first end of the second main coil 281 is coupled to the fifth node N5, and the second end of the second main coil 281 is coupled to ground Potential VSS. The first end of the second sub-coil 282 is coupled to the ninth node N9, and the second end of the second sub-coil 282 is coupled to an eleventh node N11 to output a second induced potential VS2.

The output stage circuit 290 includes a sixth diode D6, a seventh diode D7, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The anode of the sixth diode D6 is coupled to the tenth node N10 to receive the first induced potential VS1, and the cathode of the sixth diode D6 is coupled to a twelfth node N12. The first end of the second capacitor C2 is coupled to the twelfth node N12, and the second end of the second capacitor C2 is coupled to a common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS. The anode of the seventh diode D7 is coupled to the eleventh node N11 to receive the second induced potential VS2, and the cathode of the seventh diode D7 is coupled to the output node NOUT. The first end of the third capacitor C3 is coupled to the output node NOUT, and the second end of the third capacitor C3 is coupled to the twelfth node N12. The first end of the fourth capacitor C4 is coupled to the output node NOUT, and the second end of the fourth capacitor C4 is coupled to the common node NCM. In some embodiments, the potential difference of the fourth capacitor C4 is exactly equal to the sum of the potential differences of the second capacitor C2 and the third capacitor C3.

In some embodiments, the boost converter 200 may alternately operate in a first mode and a second mode, and the operation principle may be described below.

In the first mode, the PWM potential VM is at a high logic level, so that both the first transistor M1 and the second transistor M2 are enabled. At this time, both the first inductor L1 and the second inductor L2 gradually store more energy, and the first inductor current IL1 and the second inductor current IL2 both gradually increase. In addition, the first transformer 270 and the second transformer 280 can transfer the input energy to the output stage circuit 290 indirectly. Since the impedances of the first resistor R1 and the second resistor R2 are much larger than the impedances of the first secondary coil 272 and the second secondary coil 282, the fifth diode D5 will not be sufficiently turned on, and the discharge circuit 230 is in the first mode will remain inactive.

In the second mode, the PWM potential VM is at a low logic level, so that both the first transistor M1 and the second transistor M2 are disabled. At this time, the energy stored in the first inductor L1 and the second inductor L2 can only be released by the discharge circuit 230 . That is, the fifth diode D5 is sufficiently turned on, and the discharge circuit 230 will also take corresponding actions. It must be noted that the combination of the boost inductor circuit 220 and the discharge circuit 230 can be regarded as an RLC damping circuit, which can be used to buffer the discharge current of the first inductor L1 and the second inductor L2. Since the output stage circuit 290 is not directly coupled to the boost inductor circuit 220, the first inductor current IL1 and the second inductor current IL2 are also not affected by the reverse current recovery characteristics of the sixth diode D6 and the seventh diode D7 affected.

FIG. 3 is a waveform diagram showing the inductor current of a conventional boost converter, wherein the horizontal axis represents time and the vertical axis represents current value. According to the measurement results in Fig. 3, the conventional boost converter is disturbed by the non-ideal characteristics of the output diode, so the corresponding inductor current is easily distorted (as shown by the dotted box in Fig. 3).

FIG. 4 shows a waveform diagram of the first inductor current IL1 or (and) the second inductor current IL2 of the boost converter 200 according to an embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents current value . According to the measurement results in FIG. 4 , even if the PWM potential VM has a relatively high operating frequency, the design method of the present invention can still greatly reduce the total harmonic distortion of the boost converter 200 .

In some embodiments, the component parameters of the boost converter 200 may be as follows. The operating frequency of the PWM potential VM may be between 150 kHz and 250 kHz. The capacitance value of the first capacitor C1 can be between 96 μF and 144 μF, preferably 120 μF. The capacitance value of the second capacitor C2 can be between 376 μF and 564 μF, preferably 470 μF. The capacitance value of the third capacitor C3 can be between 376 μF and 564 μF, preferably 470 μF. The capacitance value of the fourth capacitor C4 may be between 544 μF and 816 μF, preferably 680 μF. The inductance value of the first inductor L1 can be between 297 μH and 363 μH, preferably 330 μH. The inductance value of the second inductor L2 may be between 297 μH and 363 μH, preferably 330 μH. The resistance value of the first resistor R1 can be between 2.7MΩ and 3.3MΩ, preferably 3MΩ. The resistance value of the second resistor R2 may be between 2.7MΩ and 3.3MΩ, preferably 3MΩ. The resistance value of the third resistor R3 can be between 0.9KΩ and 1.1KΩ, preferably 1KΩ. The turns ratio of the first secondary coil 272 to the first main coil 271 may be between 1 and 100, preferably about 11. The turns ratio of the second secondary coil 282 to the second primary coil 281 may be between 1 and 100, preferably about 11. The above parameter ranges are derived from multiple experimental results, which help to minimize the total harmonic distortion of the boost converter 200 .

The present invention provides a novel boost converter including a damping circuit formed by a boost inductor circuit and a discharge circuit. According to the actual measurement results, using the boost converter of the above design can almost completely eliminate the non-ideal total harmonic distortion and improve the power factor of the overall circuit, so it is very suitable for use in various devices.

It should be noted that the potential, current, resistance value, inductance value, capacitance value and other component parameters mentioned above are not limitations of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the states illustrated in FIGS. 1-4. The present invention may include only any one or more features of any one or more of the embodiments of Figures 1-4. In other words, not all of the features shown must be simultaneously implemented in the boost converter of the present invention. Although the embodiments of the present invention use MOSFETs as an example, the present invention is not limited to this, and those skilled in the art can use other types of transistors, such as junction field effect transistors, or fins type field effect transistor, etc., without affecting the effect of the present invention.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100,200: Boost Converter 110, 210: Bridge Rectifiers 120, 220: Boost Inductor Circuit 130,230: Discharge circuit 140,240: First Power Switch 150,250: Second power switch 160,260: Pulse Width Modulation Integrated Circuits 170,270: First Transformer 171,271: First main coil 172,272: The first secondary coil 180,280: Second Transformer 181,281: Second main coil 182, 282: Second secondary coil 190,290: Output stage circuit C1: first capacitor C2: Second capacitor C3: Third capacitor D1: first diode D2: Second diode D3: Third diode D4: Fourth diode D5: Fifth diode D6: sixth diode D7: seventh diode IL1: first inductor current IL2: Second inductor current M1: first transistor M2: second transistor N1: the first node N2: second node N3: The third node N4: Fourth Node N5: Fifth node N6: sixth node N7: seventh node N8: Eighth Node N9: ninth node N10: The tenth node N11: Eleventh node N12: Twelfth Node NCM: Common Node NIN1: The first input node NIN2: Second input node NOUT: output node L1: first inductor L2: Second Inductor R1: first resistor R2: Second resistor R3: Third resistor VIN1: the first input potential VIN2: The second input potential VM: PWM potential VOUT: output potential VR: rectified potential VS1: The first induced potential VS2: Second induced potential VSS: ground potential

FIG. 1 shows a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 2 shows a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 3 is a waveform diagram showing the inductor current of a conventional boost converter. FIG. 4 is a waveform diagram showing the first inductor current or (and) the second inductor current of the boost converter according to an embodiment of the present invention.

100: Boost Converter

110: Bridge Rectifier

120: Boost inductor circuit

130: Discharge circuit

140: The first power switch

150: Second power switch

160: Pulse Width Modulation Integrated Circuit

170: First Transformer

171: The first main coil

172: The first secondary coil

180: Second Transformer

181: The second main coil

182: Second Coil

190: Output stage circuit

VIN1: the first input potential

VIN2: The second input potential

VM: PWM potential

VOUT: output potential

VR: rectified potential

VS1: The first induced potential

VS2: Second induced potential

VSS: ground potential

Claims (10)

A boost converter for reducing total harmonic distortion, comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a boost inductance circuit to receive the rectified potential; a discharge circuit, wherein the boost inductor circuit is coupled to a ground potential through the discharge circuit; a first transformer, including a first main coil and a first sub-coil, wherein the first sub-coil is used to generate a first induced potential; a second transformer, comprising a second main coil and a second sub-coil, wherein the second sub-coil is used to generate a second induced potential; a first power switch selectively coupling the boost inductor circuit to the ground potential through the first main coil according to a pulse width modulation potential; a second power switch selectively coupling the boost inductor circuit to the ground potential through the second main coil according to the PWM potential; a pulse width modulation integrated circuit for generating the pulse width modulation potential; and An output stage circuit generates an output potential according to the first induced potential and the second induced potential. The boost converter of claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the first diode the cathode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the second diode the cathode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node. The boost converter of claim 2, wherein the boost inductor circuit comprises: a first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the first node to receive the rectified potential, and the first end of the first inductor The second end is coupled to a second node; and a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the first node, and the second end of the second inductor is coupled connected to a third node. The boost converter of claim 3, wherein the first power switch comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used for receiving the pulse width modulation potential, and the first transistor the first terminal is coupled to a fourth node, and the second terminal of the first transistor is coupled to the second node; The operating frequency of the PWM potential is between 150kHz and 250kHz. The boost converter of claim 4, wherein the second power switch comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used for receiving the pulse width modulation potential, and the second transistor has The first terminal is coupled to a fifth node, and the second terminal of the second transistor is coupled to the third node. The boost converter of claim 3, wherein the discharge circuit comprises: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the second node, and the second end of the first resistor is coupled connected to a sixth node; and a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the sixth node, and the second end of the second resistor is coupled connected to the third node; The first resistor and the second resistor both have relatively large resistance values. The boost converter of claim 6, wherein the discharge circuit further comprises: a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to a seventh node, and the second end of the first capacitor is coupled to the the sixth node; A fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the seventh node, and the cathode of the fifth diode is coupled to an eighth node node; and a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the eighth node, and the second end of the third resistor is coupled connected to this ground potential. The boost converter of claim 5, wherein the first main coil has a first end and a second end, the first end of the first main coil is coupled to the fourth node, the first end The second end of a main coil is coupled to the ground potential, the first sub coil has a first end and a second end, and the first end of the first sub coil is coupled to a ninth node , and the second end of the first sub-coil is coupled to a tenth node to output the first induced potential. The boost converter of claim 8, wherein the second main coil has a first end and a second end, the first end of the second main coil is coupled to the fifth node, the first end The second end of the two main coils is coupled to the ground potential, the second sub coil has a first end and a second end, and the first end of the second sub coil is coupled to the ninth node , and the second end of the second sub-coil is coupled to an eleventh node to output the second induced potential. The boost converter of claim 9, wherein the output stage circuit comprises: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the tenth node to receive the first induced potential, and the cathode of the sixth diode is coupled to a twelfth node; a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the twelfth node, and the second terminal of the second capacitor is coupled to a common node; a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the eleventh node to receive the second induced potential, and the seventh diode the cathode is coupled to an output node to output the output potential; a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the output node, and the second terminal of the third capacitor is coupled to the first terminal twelve nodes; and a fourth capacitor having a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the output node, and the second terminal of the fourth capacitor is coupled to the common node.

Images