TWI851351B - Power supply device for reducing power consumption - Google Patents

Abstract

A power supply device for reducing power consumption includes a bridge rectifier, a boost inductor, a first capacitor, a first power switch element, a first output stage circuit, a transformer, a second power switch element, a second output stage circuit, and a detection and control circuit. The detection and control circuit includes a first PWM (Pulse Width Modulation) IC (Integrated Circuit) and a second PWM IC. The first PWM IC is configured to generate a first PWM voltage. The second PWM IC is configured to generate a second PWM voltage. After a protection mechanism is triggered, the detection and control circuit can turn off the first PWM IC and the second PWM IC.

Description

Power supply with reduced power consumption

The present invention relates to a power supply, and more particularly to a power supply capable of reducing power consumption.

Currently, there are two types of protection mechanisms for power supplies, one is a latch-off design, and the other is an auto-recovery design. The latch-off protection mechanism has a disadvantage, that is, when a fault occurs, the related controller will still consume some power, resulting in a decrease in overall operating efficiency. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention provides a power supply for reducing power consumption, comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a boost inductor, receiving the rectified potential; a first capacitor, storing the rectified potential; a first power switch, selectively coupling the boost inductor to a ground potential according to a first pulse width modulation potential; a first output stage circuit, coupled to the boost inductor and generating an intermediate potential; a transformer, comprising a main coil and a secondary coil, wherein the main coil is used to receive the intermediate potential; a second ... A second pulse width modulation potential is used to selectively couple the main coil to the ground potential; a second output stage circuit is coupled to the secondary coil and generates an output potential; and a detection and control circuit includes a first pulse width modulation integrated circuit and a second pulse width modulation integrated circuit, wherein the first pulse width modulation integrated circuit The variable integrated circuit is used to generate the first pulse width modulation potential, and the second pulse width modulation integrated circuit is used to generate the second pulse width modulation potential; after a protection mechanism is triggered, the detection and control circuit will turn off the first pulse width modulation integrated circuit and the second pulse width modulation integrated circuit.

In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.

FIG. 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG. 1, the power supply 100 includes: a bridge rectifier 110, a boost inductor LU, a first capacitor C1, a first power switch 120, a first output stage circuit 130, a transformer 140, a second power switch 150, a second output stage circuit 160, and a detection and control circuit 170. It should be noted that, although not shown in FIG. 1, the power supply 100 may further include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50 Hz or 60 Hz, and the RMS value of the AC voltage can be approximately from 90 V to 264 V, but is not limited thereto. The boost inductor LU can receive the rectified potential VR. The first capacitor C1 can store the rectified potential VR. The first power switch 120 can selectively couple the boost inductor LU to a ground potential VSS (e.g., 0 V) according to a first pulse width modulation potential VM1. For example, if the first pulse width modulation potential VM1 is a high logic level (i.e., logic "1"), the first power switch 120 can couple the boost inductor LU to the ground potential VSS (i.e., the first power switch 120 can be similar to a short circuit path); conversely, if the first pulse width modulation potential VM1 is a low logic level (i.e., logic "0"), the first power switch 120 will not couple the boost inductor LU to the ground potential VSS (i.e., the first power switch 120 can be similar to an open circuit path). The first output stage circuit 130 is coupled to the boost inductor LU, wherein the first output stage circuit 130 can be used to generate an intermediate potential VE. In some embodiments, the bridge rectifier 110, the boost inductor LU, the first capacitor C1, the first power switch 120, and the first output stage circuit 130 may together form a front stage circuit structure of the power supply 100.

The transformer 140 includes a main coil 141 and a secondary coil 142, wherein the main coil 141 can be used to receive the intermediate potential VE. For example, the main coil 141 can be located on one side of the transformer 140, and the secondary coil 142 can be located on the other side of the transformer 140. The second power switch 150 can selectively couple the main coil 141 to the ground potential VSS according to a second pulse width modulation potential VM2. For example, if the second pulse width modulation potential VM2 is a high logic level, the second power switch 150 can couple the main coil 141 to the ground potential VSS (that is, the second power switch 150 can be similar to a short circuit path); conversely, if the second pulse width modulation potential VM2 is a low logic level, the second power switch 150 will not couple the main coil 141 to the ground potential VSS (that is, the second power switch 150 can be similar to an open circuit path). The second output stage circuit 160 is coupled to the secondary coil 142, wherein the second output stage circuit 160 can be used to generate an output potential VOUT. For example, the output potential VOUT can be a DC potential, and its potential level can be from 18V to 22V, but it is not limited thereto. In some embodiments, the transformer 140 , the second power switch 150 , and the second output stage circuit 160 may together form a rear stage circuit structure of the power supply 100 .

The detection and control circuit 170 includes a first pulse width modulation integrated circuit (PWM IC) 172 and a second pulse width modulation integrated circuit 174, wherein the first pulse width modulation integrated circuit 172 can be used to generate a first pulse width modulation potential VM1 to control the front-stage circuit structure of the power supply 100, and the second pulse width modulation integrated circuit 174 can be used to generate a second pulse width modulation potential VM2 to control the rear-stage circuit structure of the power supply 100. After a protection mechanism is triggered, the detection and control circuit 170 will shut down the first pulse width modulation integrated circuit 172 and the second pulse width modulation integrated circuit 174, thereby effectively reducing the overall power consumption of the power supply 100. For example, the aforementioned protection mechanism may refer to an over-voltage protection, an over-current protection, a short-circuit current protection, or an over-temperature protection, but is not limited thereto.

The following embodiments will introduce the detailed structure and operation of the power supply 100. It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes: a bridge rectifier 210, a boost inductor LU, a first capacitor C1, a first power switch 220, a first output stage circuit 230, a transformer 240, a second power switch 250, a second output stage circuit 260, and a detection and control circuit 270. The first input node NIN1 and the second input node NIN2 of the power supply 200 can be used to receive a first input potential VIN1 and a second input potential VIN2 respectively from an external input power source (not shown). The output node NOUT of the power supply 200 can be used to output an output potential VOUT to a system end (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The boost inductor LU has a first terminal and a second terminal, wherein the first terminal of the boost inductor LU is coupled to the first node N1 to receive the rectified potential VR, and the second terminal of the boost inductor LU is coupled to a second node N2.

The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first node N1 to receive the rectified potential VR, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

The first power switch 220 includes a first transistor M1. For example, the first transistor M1 may be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is used to receive a first pulse width modulation potential VM1, the first terminal of the first transistor M1 is coupled to the ground potential VSS, and the second terminal of the first transistor M1 is coupled to the second node N2.

The first output stage circuit 230 includes a fifth diode D5 and a second capacitor C2. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the second node N2, and the cathode of the fifth diode D5 is coupled to a third node N3 to output an intermediate potential VE. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the third node N3, and the second terminal of the second capacitor C2 is coupled to the ground potential VSS.

The transformer 240 includes a main coil 241 and a secondary coil 242, wherein the transformer 240 may further have a built-in excitation inductor LM. The excitation inductor LM may be an inherent component that is produced when the transformer 240 is manufactured, and it is not an external independent component. The main coil 241 and the excitation inductor LM may be located on the same side of the transformer 240 (e.g., the primary side), and the secondary coil 242 may be located on the other side of the transformer 240 (e.g., the secondary side, which may be isolated from the primary side). The main coil 241 has a first end and a second end, wherein the first end of the main coil 241 is coupled to the third node N3 to receive the intermediate potential VE, and the second end of the main coil 241 is coupled to a fourth node N4. The magnetizing inductor LM has a first end and a second end, wherein the first end of the magnetizing inductor LM is coupled to the third node N3, and the second end of the magnetizing inductor LM is coupled to the fourth node N4. The secondary coil 242 has a first end and a second end, wherein the first end of the secondary coil 242 is coupled to a fifth node N5, and the second end of the secondary coil 242 is coupled to a common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS. In some embodiments, the ground potential VSS can be used as a primary side ground point of the transformer 240, and the common node NCM can be used as a secondary side ground point of the transformer 240, but it is not limited to this.

The second power switch 250 includes a second transistor M2. For example, the second transistor M2 may be another N-type metal oxide semi-conductor field effect transistor. The second transistor M2 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the second transistor M2 is used to receive a second pulse width modulation potential VM2, the first end of the second transistor M2 is coupled to the ground potential VSS, and the second end of the second transistor M2 is coupled to the fourth node N4.

The second output stage circuit 260 includes a sixth diode D6 and a third capacitor C3. The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the fifth node N5, and the cathode of the sixth diode D6 is coupled to the output node NOUT. The third capacitor C3 has a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the output node NOUT, and the second terminal of the third capacitor C3 is coupled to the common node NCM.

The detection and control circuit 270 includes a first pulse width modulation integrated circuit 272, a second pulse width modulation integrated circuit 274, a timing circuit 276, a third transistor M3, a fourth transistor M4, and a resistor R. For example, the third transistor M3 and the fourth transistor M4 can each be an N-type metal oxide semi-conductor field effect transistor.

The resistor R may have a relatively large resistance value (for example, it may be greater than or equal to 500KΩ). The resistor R has a first end and a second end, wherein the first end of the resistor R is coupled to the first node N1, and the second end of the resistor R is coupled to a detection node ND to output a detection potential VD. The third transistor M3 has a control end (for example, a gate), a first end (for example, a source), and a second end (for example, a drain), wherein the control end of the third transistor M3 is used to receive a first control potential VC1, the first end of the third transistor M3 is coupled to an internal node NN, and the second end of the third transistor M3 is coupled to the detection node ND. The fourth transistor M4 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the fourth transistor M4 is used to receive a second control potential VC2, the first end of the fourth transistor M4 is coupled to the ground potential VSS, and the second end of the fourth transistor M4 is coupled to the internal node NN.

FIG. 3 shows a signal waveform diagram of the power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time (s) and the vertical axis represents the potential level (V) of each signal. Please refer to FIGS. 2 and 3 together to understand the operating principle of the power supply 200.

Initially (i.e., before a first time point T1), the power supply 200 operates normally. At this time, the detection potential VD can be maintained at a high logic level, the first pulse width modulation integrated circuit 272 can continuously output the first pulse width modulation potential VM1, and the second pulse width modulation integrated circuit 274 can continuously output the second pulse width modulation potential VM2.

At the first time point T1, the second PWM integrated circuit 274 determines that any protection mechanism has been triggered. For example, the second PWM integrated circuit 274 can determine whether the aforementioned protection mechanism has been triggered by monitoring the operating state of the power supply 200; or, the second PWM integrated circuit 274 can determine whether the aforementioned protection mechanism has been triggered according to an internal potential (not shown) of the power supply 200, but is not limited thereto.

When the aforementioned protection mechanism is triggered, the second pulse width modulation integrated circuit 274 stops outputting the second pulse width modulation potential VM2 and generates a second control potential VC2 with a high logic level, and then transmits a communication potential VT to the first pulse width modulation integrated circuit 272. In response to the communication potential VT, the first pulse width modulation integrated circuit 272 stops outputting the first pulse width modulation potential VM1 and generates a first control potential VC1 with a high logic level. At this time, the detection potential VD at the detection node ND is pulled down to the ground potential VSS level by the enabled third transistor M3 and the enabled fourth transistor M4.

The timing circuit 276 can continuously monitor the detection potential VD at the detection node ND. When it is found that the detection potential VD is substantially equal to the ground potential VSS, the timing circuit 276 starts to calculate a first delay time TD1. When the first delay time TD1 expires (i.e., at a second time point T2), the timing circuit 276 transmits a notification potential VN with a high logic level to the first PWM IC 272.

At the second time point T2, in response to the notification potential VN having a high logic level, the first PWM IC 272 starts to calculate a second delay time TD2. When the second delay time TD2 expires (i.e., at a third time point T3), the first PWM IC 272 is turned off, so that the second PWM IC 274 is also turned off. Since both the first PWM IC 272 and the second PWM IC 274 are turned off, the overall power consumption of the power supply 200 can be reduced to almost zero. In other words, based on the protection mechanism that has been triggered, the power supply 200 will be able to maintain a closed state until its external input power is reset.

In some embodiments, the first delay time TD1 may be between 100 μs and 260 μs, and the second delay time TD2 may be between 100 μs and 150 μs. The aforementioned time range is obtained based on multiple experimental results, which can avoid accidental damage to the internal components of the power supply 200 and also help reduce the probability of the protection mechanism being misjudged and triggered.

The present invention proposes a novel power supply. According to actual measurement results, the power supply using the above design can quickly shut down the corresponding pulse width modulation integrated circuit after any protection mechanism is triggered to reduce power consumption, so it is very suitable for application in various types of devices.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in Figures 1-3. The present invention may only include any one or more features of any one or more embodiments of Figures 1-3. In other words, not all of the features shown in the diagrams need to be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited to this. People in the technical field can use other types of transistors, such as junction field effect transistors, or fin field effect transistors, etc., without affecting the effects of the present invention.

Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.

Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100,200: Power supply 110,210: Bridge rectifier 120,220: First power switch 130,230: First output stage circuit 140,240: Transformer 141,241: Main coil 142,242: Secondary coil 150,250: Second power switch 160,260: Second output stage circuit 170,270: Detection and control circuit 172,272: First pulse width modulation integrated circuit 174,274: Second pulse width modulation integrated circuit 276: Timing circuit C1: First capacitor C2: Second capacitor C3: Third capacitor D1: first diode D2: second diode D3: third diode D4: fourth diode D5: fifth diode D6: sixth diode LM: excitation inductor LU: boost inductor M1: first transistor M2: second transistor M3: third transistor M4: fourth transistor N1: first node N2: second node N3: third node N4: fourth node N5: fifth node NCM: common node ND: detection node NIN1: first input node NIN2: second input node NN: internal node NOUT: output node R: resistor T1: first time point T2: second time point T3: third time point TD1: first delay time TD2: Second delay time VC1: First control potential VC2: Second control potential VD: Detection potential VE: Intermediate potential VIN1: First input potential VIN2: Second input potential VM1: First pulse width modulation potential VM2: Second pulse width modulation potential VN: Notification potential VOUT: Output potential VR: Rectification potential VSS: Ground potential VT: Communication potential

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. FIG. 3 is a signal waveform diagram showing a power supply according to an embodiment of the present invention.

100: Power supply

110: Bridge rectifier

120: First power switch

130: First output stage circuit

140: Transformer

141: Main coil

142: Secondary coil

150: Second power switch

160: Second output stage circuit

170: Detection and control circuit

172: The first pulse width modulation integrated circuit

174: The second pulse width modulation integrated circuit

C1: First capacitor

LU: Boost Inductor

VE: Middle potential

VIN1: first input potential

VIN2: Second input potential

VM1: First pulse width modulation potential

VM2: Second pulse width modulation potential

VOUT: output voltage

VR: Rectification potential

VSS: ground potential

Claims (9)

A power supply for reducing power consumption includes: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a boost inductor, receiving the rectified potential; a first capacitor, storing the rectified potential; a first power switch, selectively coupling the boost inductor to a ground potential according to a first pulse width modulation potential; a first output stage circuit, coupled to the boost inductor and generating an intermediate potential; a transformer, including a main coil and a secondary coil, wherein the main coil is used to receive the intermediate potential; a second power switch, selectively coupling the main coil to the ground potential according to a second pulse width modulation potential; a second output stage circuit, coupled to the secondary coil , and generates an output potential; and a detection and control circuit, including a first pulse width modulation integrated circuit and a second pulse width modulation integrated circuit, wherein the first pulse width modulation integrated circuit is used to generate the first pulse width modulation potential, and the second pulse width modulation integrated circuit is used to generate the second pulse width modulation potential; wherein in a protection mechanism After being triggered, the detection and control circuit will turn off the first pulse width modulation integrated circuit and the second pulse width modulation integrated circuit; wherein the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the The detection and control circuit further comprises: a resistor having a first terminal and a second terminal. , wherein the first end of the resistor is coupled to the first node, and the second end of the resistor is coupled to a detection node to output a detection potential; a third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is used to receive a first control potential, the first end of the third transistor is coupled to an internal node, and the second end of the third transistor is coupled to the detection node; and a fourth transistor having a control end, a first end, and a second end, wherein the control end of the fourth transistor is used to receive a second control potential, the first end of the fourth transistor is coupled to the ground potential, and the second end of the fourth transistor is coupled to the internal node. A power supply as claimed in claim 1, wherein: the boost inductor has a first end and a second end, the first end of the boost inductor is coupled to the first node to receive the rectified potential, and the second end of the boost inductor is coupled to a second node; the first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the first node to receive the rectified potential, and the second end of the first capacitor is coupled to the ground potential. A power supply as claimed in claim 2, wherein the first power switch comprises: a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the first pulse width modulation potential, the first end of the first transistor is coupled to the ground potential, and the second end of the first transistor is coupled to the second node. A power supply as claimed in claim 2, wherein the first output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to a third node to output the intermediate potential; and a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the third node, and the second end of the second capacitor is coupled to the ground potential. As the power supply of claim 4, the transformer further has a built-in excitation inductor, the main coil has a first end and a second end, the first end of the main coil is coupled to the third node to receive the intermediate potential, the second end of the main coil is coupled to a fourth node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the third node, and the second end of the excitation inductor is coupled to the fourth node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled to a fifth node, and the second end of the secondary coil is coupled to a common node. A power supply as claimed in claim 5, wherein the second power switch comprises: a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive the second pulse width modulation potential, the first end of the second transistor is coupled to the ground potential, and the second end of the second transistor is coupled to the fourth node. A power supply as claimed in claim 5, wherein the second output stage circuit comprises: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fifth node, and the cathode of the sixth diode is coupled to an output node to output the output potential; and a third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the output node, and the second end of the third capacitor is coupled to the common node. The power supply of claim 1, wherein the detection and control circuit further comprises: a timing circuit, wherein when the detection potential is approximately equal to the ground potential, the timing circuit starts to calculate a first delay time; wherein when the first delay time expires, the timing circuit transmits a notification potential to the first pulse width modulation integrated circuit. The power supply of claim 8, wherein: when the protection mechanism is triggered, the second pulse width modulation integrated circuit stops outputting the second pulse width modulation potential and generates the second control potential with a high logic level, and then transmits a communication potential to the first pulse width modulation integrated circuit; in response to the communication potential, the first pulse width modulation integrated circuit Stop outputting the first pulse width modulation potential and generate the first control potential with a high logic level; in response to the notification potential, the first pulse width modulation integrated circuit starts calculating a second delay time; when the second delay time expires, the first pulse width modulation integrated circuit is turned off, so that the second pulse width modulation integrated circuit is also turned off.

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