TWI869009B - Circuit board and manufacturing method thereof - Google Patents

Abstract

A circuit board includes a body, a cavity opening, a power supply circuit, a metal wall layer and a plurality of shielding blind vias. The body has an upper surface and a lower surface opposite to the upper surface. The cavity opening is disposed in the body and has a bottom and a stepped sidewall surrounding the bottom. The stepped sidewall is connected to the upper surface. The power supply circuit is disposed on the bottom. The metal wall layer is disposed on the stepped sidewall and is electrically separated from the power supply circuit. The shielding blind vias are disposed in the body and located between the bottom and the lower surface.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board with a cavity opening having a stepped side wall and a manufacturing method thereof.

As electronic products develop towards lightweight and miniaturization, more and more products combine cavity waveguides with circuit boards. With the low signal loss characteristics of air, cavity waveguides can transmit signals completely. Cavity waveguides can be used in automotive radar products, for example. However, forming a circuit board with a cavity by pressing a multi-layer structure may cause problems such as cavity slot alignment deviation, discontinuity of the metal layer on the cavity side wall, and glue overflow into the cavity, making it difficult to improve the yield, or even reduce it.

At least one embodiment of the present invention provides a circuit board having a cavity opening with a stepped side wall and a metal wall layer disposed on the stepped side wall, which can improve the integration of the circuit board.

At least one embodiment of the present invention provides a method for manufacturing the above-mentioned circuit board to help improve the yield of the above-mentioned circuit board.

A circuit board proposed in at least one embodiment of the present invention comprises a board body, a cavity opening, a power supply line, a metal wall layer and a plurality of shielding blind holes. The board body has an upper surface and a lower surface opposite to the upper surface. The cavity opening is arranged in the board body and has a bottom and a stepped side wall surrounding the bottom, and the stepped side wall is connected to the upper surface. The power supply line is arranged on the bottom. The metal wall layer is arranged on the stepped side wall and is electrically separated from the power supply line. The shielding blind hole is arranged in the board body and is located between the bottom and the lower surface.

In at least one embodiment of the present invention, in the normal direction of the lower surface, the plurality of shielding blind holes do not overlap with the power supply line.

In at least one embodiment of the present invention, the board body includes a bottom layer, a middle layer and a top layer. The bottom layer has the bottom surface, and the plurality of shielding blind holes are arranged in the bottom layer. The middle layer is arranged on the bottom layer. The top layer is arranged on the middle layer and has the top surface.

In at least one embodiment of the present invention, the cavity opening includes a middle opening and a top opening. The middle opening is disposed in the middle layer and has a middle side wall and a middle opening width. The top opening is disposed in the top layer and has a top side wall and a top opening width, and the top opening width is greater than the middle opening width.

In at least one embodiment of the present invention, the metal wall layer includes a bottom section, a middle section and a top section. The bottom section is arranged on the bottom. The middle section is arranged on the middle side wall and connected to the bottom section. The top section is arranged on the top side wall and connected to the middle section.

In at least one embodiment of the present invention, the top section extends to the upper surface.

In at least one embodiment of the present invention, the intermediate layer includes a first sublayer and a second sublayer. The first sublayer is disposed on the bottom layer. The second sublayer is disposed on the first sublayer.

In at least one embodiment of the present invention, the middle opening includes a first opening and a second opening. The first opening is disposed in the first sublayer and has a first sidewall and a first opening width. The second opening is disposed in the second sublayer and has a second sidewall and a second opening width, and the second opening width is greater than the first opening width.

In at least one embodiment of the present invention, the middle section includes a first section and a second section. The first section is disposed on the first side wall and connected to the bottom section. The second section is disposed on the second side wall and connected to the first section and the top section.

A method for manufacturing a circuit board proposed in at least one embodiment of the present invention includes providing a bottom layer circuit structure having a top surface and a bottom surface opposite to the top surface. A peelable colloid is bonded to the top surface. An intermediate layer circuit structure and a top layer circuit structure are provided. The intermediate layer circuit structure is disposed between the bottom layer circuit structure and the top layer circuit structure to form a circuit stack. A plurality of shielding blind holes are formed on the bottom surface. A portion of the circuit stack is removed to form a temporary opening and a temporary circuit stack surrounded by the first temporary opening, wherein the temporary opening exposes a portion of the bottom layer circuit structure and has a temporary side wall. An initial metal wall layer is formed on the temporary side wall. A portion of the temporary circuit stack is removed to expose the peelable colloid and a portion of the initial metal wall layer is removed to form a metal wall layer. The peelable colloid and the remaining temporary circuit stack located on the peelable colloid are removed to form a cavity opening, the cavity opening having a bottom and a stepped side wall surrounding the bottom, and the metal wall layer is located on the stepped side wall. A power supply line is formed, the power supply line is located on the bottom and is electrically separated from the metal wall layer.

In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes, and deviations therefrom caused by actual processes and/or tolerances. For example, the flat surface shown in the drawings may have rough and/or nonlinear features, and the sharp corners shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly used for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the scope of the patent application of the present invention.

Secondly, the words "approximately", "approximately" or "substantially" used in the present invention not only cover the numerical values and numerical ranges clearly stated, but also cover the permissible deviation range that can be understood by a person of ordinary skill in the art to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by the limitations of the measurement system or process conditions, for example. For example, two objects (such as the planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include non-parallelism and non-perpendicularity caused by the permissible deviation range.

The spatially relative terms used in the present invention, such as "below", "under", "above", "on", etc., are for the purpose of facilitating the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped 180 degrees up and down, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in the present invention should also be interpreted in the same way.

It should be understood that, although the present invention may use terms such as "first", "second", and "third" to describe various components or features, these components or features should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one feature from another feature. In addition, the term "or" used in the present invention may include any one or more combinations of the related listed items depending on the actual situation.

Although a series of operations or steps are used in the present invention to illustrate the manufacturing method, the order in which these operations or steps are shown should not be interpreted as a limitation of the present invention. For example, certain operations or steps can be performed in different orders and/or simultaneously with other steps. In addition, each operation or step described herein can include a plurality of sub-steps or actions.

In addition, the present invention may be implemented or applied through other different specific embodiments, and the details of the present invention may also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

FIG1 is a partial cross-sectional schematic diagram of a circuit board of at least one embodiment of the present invention. Referring to FIG1 , the circuit board 1 includes a board body 10, a cavity opening 20, a power supply line PC, a metal wall layer 30, and a plurality of shielding blind holes BH. The board body 10 has an upper surface US and a lower surface LS opposite to the upper surface US. The cavity opening 20 is disposed in the board body 10 and has a bottom BT and a stepped side wall SW surrounding the bottom BT, and the stepped side wall SW is connected to the upper surface US. The power supply line PC is disposed on the bottom BT. The metal wall layer 30 is disposed on the stepped side wall SW and is electrically separated from the power supply line PC. The shielding blind hole BH is disposed in the board body 10 and is located between the bottom BT and the lower surface LS.

By means of the above structural design, a cavity opening with stepped sidewalls is arranged in the board body of the circuit board to form a circuit board with a vertical cavity waveguide structure, which makes it easy to combine the cavity waveguide structure into the circuit board, thereby improving the integration of the circuit board. Since air can be stored in the cavity opening, the cavity opening has a smaller dielectric constant, thereby improving the signal transmission capability. In addition, a metal wall layer is arranged on the aforementioned stepped sidewalls to improve the shielding capability and reduce radiation loss.

Please continue to refer to FIG. 1. The board 10 includes a bottom layer 11, an intermediate layer 12 disposed on the bottom layer 11, and a top layer 13 disposed on the intermediate layer 12. The top layer 13 is disposed on the intermediate layer 12 and has an upper surface US, while the bottom layer 11 has a lower surface LS, and the shielding blind hole BH is disposed in the bottom layer 11. As shown in FIG. 1, the bottom layer 11, the intermediate layer 12, and the top layer 13 may include an insulating layer (not shown) and a circuit layer (not shown). In addition, in the normal direction of the lower surface LS, the shielding blind hole BH does not overlap with the power supply line PC. As shown in FIG. 1 , the shielding blind via BH is electrically connected to the metal wall layer 30 through the circuit layer located at the bottom BT, and the shielding blind via BH is electrically connected to the metal coating (not shown) located on the lower surface LS. The above-mentioned design can further enhance the shielding capability of the metal wall layer 30 and the shielding blind via BH.

The cavity opening 20 includes a middle opening 21 and a top opening 22. The middle opening 21 is disposed in the middle layer 12 and has a middle side wall SWM, and the top opening 22 is disposed in the top layer 13 and has a top side wall SWU. As shown in FIG1 , the middle opening 21 has middle opening widths W1 and W2, and the top opening 22 has a top opening width W, and the top opening width W is greater than the middle opening widths W1 and W2. By designing the aforementioned opening widths, the middle side wall SWM and the top side wall SWU can form the aforementioned stepped side wall SW.

The metal wall layer 30 includes a bottom section 31, a middle section 32, and a top section 33. The bottom section 31 is disposed on the bottom BT of the cavity opening 20, the middle section 32 is disposed on the middle side wall SWM and connected to the bottom section 31, and the top section 33 is disposed on the top side wall SWU and connected to the middle section 32. In other words, the bottom section 31 is disposed on the top surface of the bottom layer 11, the middle section 32 is disposed on the side surface of the middle layer 12 and connected to the bottom section 31, and the top section 33 is disposed on the side surface of the top layer 13 and connected to the middle section 32. Therefore, the metal wall layer 30 is a continuous and complete metal layer formed on the stepped side wall SW, so it can have better shielding ability and higher reliability. In some embodiments, the top section 33 can extend to the upper surface US of the board 10, that is, the top surface of the top layer 13.

Please continue to refer to FIG. 1 . The middle layer 12 includes a first sublayer 121 and a second sublayer 122 . The first sublayer 121 is disposed on the bottom layer 11 , and the second sublayer 122 is disposed on the first sublayer 121 . The first sublayer 121 and the second sublayer 122 may include an insulating layer (not labeled) and a circuit layer (not labeled). The middle opening 21 includes a first opening 211 and a second opening 212. The first opening 211 is disposed in the first sub-layer 121 and has a first side wall SW1 and a first opening width W1. The second opening 212 is disposed in the second sub-layer 122 and has a second side wall SW2 and a second opening width W2. The second opening width W2 is greater than the first opening width W1. By designing the opening width, the first side wall SW1 and the second side wall SW2 of the top side wall SWU and the middle side wall SWM can form the above-mentioned stepped side wall SW.

As shown in FIG1 , the middle section 32 includes a first section 321 and a second section 322. The first section 321 is disposed on the first side wall SW1 and connected to the bottom section 31, and the second section 322 is disposed on the second side wall SW2 and connected to the first section 321 and the top section 33. In other words, the first section 321 is disposed on the side and top surfaces of the first sub-layer 121 and connected to the bottom section 31, and the second section 322 is disposed on the side and top surfaces of the second sub-layer 122 and connected to the first section 321 and the top section 33.

FIG. 2A to FIG. 2M are partial cross-sectional views of a circuit board of at least one embodiment of the present invention at different process stages. Referring to FIG. 2A to FIG. 2C, as shown in FIG. 2A, a bottom layer circuit structure 11' is provided, which has a top surface S1 and a bottom surface S2 opposite to the top surface S1. As shown in FIG. 2B, a peelable colloid G is attached to the top surface S1. As shown in FIG. 2C, an intermediate layer circuit structure 12' and a top layer circuit structure 13' are provided, and the intermediate layer circuit structure 12' is disposed between the bottom layer circuit structure 11' and the top layer circuit structure 13' to form a circuit stack 10'. In some embodiments, the circuit stack 10' can be formed by a build-up method. In addition, the circuit stack 10' has an initial upper surface US' and an initial lower surface LS' opposite to the initial upper surface US', and the initial lower surface LS' is the bottom surface S2 of the bottom layer circuit structure 11'.

Please refer to Figures 2D to 2F, a plurality of shielding blind holes BH are formed on the bottom surface S2. First, as shown in Figure 2D, a plurality of initial blind holes BH' are formed on the bottom surface S2. In some embodiments, the initial blind holes BH' can be formed by a laser drilling process. Then, as shown in Figure 2E, a blind hole metal layer BM is formed on the hole wall of the initial blind hole BH'. In some embodiments, the blind hole metal layer BM can be formed by electroless plating, wherein the material of the blind hole metal layer BM can include copper. As shown in Figure 2F, a metal material F is formed in the initial blind hole BH' to form a shielding blind hole BH, wherein the metal material F can be formed by electric plating. Alternatively, the metal material F can be a conductive paste such as copper paste or silver paste.

2G , a metal cladding layer CL is formed on the initial upper surface US′ and the initial lower surface LS′ of the circuit stack 10′. In some embodiments, the metal cladding layer CL may be formed by an electric plating process, and the material of the metal cladding layer CL may include copper.

Referring to FIG. 2H , a portion of the circuit stack 10′ is removed to form a temporary opening 20′ and a temporary circuit stack TL surrounded by the temporary opening 20′, wherein the temporary opening 20′ exposes a portion of the bottom wiring structure 11′ and has a temporary sidewall TSW. Specifically, a portion of the circuit stack 10′ is removed downward from the initial upper surface US′ of the circuit stack 10′ to form the temporary opening 20′, wherein the temporary opening 20′ exposes a portion of the bottom wiring structure 11′ and has a stepped temporary sidewall TSW. In some embodiments, the temporary opening 20′ may be formed by a machining process, such as routing. As shown in FIG2H , the temporary opening 20 ′ exposes the circuit layers (not shown) of the bottom circuit structure 11 ′, the middle circuit structure 12 ′ and the top circuit structure 13 ′. The vertical depth and horizontal position of the groove can be determined by the position of each circuit layer to improve the positioning accuracy of the groove.

Please refer to FIG. 2I , an initial metal wall layer 30′ is formed on the temporary sidewall TSW. In some embodiments, the initial metal wall layer 30′ can be formed by electroless plating and electric plating, wherein the material of the initial metal wall layer 30′ can include copper. In some embodiments, the initial metal wall layer 30′ can be formed by electric plating, as shown in FIG. 2I , the circuit layers of the bottom wiring structure 11′, the middle wiring structure 12′, and the top wiring structure 13′ exposed by the temporary opening 20′ can increase the plating rate and improve the uniformity of the coating, and can also reduce the problem of too thin film thickness at the turning point, or even broken lines.

2J , a portion of the temporary circuit stack TL is removed to expose the strippable gel G and a portion of the initial metal wall layer 30′ is removed to form the metal wall layer 30. In detail, a portion of the temporary circuit stack TL is removed downward from the top surface of the temporary circuit stack TL to expose the strippable gel G, and a portion of the initial metal wall layer 30′ located on the top surface and the side surface of the temporary circuit stack TL is removed to form the metal wall layer 30. In some embodiments, a portion of the temporary circuit stack TL and a portion of the initial metal wall layer 30′ can be removed by a machining process (e.g., profile cutting).

2K , the peelable gel G and the remaining temporary circuit stack TL on the peelable gel G are removed to form a cavity opening 20. The cavity opening 20 has a bottom BT and a stepped sidewall SW surrounding the bottom, and a metal wall layer 30 is located on the stepped sidewall SW.

Referring to FIG. 2L , a power supply circuit PC is formed, and the power supply circuit PC is located on the bottom BT and electrically separated from the metal wall layer 30. In some embodiments, the power supply circuit PC can be formed by a lithography process and an etching process. As shown in FIG. 2L , the circuit stack 10' forms the board 10, and the bottom layer circuit structure 11', the middle layer circuit structure 12' and the top layer circuit structure 13' respectively form the bottom layer 11, the middle layer 12 and the top layer 13 of the board 10.

Please refer to Figure 2M. A solder mask layer SM and a surface treatment layer SF can be formed on the upper surface US and the lower surface LS of the board body 10 to complete the circuit board 1. In some embodiments, the solder mask layer SM can be formed by a printing process, and the material of the solder mask layer SM can be ink or resin. In some embodiments, the surface treatment layer SF can be formed by a tinning process or a tinning process. Alternatively, the surface treatment layer SF can also be a nickel layer. However, the present invention is not limited to this. In other embodiments, the circuit board 1 can be completed without forming the solder mask layer SM and the surface treatment layer SF, as shown in Figure 2L.

In summary, in the circuit board and the manufacturing method thereof of at least one embodiment of the present invention, a cavity opening with a stepped sidewall can be arranged in the board body of the circuit board to form a circuit board with a vertical cavity waveguide structure, which makes it easy to combine the cavity waveguide structure into the circuit board, thereby improving the integration of the circuit board. Since air can be stored in the cavity opening, the cavity opening has a smaller dielectric constant, thereby improving the signal transmission capability. Furthermore, a metal wall layer is arranged on the aforementioned stepped sidewall to improve the shielding capability, which can reduce radiation loss. In addition, the circuit board manufacturing method of at least one embodiment of the present invention forms a cavity opening by removing the circuit structure, which can avoid problems such as cavity slot alignment deviation and glue overflowing into the cavity, and forms a metal wall layer by a one-time electroplating method, which can reduce problems such as discontinuity or incompleteness of the metal wall layer, thereby improving the yield.

Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. A person having ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

1: Circuit board

10: Board

10’: Circuit stacking

11: Bottom layer

11’: Bottom layer wiring structure

12: Middle layer

12’: Middle layer circuit structure

13: Top floor

13’: Top layer circuit structure

121: First sublayer

122: Second sublayer

20: Cavity opening

20’: Temporary opening

21: Middle opening

22: Top opening

211: First opening

212: Second opening

30:Metal wall

30’: Initial metal wall

31: Bottom section

32: Middle section

33: Top section

321: Section 1

322: Second Section

BH: Shielded Blind Hole

BH’: Initial blind hole

BT: Bottom

G: Peelable colloid

LS: Lower surface

LS’: Initial lower surface

PC: Power supply line

S1: Top

S2: Bottom

SF: Surface treatment layer

SM: Solder Mask

SW: Stepped sidewalls

SW1: First side wall

SW2: Second side wall

SWM: Middle side wall

SWU: Top side wall

TL: Temporary Line Layer

TSW: Temporary Sidewall

US: Upper surface

US’: Initial upper surface

W: Top opening width

W1: First opening width

W2: Second opening width

FIG1 is a partial cross-sectional schematic diagram of a circuit board according to at least one embodiment of the present invention; and FIG2A to FIG2M are partial cross-sectional diagrams of a circuit board according to at least one embodiment of the present invention at different process stages.

Domestic storage information (please note the order of storage institution, date, and number) None Overseas storage information (please note the order of storage country, institution, date, and number) None

1: Circuit board

10: Board

11: Bottom layer

12: Middle layer

13: Top floor

121: First sublayer

122: Second sublayer

20: Cavity opening

21: Middle opening

22: Top opening

211: First opening

212: Second opening

30:Metal wall layer

31: Bottom section

32: Middle section

33: Top section

321: Section 1

322: Second section

BH: Shielded Blind Hole

BT:Bottom

LS: Lower surface

PC: power supply line

SW: Stepped sidewalls

SW1: First side wall

SW2: Second side wall

SWM: Middle side wall

SWU: top side wall

US: Upper surface

W: Top opening width

W1: First opening width

W2: Second opening width

Claims (9)

A circuit board comprises: a board body having an upper surface and a lower surface opposite to the upper surface; a cavity opening arranged in the board body and having a bottom and a stepped side wall surrounding the bottom, wherein the stepped side wall is connected to the upper surface; a power supply circuit arranged on the bottom; a metal wall layer arranged on the stepped side wall and electrically separated from the power supply circuit; and a plurality of shielding blind holes arranged in the board body and located between the bottom and the lower surface, wherein in a normal direction of the lower surface, the plurality of shielding blind holes do not overlap with the power supply circuit. A circuit board as described in claim 1, wherein the board body comprises: a bottom layer having the bottom surface, wherein the plurality of shielding blind holes are arranged in the bottom layer; a middle layer arranged on the bottom layer; and a top layer arranged on the middle layer and having the top surface. A circuit board as described in claim 2, wherein the cavity opening includes: a middle opening disposed in the middle layer and having a middle side wall and a middle opening width; and a top opening disposed in the top layer and having a top side wall and a top opening width, wherein the top opening width is greater than the middle opening width. A circuit board as described in claim 3, wherein the metal wall layer includes: a bottom section disposed on the bottom; a middle section disposed on the middle side wall and connected to the bottom section; and a top section disposed on the top side wall and connected to the middle section. A circuit board as described in claim 4, wherein the top section extends to the upper surface. A circuit board as described in claim 4, wherein the intermediate layer includes: a first sublayer disposed on the bottom layer; and a second sublayer disposed on the first sublayer. A circuit board as described in claim 6, wherein the middle opening comprises: a first opening disposed in the first sublayer and having a first sidewall and a first opening width; and a second opening disposed in the second sublayer and having a second sidewall and a second opening width, wherein the second opening width is greater than the first opening width. A circuit board as described in claim 7, wherein the middle section includes: a first section disposed on the first side wall and connected to the bottom section; and a second section disposed on the second side wall and connected to the first section and the top section. A method for manufacturing a circuit board includes: providing a bottom layer circuit structure having a top surface and a bottom surface opposite to the top surface; attaching a peelable colloid to the top surface; providing an intermediate layer circuit structure and a top layer circuit structure; arranging the intermediate layer circuit structure between the bottom layer circuit structure and the top layer circuit structure to form a circuit stack; forming a plurality of shielding blind holes on the bottom surface; removing part of the circuit stack to form a temporary opening and a temporary circuit stack surrounded by the temporary opening, wherein the temporary opening exposes part of the bottom layer circuit structure and has a temporary side wall; forming an initial metal wall layer on the temporary side wall; removing part of the temporary circuit stack to expose the strippable colloid and removing part of the initial metal wall layer to form a metal wall layer; removing the strippable colloid and the remaining temporary circuit stack on the strippable colloid to form a cavity opening, wherein the cavity opening has a bottom and a stepped side wall surrounding the bottom, and the metal wall layer is located on the stepped side wall; and forming a power supply line, wherein the power supply line is located on the bottom and electrically separated from the metal wall layer.

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