CN119893819A - Circuit board and manufacturing method thereof - Google Patents

Abstract

A circuit board comprises a board body, a cavity opening, a power supply circuit, a metal wall layer and a plurality of shielding blind holes. The board body has an upper surface and a lower surface opposite to the upper surface. The cavity opening is arranged in the board body and has a bottom and a stepped side wall surrounding the bottom, and the stepped side wall is connected to the upper surface. The power supply circuit is arranged on the bottom. The metal wall layer is arranged on the stepped side wall and is electrically separated from the power supply circuit. The shielding blind hole is arranged in the board body and is located between the bottom and the lower surface. The above-mentioned circuit board can improve the integration of the circuit board.

Description

Circuit board and manufacturing method thereof

Technical Field

The present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a circuit board having a cavity opening with a stepped side wall and a method for manufacturing the same.

Background

With the development of electronic products toward light weight and miniaturization, more and more products combine a cavity waveguide with a circuit board, and the cavity waveguide can completely transmit signals through the low signal loss characteristic of air, wherein the cavity waveguide can be applied to radar products for vehicles, for example. However, the lamination of the multi-layer structure to form the circuit board with the cavity may cause problems such as misalignment of the cavity, discontinuous metal layer on the side wall of the cavity, and overflow of glue into the cavity, which may cause difficulty in improving or even reducing the yield.

Disclosure of Invention

At least one embodiment of the invention provides a circuit board with a cavity opening with a step-shaped side wall and a metal wall layer arranged on the step-shaped side wall, which can improve the integration of the circuit board.

At least one embodiment of the present invention provides a method for manufacturing the circuit board, so as to help to improve the yield of the circuit board.

The invention provides a circuit board, which comprises a board body, a cavity opening, a power supply circuit, a metal wall layer and a plurality of shielding blind holes. The plate body is provided with an upper surface and a lower surface opposite to the upper surface. The cavity opening is arranged in the plate body and is provided with a bottom and a stepped side wall surrounding the bottom, and the stepped side wall is connected with the upper surface. The power supply circuit is arranged on the bottom. The metal wall layer is arranged on the stepped side wall and is electrically separated from the power supply circuit. The shielding blind hole is arranged in the plate body and is positioned between the bottom and the lower surface.

In at least one embodiment of the present invention, the plurality of blind shielding holes do not overlap with the power supply line in a normal direction of the lower surface.

In at least one embodiment of the present invention, the plate includes a bottom layer, a middle layer, and a top layer. The bottom layer is provided with the lower surface, and the shielding blind holes are arranged in the bottom layer. The middle layer is arranged on the bottom layer. The top layer is arranged on the middle layer and provided with the upper surface.

In at least one embodiment of the present invention, the cavity opening includes a middle opening and a top opening. The intermediate opening is disposed in the intermediate layer and has an intermediate sidewall and an intermediate opening width. The top opening is disposed in the top layer and has a top sidewall and a top opening width, the top opening width being greater than the middle opening width.

In at least one embodiment of the present invention, the metal wall layer includes a bottom section, a middle section, and a top section. A bottom section is disposed on the bottom. The middle section is disposed on the middle sidewall and connects to the bottom section. A top section is disposed on the top sidewall and connects to the middle section.

In at least one embodiment of the invention, the top section extends to the upper surface.

In at least one embodiment of the present invention, the intermediate layer includes a first sub-layer and a second sub-layer. The first sub-layer is arranged on the bottom layer. The second sub-layer is arranged on the first sub-layer.

In at least one embodiment of the invention, the intermediate opening comprises a first opening and a second opening. The first opening is arranged in the first sub-layer, has a first side wall and has a first opening width. The second opening is arranged in the second sub-layer, is provided with a second side wall and a second opening width, and the second opening width is larger than the first opening width.

In at least one embodiment of the present invention, the intermediate section includes a first section and a second section. The first section is disposed on the first sidewall and connected to the bottom section. The second section is arranged on the second side wall and connected with the first section and the top section.

The invention provides a manufacturing method of a circuit board, which comprises providing a bottom layer circuit structure with a top surface and a bottom surface opposite to the top surface. And attaching a strippable colloid on the top surface. An intermediate layer circuit structure and a top layer circuit structure are provided. The middle layer circuit structure is arranged between the bottom layer circuit structure and the top layer circuit structure to form a circuit lamination. And forming a plurality of shielding blind holes on the bottom surface. Removing a portion of the wiring stack to form a temporary opening and a temporary wiring stack surrounded by the first temporary opening, the temporary opening exposing a portion of the underlying wiring structure and having temporary sidewalls. An initial metal wall layer is formed on the temporary sidewalls. Removing part of the temporary circuit layer stack to expose the strippable glue and removing part of the initial metal wall layer to form a metal wall layer. Removing the peelable glue and the remaining temporary circuit stack on the peelable glue to form a cavity opening, wherein the cavity opening is provided with a bottom and a stepped side wall surrounding the bottom, and the metal wall layer is positioned on the stepped side wall. And forming a power supply circuit which is positioned on the bottom and is electrically separated from the metal wall layer.

Drawings

FIG. 1 is a schematic partial cross-sectional view of a circuit board according to at least one embodiment of the invention;

fig. 2A-2M are partial cross-sectional views of a circuit board at various stages of processing according to at least one embodiment of the present invention.

Detailed Description

In the following text, the dimensions (e.g., length, width, thickness and depth) of elements (e.g., layers, films, substrates, regions, etc.) in the drawings are exaggerated in an unequal manner and the number of elements is reduced for clarity in the technical features of the present invention. Accordingly, the following description and illustrations of embodiments are not limited to the number of elements in the figures and the sizes and shapes presented by the elements, but rather are intended to cover deviations in size, shape and both as a result of actual processes and/or tolerances. For example, the planar surface shown in the figures may have rough and/or non-linear features, while the acute angles shown in the figures may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to precisely describe the actual shapes of the elements, nor to limit the claims of the present invention.

Furthermore, the terms "about," "approximately" or "substantially" as used herein are not only inclusive of the values and ranges of values explicitly recited, but also are inclusive of the permissible deviations as understood by those skilled in the art, wherein the deviations may be determined by errors occurring during measurement, e.g., due to limitations in both the measurement system and process conditions. For example, two objects (e.g., planes or traces of a substrate) "substantially parallel" or "substantially perpendicular," wherein "substantially parallel" and "substantially perpendicular" respectively represent parallel and perpendicular between the two objects may include non-parallel and non-perpendicular due to allowable deviation ranges.

Spatially relative terms, such as "under", "beneath", "over" and the like, may be used herein for convenience in describing the relative relationship of one element or feature to another element or feature as illustrated in the figures. The true meaning of these spatially relative terms encompasses other orientations. For example, when the drawing is turned over 180 degrees up and down, the relationship between one element and another element might be changed from "below," below, "to" above, "" over. In addition, the spatially relative descriptions used in the present invention should be construed as such.

It should be understood that although the invention may be described using terms such as "first," "second," "third," etc., these elements or features should not be limited by these terms. These terms are used primarily to distinguish one element from another element or feature from another feature. In addition, the term "or" as used herein shall be taken to include any one or a combination of more of the associated listed items as the case may be.

Although the present invention has been described in terms of a series of operations or steps, the order in which the operations or steps are performed should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Furthermore, each operation or step described herein may comprise several sub-steps or actions.

Furthermore, the invention is capable of other and different embodiments and its several details are capable of modification and various other respects, all without departing from the spirit of the present invention.

Fig. 1 is a schematic partial cross-sectional view of a circuit board according to at least one embodiment of the invention. Referring to fig. 1, a circuit board 1 includes a board body 10, a cavity opening 20, a power supply circuit PC, a metal wall layer 30, and a plurality of shielding blind holes BH. The plate body 10 has an upper surface US and a lower surface LS opposite to the upper surface US. The cavity opening 20 is disposed in the plate body 10, and has a bottom BT and a stepped sidewall SW surrounding the bottom BT, and the stepped sidewall SW is connected to the upper surface US. The power supply line PC is disposed on the bottom BT. The metal wall layer 30 is disposed on the stepped sidewall SW and electrically separated from the power supply circuit PC. The shielding blind hole BH is disposed in the board body 10 and located between the bottom BT and the lower surface LS.

Through the structural design, the cavity opening with the stepped side wall is arranged in the board body of the circuit board, so that the circuit board with the vertical cavity waveguide structure is formed, the cavity waveguide structure is easy to be combined in the circuit board, and the integration of the circuit board is further improved. Because air can be stored in the cavity opening, the cavity opening has smaller dielectric constant, and the signal transmission capability can be improved. In addition, the metal wall layer is arranged on the stepped side wall to improve shielding capability, so that radiation loss can be reduced.

With continued reference to fig. 1, the board 10 includes a bottom layer 11, a middle layer 12 disposed on the bottom layer 11, and a top layer 13 disposed on the middle layer 12. The top layer 13 is disposed on the middle layer 12 and has an upper surface US, while the bottom layer 11 has a lower surface LS, and the shielding blind holes BH are disposed in the bottom layer 11. As shown in fig. 1, the bottom layer 11, the middle layer 12 and the top layer 13 may include an insulating layer (not shown) and a wiring layer (not shown). In addition, in the normal direction of the lower surface LS, the shielding blind hole BH does not overlap with the power supply line PC. As shown in fig. 1, the shielding blind hole BH is electrically connected to the metal wall layer 30 through the circuit layer at the bottom BT, and the shielding blind hole BH is electrically connected to the metal coating layer (not labeled) on the lower surface LS, so that the shielding capability of the metal wall layer 30 and the shielding blind hole BH can be further improved through the above design.

The cavity opening 20 includes a central opening 21 and a top opening 22. Intermediate opening 21 is provided in intermediate layer 12 and has intermediate side walls SWM, and top opening 22 is provided in top layer 13 and has top side walls SWU. As shown in fig. 1, the intermediate opening 21 has intermediate opening widths W1, W2, the top opening 22 has a top opening width W, and the top opening width W is larger than the intermediate opening widths W1, W2. The intermediate side wall SWM and the top side wall SWU may form the stepped side wall SW by the design of the opening width.

The metal wall layer 30 includes a bottom section 31, a middle section 32, and a top section 33. The bottom section 31 is disposed on the bottom BT of the cavity opening 20, the middle section 32 is disposed on the middle sidewall SWM and connects the bottom section 31, and the top section 33 is disposed on the top sidewall SWU and connects the middle section 32. In other words, the bottom section 31 is disposed on the top surface of the bottom layer 11, the middle section 32 is disposed on the side surface of the middle layer 12 and connects the bottom section 31, and the top section 33 is disposed on the side surface of the top layer 13 and connects the middle section 32. Therefore, the metal wall layer 30 is a continuous and complete metal layer formed on the step-shaped side wall SW, so that the shielding capability and the reliability are improved. In some embodiments, top section 33 may extend to upper surface US of plate body 10, i.e., the top surface of top layer 13.

With continued reference to fig. 1, the intermediate layer 12 includes a first sub-layer 121 and a second sub-layer 122, the first sub-layer 121 is disposed on the bottom layer 11, the second sub-layer 122 is disposed on the first sub-layer 121, and the first sub-layer 121 and the second sub-layer 122 may include an insulating layer (not labeled) and a circuit layer (not labeled). The middle opening 21 includes a first opening 211 and a second opening 212, the first opening 211 is disposed in the first sub-layer 121 and has a first sidewall SW1 and a first opening width W1, the second opening 212 is disposed in the second sub-layer 122 and has a second sidewall SW2 and a second opening width W2, and the second opening width W2 is greater than the first opening width W1. The first and second sidewalls SW1 and SW2 of the top and middle sidewalls SWU and SWM may form the stepped sidewall SW by the design of the opening width.

As shown in fig. 1, the middle section 32 includes a first section 321 and a second section 322, the first section 321 is disposed on the first side wall SW1 and connected to the bottom section 31, and the second section 322 is disposed on the second side wall SW2 and connected to the first section 321 and the top section 33. In other words, the first section 321 is disposed on the side and top surfaces of the first sub-layer 121 and connects the bottom section 31, and the second section 322 is disposed on the side and top surfaces of the second sub-layer 122 and connects the first section 321 and the top section 33.

Fig. 2A-2M are partial cross-sectional views of a circuit board at various stages of processing according to at least one embodiment of the present invention. Referring to fig. 2A to 2C, as shown in fig. 2A, an underlying circuit structure 11' is provided, which has a top surface S1 and a bottom surface S2 opposite to the top surface S1. As shown in fig. 2B, a peelable glue G is attached to the top surface S1. As shown in fig. 2C, an intermediate layer wire structure 12 'and a top layer wire structure 13' are provided, and the intermediate layer wire structure 12 'is disposed between the bottom layer wire structure 11' and the top layer wire structure 13 'to form a wire stack 10'. In some embodiments, the wiring stack 10' may be formed by a build-up process. In addition, the circuit stack 10 'has an initial upper surface US' and an initial lower surface LS 'opposite to the initial upper surface US', and the initial lower surface LS 'is the bottom surface S2 of the underlying circuit structure 11'.

Referring to fig. 2D to 2F, a plurality of shielding blind holes BH are formed in the bottom surface S2. First, as shown in fig. 2D, a plurality of initial blind holes BH' are formed in the bottom surface S2. In some embodiments, the initial blind hole BH' may be formed by a laser drilling process. Next, as shown in fig. 2E, a blind via metal layer BM is formed on the walls of the initial blind via BH'. In some embodiments, the blind via metal layer BM may be formed using electroless plating, wherein the material of the blind via metal layer BM may comprise copper. As shown in fig. 2F, a metal material F is formed in the initial blind hole BH' to form a shielding blind hole BH, wherein the metal material F may be formed by electroplating. Or the metal material F may be a conductive colloid such as copper paste or silver paste.

Referring to fig. 2G, a metal layer CL is formed on the initial upper surface US ' and the initial lower surface LS ' of the circuit stack 10', respectively. In some embodiments, the metal cap layer CL may be formed by an electroplating process, and the material of the metal cap layer CL may include copper.

Referring to fig. 2H, a portion of the wiring stack 10' is removed to form a temporary opening 20' and a temporary wiring stack TL surrounded by the temporary opening 20', the temporary opening 20' exposing a portion of the underlying wiring structure 11' and having temporary sidewalls TSW. In detail, a portion of the wiring stack 10 'is removed from the initial upper surface US' of the wiring stack 10 'downward to form a temporary opening 20', and the temporary opening 20 'exposes a portion of the underlying wiring structure 11' and has a stepped temporary sidewall TSW. In some embodiments, the temporary opening 20' may be formed by a machining process, such as form cutting (routing). As shown in fig. 2H, the temporary opening 20 'exposes the circuit layers (not shown) of the bottom circuit structure 11', the middle circuit structure 12 'and the top circuit structure 13', and the vertical depth and the horizontal position of the fishing groove can be determined by the positions of the circuit layers, so as to improve the positioning accuracy of the fishing groove.

Referring to fig. 2I, an initial metal wall layer 30' is formed on the temporary sidewall TSW. In some embodiments, the initial metal wall layer 30 'may be formed by electroless plating and electroless plating, wherein the material of the initial metal wall layer 30' may comprise copper. In some embodiments, the initial metal wall layer 30' may be formed by electroplating, as shown in fig. 2I, the circuit layers of the bottom circuit structure 11', the middle circuit structure 12', and the top circuit structure 13' exposed by the temporary opening 20' may increase the electroplating rate and improve the uniformity of the plating film, and may reduce the problems of too thin film thickness and even wire breakage of the plating film at the turning point.

Referring to fig. 2J, a portion of the temporary circuit layer TL is removed to expose the strippable glue G and a portion of the initial metal wall layer 30' is removed to form the metal wall layer 30. In detail, a portion of the temporary wiring stack TL is removed downward from the top surface of the temporary wiring stack TL to expose the strippable glue G, and a portion of the initial metal wall layer 30' located on the top and side surfaces of the temporary wiring stack TL is removed at the same time to form the metal wall layer 30. In some embodiments, portions of the temporary wiring stack TL and portions of the initial metal wall layer 30' may be removed by a machining process (e.g., form cutting).

Referring to fig. 2K, the peelable gel G and the remaining temporary circuit stack TL on the peelable gel G are removed to form the cavity opening 20. The cavity opening 20 has a bottom BT and a stepped sidewall SW surrounding the bottom, and the metal wall layer 30 is located on the stepped sidewall SW.

Referring to fig. 2L, a power supply line PC is formed, and the power supply line PC is located on the bottom BT and electrically separated from the metal wall layer 30. In some embodiments, the power supply line PC may be formed by a photolithography process and an etching process. As shown in fig. 2L, the wiring stack 10 'forms a board body 10, and the bottom layer wiring structure 11', the middle layer wiring structure 12', and the top layer wiring structure 13' form a bottom layer 11, a middle layer 12, and a top layer 13 of the board body 10, respectively.

Referring to fig. 2M, a solder mask SM and a surface treatment layer SF can be formed on the upper surface US and the lower surface LS of the board body 10 to complete the circuit board 1. In some embodiments, the solder mask layer SM may be formed by a printing process, and the material of the solder mask layer SM may be ink or resin. In some embodiments, the surface treatment layer SF may be formed by a tin plating process or a tin spraying process. Or the surface treatment layer SF may be a nickel-gold layer. However, the invention is not limited thereto, and in other embodiments, the circuit board 1 may be completed without forming the solder mask layer SM and the surface treatment layer SF, as shown in fig. 2L.

In summary, in the circuit board and the method for manufacturing the same according to at least one embodiment of the invention, the cavity opening with the stepped sidewall is disposed in the board body of the circuit board to form the circuit board with the vertical cavity waveguide structure, so that the cavity waveguide structure is easy to be combined in the circuit board, and the integration of the circuit board is improved. Because air can be stored in the cavity opening, the cavity opening has smaller dielectric constant, and the signal transmission capability can be improved. Furthermore, the metal wall layer is disposed on the stepped sidewall to improve shielding capability, so as to reduce radiation loss. In addition, the circuit board manufacturing method of at least one embodiment of the invention forms the cavity opening by removing the circuit structure, so that the problems of misalignment of the cavity groove body, overflow of glue into the cavity and the like can be avoided, and the metal wall layer is formed by one-time electroplating, so that the problems of discontinuity or incomplete metal wall layer and the like can be reduced, and the yield is improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified and practiced by those skilled in the art without departing from the spirit and scope of the present invention.

[ Symbolic description ]

1 Circuit Board

10 Plate body

10': Line stack

11 Bottom layer

11': Underlying circuit structure

12 Intermediate layer

12': Intermediate layer line structure

Top layer 13

13': Top layer line Structure

121 First sublayer

122 Second sub-layer

20 Cavity opening

20': Temporary opening

21-Intermediate opening

22 Top opening

211 First opening

212 Second opening

30 Metal wall layer

30': Initial metal wall layer

31 Bottom section

32 Intermediate section

33 Top section

321 First section

322 Second section

BH shielding blind hole

BH'

BT bottom

G, strippable colloid

LS lower surface

LS': initial lower surface

PC power supply circuit

S1. Top surface

S2, bottom surface

SF surface treatment layer

SM solder mask layer

SW stepped sidewall

SW1 first sidewall

SW2 second side wall

SWM middle sidewall

SWU Top sidewall

TL temporary line lamination

TSW temporary sidewall

US upper surface

US': initial upper surface

Width of top opening

W1 first opening width

W2, second opening width.

Claims (10)

1.A circuit board, comprising:

a plate body having an upper surface and a lower surface opposite to the upper surface;

The cavity opening is arranged in the plate body and is provided with a bottom and a stepped side wall surrounding the bottom, wherein the stepped side wall is connected with the upper surface;

A power supply line disposed on the bottom;

A metal wall layer disposed on the stepped side wall and electrically separated from the power supply circuit, and

The shielding blind holes are arranged in the plate body and are positioned between the bottom and the lower surface.

2. The circuit board of claim 1, wherein the plurality of blind shielding holes do not overlap the power supply line in a direction normal to the lower surface.

3. The circuit board of claim 1, wherein the board body comprises:

a bottom layer having the lower surface, wherein the plurality of blind shielding holes are disposed in the bottom layer;

an intermediate layer disposed on the bottom layer, and

And a top layer disposed on the middle layer and having the upper surface.

4. A circuit board according to claim 3, wherein the cavity opening comprises:

A middle opening provided in the middle layer and having a middle sidewall and a middle opening width, and

A top opening disposed in the top layer and having a top sidewall and having a top opening width, wherein the top opening width is greater than the middle opening width.

5. The circuit board of claim 4, wherein the metal wall layer comprises:

a bottom section disposed on the bottom;

a middle section disposed on the middle sidewall and connected to the bottom section, and

And a top section disposed on the top sidewall and connected to the middle section.

6. The circuit board of claim 5, wherein the top section extends to the upper surface.

7. The circuit board of claim 5, wherein the intermediate layer comprises:

A first sub-layer disposed on the bottom layer, and

And the second sub-layer is arranged on the first sub-layer.

8. The circuit board of claim 7, wherein the intermediate opening comprises:

a first opening arranged in the first sub-layer and having a first sidewall and a first opening width, and

And the second opening is arranged in the second sub-layer, is provided with a second side wall and a second opening width, wherein the second opening width is larger than the first opening width.

9. The circuit board of claim 8, wherein the intermediate section comprises:

a first section disposed on the first sidewall and connected to the bottom section, and

And the second section is arranged on the second side wall and is connected with the first section and the top section.

10. A method of manufacturing a circuit board, comprising:

Providing a bottom layer circuit structure, which is provided with a top surface and a bottom surface opposite to the top surface;

attaching a strippable glue to the top surface;

providing a middle layer circuit structure and a top layer circuit structure;

Disposing the middle layer of wiring structure between the bottom layer of wiring structure and the top layer of wiring structure to form a wiring stack;

forming a plurality of shielding blind holes on the bottom surface;

removing a portion of the wiring stack to form a temporary opening and a temporary wiring stack surrounded by the temporary opening, wherein the temporary opening exposes a portion of the underlying wiring structure and has temporary sidewalls;

Forming an initial metal wall layer on the temporary side wall;

removing a portion of the temporary circuit stack to expose the strippable glue and removing a portion of the initial metal wall layer to form a metal wall layer;

removing the peelable glue and the remaining temporary circuit stack on the peelable glue to form a cavity opening, wherein the cavity opening has a bottom and a stepped sidewall surrounding the bottom, the metal wall layer is on the stepped sidewall, and

And forming a power supply circuit, wherein the power supply circuit is positioned on the bottom and is electrically separated from the metal wall layer.