TWI865025B - Pixel circuit operation method, gate drive circuit and information processing device - Google Patents

Abstract

The present invention mainly discloses a pixel circuit operation method, which is executed by a gate drive unit and includes the following steps: providing a gate control signal including an enable segment and a non-enable segment to a display data writing element in a pixel circuit within a frame display cycle, so that the enable segment of the gate control signal is within a data writing time interval; and providing a light regulation signal including an enable segment and a non-enable segment to a light regulation element in the pixel circuit within the frame display cycle, so that a part of the enable segment of the light regulation signal falls within the data writing time interval.

Description

Pixel circuit operation method, gate drive circuit and information processing device

The present invention relates to the technical field of OLED and Micro-LED displays, and in particular to a pixel circuit operation method for a gate drive circuit.

It is known that flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays, wherein liquid crystal displays are a type of non-self-luminous flat panel displays that have been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays that are currently in mainstream applications.

FIG1 is a block diagram of a known OLED display. As shown in FIG1 , the known OLED display 1a mainly includes: an OLED display panel 11a, a timing controller 120a, a source drive circuit (or display drive circuit) 121a, and a gate drive circuit 122a, wherein the OLED display panel 11a includes a plurality of pixel circuits 111a and a plurality of sub-pixels (i.e., OLED elements) 112a, and the source drive circuit 121a provides display data signals VDATA to each pixel circuit 111a through a plurality of source lines. On the other hand, the gate driving circuit 122a includes a plurality of gate driving units 12Ga, and each of the gate driving units 12Ga includes at least one shift register and an emission controller for respectively providing at least one scanning signal (or gate control signal) and an emission control signal to the pixel circuit 111a.

Electronic engineers familiar with the design of pixel circuits know that a pixel circuit 111a using a 6T1C, 7T1C, 7T2C, 8T1C, or 8T2C architecture must contain a driving element, a display data writing element, at least one storage capacitor, and at least one light-emitting control element. FIG2 is a diagram of a driving element M1a, a display data writing element M2a, a storage capacitor C1a, and a light-emitting control element M3a included in the pixel circuit 111a shown in FIG1. As shown in FIG2, the driving element M1a, the display data writing element M2a, and the light-emitting control element M3a can all be a TFT element or a MOSFET element, and all have a gate terminal, a first element electrical terminal, and a second element electrical terminal. To explain in more detail, the second element electrical terminal of the driving element M1a is coupled to the anode terminal of the OLED element 112a, and its gate terminal is coupled to the first terminal of the storage capacitor C1a. On the other hand, the gate terminal, the first element electrical terminal and the second element electrical terminal of the display data writing element M2a are respectively coupled to a gate control signal G<n>, a display data signal VDATA and the gate terminal of the driving element M1a. Furthermore, the gate terminal, the first element electrical terminal and the second element electrical terminal of the luminescence control element M3a are respectively coupled to a luminescence control signal EM<n>, a first driving voltage ELVDD and the first element electrical terminal of the driving element M1a.

FIG3 is a working timing diagram of the gate control signal and the light emission control signal shown in FIG2. As shown in FIG2 and FIG3, in a display data writing stage ( _tPROM ), the gate control signal G<n> is at a low level and the light emission control signal EM<n> is at a high level, so the light emission control element M3a is turned off and the display data writing element M2a is turned on, so that the data voltage of the display data signal VDATA is written into the storage capacitor C1a. Next, in a light emitting phase (t _EM ), the gate control signal G<n> is at a high level and the light emitting control signal EM<n> is at a low level, so the display data writing element M2a is turned off and the light emitting control element M3a and the driving element M1a are both turned on, so that the OLED element 112a is driven by voltage to emit light.

In practice, as shown in FIG2 , a parasitic capacitor Cpa is formed between a node A and a node B, wherein the node A and the node B are the gate terminal and the first element electrical terminal of the driving element M1a, respectively. Further, as shown in FIG2 and FIG3 , since the light-emitting control element M3a is off in the display data writing phase and on in the light-emitting phase, the node B is in a floating state in the display data writing phase, and the terminal voltage of the node B rises rapidly to ELVDD in the light-emitting phase. It is worth noting that, under normal circumstances, node A should be in a floating state at the end of the display data writing phase. However, due to the capacitance coupling of the parasitic capacitor Cpa, the terminal voltage of node A is increased at the end of the display data writing phase. This phenomenon is called feedthrough. As can be imagined, in the light-emitting phase (t _EM ), this feedthrough voltage will have a negative impact on the driving voltage applied to the OLED element 112a, causing the brightness of the light emitted by the OLED element 112a to be different from the predetermined brightness.

In summary, when the parasitic capacitor Cpa cannot be completely removed, it should be considered to change the working timing of the gate control signal G<n> and/or the luminance control signal EM<n> as shown in FIG. 3 to minimize or eliminate the negative impact of the feedback effect of the parasitic capacitor Cpa.

From the above description, it can be seen that a new pixel circuit operation method is urgently needed in the art.

The main purpose of the present invention is to provide a pixel circuit operation method, which is performed by a gate drive circuit, wherein the gate drive circuit is integrated in a display device, and the display device further includes a source drive circuit, a timing controller, and a display panel including a plurality of pixel circuits and a plurality of sub-pixels. When the pixel circuit operation method of the present invention is applied, the feedthrough effect caused by the parasitic capacitance contained in a driving element in the pixel circuit can be eliminated, so that each sub-pixel emits light uniformly.

To achieve the above-mentioned purpose, the present invention proposes a first embodiment of the pixel circuit operation method, which is executed by a gate drive unit and includes the following steps: Provide a gate control signal including an enable segment and a disable segment to a display data write element in a pixel circuit within a frame display cycle, so that the enable segment of the gate control signal is within a data write time interval; and Provide a light regulation signal including an enable segment and a disable segment to a light regulation element in the pixel circuit within the frame display cycle, so that a part of the enable segment of the light regulation signal falls within the data write time interval.

In a feasible embodiment, the pixel circuit is any one selected from the group consisting of an OLED pixel circuit, a Micro-LED pixel circuit and a QLED pixel circuit.

In another feasible embodiment, the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements.

Furthermore, the present invention also proposes a second embodiment of the pixel circuit operation method, which is executed by a gate drive unit and includes the following steps: Providing a gate control signal including an enable segment and a disable segment to a display data write element in a pixel circuit within a frame display cycle, so that the enable segment of the gate control signal is within a data write time interval; and Providing a light regulation signal including an enable segment and a disable segment to a light regulation element in the pixel circuit within the frame display cycle, so that the trailing edge of the disable segment of the light regulation signal falls on a starting time of the data write time interval.

In a feasible embodiment, the pixel circuit is any one selected from the group consisting of an OLED pixel circuit, a Micro-LED pixel circuit and a QLED pixel circuit.

In another feasible embodiment, the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements.

To achieve the above-mentioned purpose, the present invention also proposes a first embodiment of a gate drive circuit, which is integrated in a display device, wherein the display device also includes a source drive circuit, a timing controller, and a display panel including a plurality of pixel circuits and a plurality of sub-pixels; the characteristic is that the gate drive circuit executes a pixel circuit operation method to control each of the pixel circuits, and the pixel circuit operation method includes the following steps: Provide a gate control signal including an enable section and a non-enable section to a display data writing element in a pixel circuit within a frame display cycle, so that the enable section of the gate control signal is within a data writing time interval; and During the frame display cycle, a light-emitting control signal including an enabled segment and a disabled segment is provided to a light-emitting control element in the pixel circuit, so that a portion of the enabled segment of the light-emitting control signal falls within the data writing time interval.

In a feasible embodiment, the pixel circuit is any one selected from the group consisting of an OLED pixel circuit, a Micro-LED pixel circuit and a QLED pixel circuit.

In another feasible embodiment, the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements.

Furthermore, the present invention also proposes a second embodiment of the gate drive circuit, which is integrated into a display device, wherein the display device further includes a source drive circuit, a timing controller, and a display panel including a plurality of pixel circuits and a plurality of sub-pixels; the characteristic is that the gate drive circuit executes a pixel circuit operation method to control each of the pixel circuits, and the pixel circuit operation method includes the following steps: Provide a gate control signal including an enable section and a non-enable section to a display data writing element in a pixel circuit within a display cycle, so that the enable section of the gate control signal is within a data writing time interval; and During the frame display cycle, a light-emitting control signal including an enabled segment and a disabled segment is provided to a light-emitting control element in the pixel circuit, so that the trailing edge of the disabled segment of the light-emitting control signal falls on a starting time of the data writing time interval.

In a feasible embodiment, the pixel circuit is any one selected from the group consisting of an OLED pixel circuit, a Micro-LED pixel circuit and a QLED pixel circuit.

In another feasible embodiment, the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements.

Furthermore, the present invention also provides an embodiment of an information processing device, which is characterized in that it has a display device, and the display device includes the first embodiment or the second embodiment of the gate drive circuit of the present invention as described above.

In one embodiment, the information processing device is an electronic device selected from the group consisting of an OLED display device, a Micro-LED display device, a QLED display device, a smart TV, a smart phone, a smart watch, a tablet computer, a laptop computer, an all-in-one computer, an in-vehicle entertainment system, a head-mounted display device, a video portal, a multimedia information display device, and a digital camera.

In order to enable the Review Committee to further understand the structure, features, purpose, and advantages of the present invention, the following are attached with drawings and detailed descriptions of preferred specific embodiments.

FIG4 is a block diagram of a display device including a gate drive circuit of the present invention. As shown in FIG4 , the display device 1 includes: a display panel 11, a timing controller 120, a source drive circuit 121, and a gate drive circuit 122 of the present invention, wherein the display panel 11 includes a plurality of pixel circuits 111 and a plurality of sub-pixels 112. For example, the display panel 11 is an OLED display panel, which includes a plurality of OLED pixel circuits and a plurality of OLED elements. In other feasible embodiments, the display panel 11 may also be a Micro-LED display panel or a QLED display panel, in which case the pixel circuit 111 is correspondingly a Micro-LED pixel circuit or a QLED pixel circuit.

Electronic engineers familiar with the design of pixel circuits know that the pixel circuit 111 includes a plurality of semiconductor switch elements and at least one storage capacitor, wherein the semiconductor switch element can be a thin film transistor (TFT) element or a metal oxide semiconductor field effect transistor (MOSFET) element. For example, the structure of the pixel circuit 111 is 6T1C, 7T1C, 7T2C, 8T1C, or 8T2C. To explain in more detail, among the plurality of semiconductor switch elements, there is one semiconductor switch element as a driving element, there is one semiconductor switch element as a display data writing element coupled, and there is one semiconductor switch element as a light-emitting control element.

FIG5 is a diagram of a driving element M1, a display data writing element M2, a storage capacitor C1, and a light-emitting control element M3 included in the pixel circuit 111 shown in FIG4. As shown in FIG3, the driving element M1, the display data writing element M2, and the light-emitting control element M3 can all be a TFT element or a MOSFET element, and all have a gate terminal, a first element electrical terminal, and a second element electrical terminal. To explain in more detail, the second element electrical terminal of the driving element M1 is coupled to an electrical terminal of the sub-pixel 112, and its gate terminal is coupled to the first terminal of the storage capacitor C1. On the other hand, the gate terminal, the first device electrical terminal and the second device electrical terminal of the display data writing element M2 are respectively coupled to a gate control signal G<n>, a display data signal VDATA and the gate terminal of the driving element M1. In addition, the gate terminal, the first device electrical terminal and the second device electrical terminal of the luminescence control element M3 are respectively coupled to a luminescence control signal EM<n>, a first driving voltage ELVDD and the first device electrical terminal of the driving element M1.

As shown in FIG4 , the source driver circuit 121 (also called display driver circuit) provides the display data signal VDATA to each pixel circuit 111 through a plurality of source lines. On the other hand, the gate driver circuit 122 includes a plurality of gate driver units 12G, and each gate driver unit 12G includes at least one shift register and an emission controller, which are used to provide at least one gate control signal G<n> (or scan signal) and an emission control signal EM<n> to each pixel circuit 111.

FIG6 is a first operation timing diagram of the plurality of signals shown in FIG5. In particular, the present invention provides a first embodiment of a pixel circuit operation method for the gate driver circuit 122 to execute, so that the gate driver unit 12G provides a gate control signal G<n> and a light-emitting control signal EM<n> with a specified operation timing to the corresponding pixel circuit 111. FIG7 is a first flow chart of a pixel circuit operation method of the present invention. As shown in FIG. 5, FIG. 6 and FIG. 7, the method flow first executes step S1: providing a gate control signal G<n> including an enable section and a disable section to a display data writing element M2 in a pixel circuit 111 within a frame display cycle, so that the enable section of the gate control signal G<n> is within a data writing time period. Then, the method flow executes step S2: providing a light-emitting control signal EM<n> including an enable section and a non-enable section to a light-emitting control element M3 in the pixel circuit 111 during the frame display cycle, so that a part of the enable section of the light-emitting control signal EM<n> falls within the data writing time interval. Inside.

As shown in FIG. 5 and FIG. 6 , a parasitic capacitor Cp is formed between a node A and a node B, wherein the node A and the node B are the gate terminal and the first device electrical terminal of the driving device M1, respectively. In the example, the gate control signal G<n> is at a low level in the enable section, so the display data writing element M2 is turned on, so that the data voltage of the display data signal VDATA is written into the storage capacitor C1. It is worth noting that the non-enable section and the enable section of the luminous modulation signal EM<n> are respectively at a high level and a low level, and half of the non-enable section and half of the enable section are within the data writing time period. Therefore, during the data writing time period In the FET, node B is initially in a floating state and quickly rises to ELVDD when the luminance control signal EM<n> switches from the non-enabled section to the enabled section. On the other hand, due to the capacitance coupling of the parasitic capacitor Cp, the terminal voltage of node A is increased when node B rises to ELVDD. This phenomenon is called feedthrough. Then, during the data writing time period, In this case, the terminal voltage of node A (i.e., the terminal voltage of storage capacitor C1) is still charged by the data voltage, thereby restoring the original potential. In this way, during a light-emitting time interval of a frame display cycle, Afterwards, there is no voltage at the node A that will have a negative impact on the driving voltage of the sub-pixel 112, thereby ensuring uniform light emission of each of the sub-pixels 112.

FIG8 is a diagram of the four pixel circuits 111 and the four sub-pixels 112 in FIG4, and FIG9 is a first light-emitting diagram of the four sub-pixels. As shown in FIG5, FIG8 and FIG9, under the influence of the feedthrough effect of the parasitic capacitance Cp, the four sub-pixels 112 driven by the four pixel circuits 111 respectively exhibit different light-emitting brightness, that is, the light-emitting brightness is uneven. In contrast, FIG10 is a second light-emitting diagram of the four sub-pixels. As shown in FIG4, FIG5, FIG8 and FIG10, when the gate drive circuit 122 uses the pixel circuit operation method of the present invention, the feedthrough effect (feedthrough) caused by the parasitic capacitance Cp contained in a driving element M1 in each of the pixel circuits 111 can be eliminated, so that each of the sub-pixels 112 emits light uniformly.

In particular, the present invention also proposes a second embodiment of a pixel circuit operation method. Figure 11 is a second flow chart of a pixel circuit operation method of the present invention, and Figure 12 is a second operation timing diagram of multiple signals shown in Figure 5. As shown in Figures 5, 11 and 12, the method flow of the second embodiment first executes step S1a: providing a gate control signal G＜n＞ including an enable segment and a non-enable segment to a display data writing element M2 in a pixel circuit 111 within a frame display cycle, so that the enable segment of the gate control signal G＜n＞ is within a data writing time period. Then, the method flow executes step S2a: providing a light modulation signal EM<n> including an enable segment and a disable segment to a light modulation element M3 in the pixel circuit 111 during the frame display cycle, so that the trailing edge of the disable segment of the light modulation signal EM<n> falls within the data writing time interval. above the starting time.

As shown in FIG5 and FIG12, a data writing time interval in a frame display cycle In the second embodiment of the pixel circuit operation method of the present invention, the non-enable segment and the enable segment of the luminous modulation signal EM<n> are respectively high and low, and the trailing edge of the non-enable segment is set to fall within the data writing time interval. , thus ensuring that the enable section is within the data write time range. According to this design, when entering the data writing time zone Previously, the B node was in a floating state in the non-enabled section (i.e., high level) of the luminous control signal EM<n>, and quickly rose to ELVDD when the luminous control signal EM<n> switched from the non-enabled section to the enabled section. That is, the B node entered the data writing time period. The starting point is quickly raised to ELVDD.

Affected by the capacitance coupling of the parasitic capacitor Cp, the terminal voltage of node A is increased when the voltage of node B rises to ELVDD. This phenomenon is called feedthrough. Then, during the data writing time period In this case, the terminal voltage of node A (i.e., the terminal voltage of storage capacitor C1) is still charged by the data voltage, thereby restoring the original potential. In this way, during a light-emitting time interval of a frame display cycle, Afterwards, there is no voltage at the node A that will have a negative impact on the driving voltage of the sub-pixel 112, thereby ensuring uniform light emission of each of the sub-pixels 112.

Thus, the above description has completely and clearly explained a pixel circuit operation method of the present invention; and, from the above description, it can be known that the present invention has the following advantages:

(1) The present invention discloses a pixel circuit operation method, which is performed by a gate drive circuit, wherein the gate drive circuit is integrated into a display device, and the display device further includes a source drive circuit, a timing controller, and a display panel including a plurality of pixel circuits and a plurality of sub-pixels. When the pixel circuit operation method of the present invention is applied, the feedthrough effect caused by the parasitic capacitance contained in a driver element in the pixel circuit can be eliminated, so that each of the sub-pixels emits light uniformly.

(2) The present invention also discloses a gate driving circuit integrated in a display device, wherein the gate driving circuit executes the pixel circuit operation method of the present invention as described above, so that each gate driving unit provides a gate control signal and a light regulation signal with a specified working timing to its corresponding pixel circuit, thereby eliminating the adverse effects derived from the feedthrough effect.

(3) The present invention further discloses an information processing device, characterized in that it has a display device, and the display device includes the gate drive circuit of the present invention as described above. The information processing device is an electronic device selected from the group consisting of an OLED display device, a Micro-LED display device, a QLED display device, a smart TV, a smart phone, a smart watch, a tablet computer, a notebook computer, an all-in-one computer, an in-vehicle entertainment system, a head-mounted display device, a video door machine, a multimedia information display device, and a digital camera.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are very different from the known technology, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely request the review committee to examine this carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

1a:OLED display

11a:OLED display panel

111a: Pixel circuit

112a: OLED element

120a: Timing controller

121a: Source drive circuit

122a: Gate drive circuit

12Ga: Gate drive unit

M1a: Drive element

M2a: Display data writing device

M3a: Light-emitting control element

C1a: Storage capacitor

1: Display device

11: Display Panel

111: Pixel circuit

112: Sub-pixel

120: Timing controller

121: Source drive circuit

122: Gate drive circuit

12G: Gate drive unit

M1: driving element

M2: Display data writing device

M3: Light-emitting control element

C1: Storage capacitor

S1: providing a gate control signal including an enable section and a non-enable section to a display data writing element in a pixel circuit within a frame display cycle, so that the enable section of the gate control signal is within a data writing time period

S2: providing a light-emitting control signal including an enable section and a non-enable section to a light-emitting control element in the pixel circuit during the frame display cycle, so that a portion of the enable section of the light-emitting control signal falls within the data writing time interval

S1a: providing a gate control signal including an enable section and a non-enable section to a display data writing element in a pixel circuit within a frame display cycle, so that the enable section of the gate control signal is within a data writing time period

S2a: providing a light-emitting control signal including an enable segment and a non-enable segment to a light-emitting control element in the pixel circuit during the frame display cycle, so that the trailing edge of the non-enable segment of the light-emitting control signal falls on a starting time of the data writing time interval

FIG1 is a block diagram of a known OLED display; FIG2 is a diagram of a driving element, a display data writing element, a storage capacitor, and a light-emitting control element included in the pixel circuit shown in FIG1; FIG3 is a working timing diagram of the gate control signal and the light-emitting control signal shown in FIG2; FIG4 is a block diagram of a display device including a gate driving circuit of the present invention; FIG5 is a diagram of a driving element, a display data writing element, a storage capacitor, and a light-emitting control element included in the pixel circuit shown in FIG4; FIG6 is a first working timing diagram of multiple signals shown in FIG5; FIG7 is a first flow chart of a pixel circuit operation method of the present invention; FIG8 is a diagram of four pixel circuits and four sub-pixels in FIG4; FIG. 9 is a first light-emitting diagram of four sub-pixels; FIG. 10 is a second light-emitting diagram of four sub-pixels; FIG. 11 is a second flow chart of a pixel circuit operation method of the present invention; and FIG. 12 is a second operation timing diagram of multiple signals shown in FIG. 5.

S1: Provide a gate control signal including an enable segment and a non-enable segment to a display data writing element in a pixel circuit within a frame display cycle, so that the enable segment of the gate control signal is within a data writing time interval

S2: Provide a light-emitting control signal including an enabled segment and a disabled segment to a light-emitting control element in the pixel circuit during the frame display cycle, so that a portion of the enabled segment of the light-emitting control signal falls within the data writing time interval

Claims (14)

A pixel circuit operation method is performed by a gate drive unit and includes the following steps: providing a gate control signal including a first enable segment and a first non-enable segment to a display data write element in a pixel circuit within a frame display cycle, wherein the first enable segment of the gate control signal determines a data write time interval; and providing a light regulation signal including a second enable segment and a second non-enable segment to a light regulation element in the pixel circuit within the frame display cycle, so that a part of the second enable segment of the light regulation signal falls within the data write time interval; wherein the first non-enable segment and the first enable segment are respectively a high level and a low level, and the second non-enable segment and the second enable segment are respectively a high level and a low level. The first and second segments are high and low respectively; in the data writing time interval, the gate control signal is in the first enabling segment to turn on the display data writing element, so that the data voltage of a display data signal is written into a storage capacitor and presented on a first node; and the second non-enabling segment of the light-emitting control signal starts before the data writing time interval and ends in the data writing time interval, so as to make a second node coupled to the output end of the light-emitting control element in a floating state, and the light-emitting control signal enters the second enabling segment after the second non-enabling segment ends to make the second node quickly rise to a DC voltage, wherein a parasitic capacitance generated by a driving element exists between the second node and the first node. A pixel circuit operation method as described in claim 1, wherein the pixel circuit is selected from any one of the groups consisting of an OLED pixel circuit, a Micro-LED pixel circuit, and a QLED pixel circuit. A pixel circuit operation method as described in claim 1, wherein the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements. A pixel circuit operation method is performed by a gate drive unit and includes the following steps: providing a gate control signal including a first enable segment and a first non-enable segment to a display data write element in a pixel circuit within a frame display cycle, wherein the first enable segment of the gate control signal determines a data write time interval; and providing a light regulation signal including a second enable segment and a second non-enable segment to a light regulation element in the pixel circuit within the frame display cycle, wherein the trailing edge of the second non-enable segment of the light regulation signal falls on a starting time of the data write time interval; wherein the first non-enable segment and the first enable segment are respectively a high level and a low level, and the second non-enable segment and the second non-enable segment are respectively a high level and a low level. The enable section is respectively a high level and a low level; in the data writing time interval, the gate control signal is in the first enable section to turn on the display data writing element, so that the data voltage of a display data signal is written into a storage capacitor and presented on a first node; and the second non-enable section of the light-emitting control signal starts before the data writing time interval and ends in the data writing time interval, so as to make a second node coupled to the output end of the light-emitting control element in a floating state, and the light-emitting control signal enters the second enable section after the second non-enable section ends to make the second node quickly rise to a DC voltage, wherein a parasitic capacitance generated by a driving element exists between the second node and the first node. A pixel circuit operation method as described in claim 4, wherein the pixel circuit is selected from any one of the groups consisting of an OLED pixel circuit, a Micro-LED pixel circuit, and a QLED pixel circuit. A pixel circuit operation method as described in claim 4, wherein the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements. A gate drive circuit is integrated in a display device, wherein the display device further includes a source drive circuit, a timing controller, and a display panel including a plurality of pixel circuits and a plurality of sub-pixels; the gate drive circuit executes a pixel circuit operation method to control each of the pixel circuits, and the pixel circuit operation method includes the following steps: providing a first enabling section and a first enabling section in a display cycle; A gate control signal of a non-enable segment is provided to a display data writing element in the pixel circuit, wherein the first enable segment of the gate control signal determines a data writing time interval; and a light regulation signal including a second enable segment and a second non-enable segment is provided to a light regulation element in the pixel circuit during the frame display cycle, so that a portion of the second enable segment of the light regulation signal falls within the data writing time interval. ; wherein the first non-enable section and the first enable section are respectively at a high level and a low level, and the second non-enable section and the second enable section are respectively at a high level and a low level; during the data writing time period, the gate control signal is in the first enable section and turns on the display data writing element, so that a data voltage of a display data signal is written into a storage capacitor and presented on a first node; and the second non-enable section of the luminescence modulation signal is The enable section starts before the data writing time section and ends in the data writing time section, so as to make a second node coupled to the output end of the light-emitting control element in a floating state, and the light-emitting control signal enters the second enable section after the second non-enable section ends to make the second node quickly rise to a DC voltage, wherein a parasitic capacitance generated by a driving element exists between the second node and the first node. The gate drive circuit as described in claim 7, wherein the pixel circuit is selected from any one of the group consisting of an OLED pixel circuit, a Micro-LED pixel circuit, and a QLED pixel circuit. A gate drive circuit as described in claim 7, wherein the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements. A gate drive circuit is integrated in a display device, wherein the display device further includes a source drive circuit, a timing controller, and a display panel including a plurality of pixel circuits and a plurality of sub-pixels; the gate drive circuit executes a pixel circuit operation method to control each of the pixel circuits, and the pixel circuit operation method includes the following steps: providing a first enabling section and a first non-enabling section in a display cycle; The invention relates to a method for controlling the pixel circuit to write a display data to a display data writing element in the pixel circuit, wherein the first enabling segment of the gate control signal determines a data writing time interval; and providing a light regulation signal including a second enabling segment and a second non-enabling segment to a light regulation element in the pixel circuit during the frame display cycle, so that the trailing edge of the second non-enabling segment of the light regulation signal falls at a starting time of the data writing time interval. wherein the first non-enable section and the first enable section are respectively high and low, and the second non-enable section and the second enable section are respectively high and low; During the data writing time interval, the gate control signal is in the first enable section and turns on the display data writing element, so that the data voltage of a display data signal is written into a storage capacitor and presented on a first node; and the first The second non-enable section starts before the data writing time period and ends in the data writing time period, so as to make a second node coupled to the output end of the light-emitting control element in a floating state, and the light-emitting control signal enters the second enable section after the second non-enable section ends to make the second node quickly rise to a DC voltage, wherein a parasitic capacitance generated by a driving element exists between the second node and the first node. The gate drive circuit as described in claim 10, wherein the pixel circuit is selected from any one of the group consisting of an OLED pixel circuit, a Micro-LED pixel circuit, and a QLED pixel circuit. A gate drive circuit as described in claim 10, wherein the pixel circuit includes a plurality of semiconductor switch elements and at least one storage capacitor, and the semiconductor switch element is any one selected from the group consisting of TFT elements and MOSFET elements. An information processing device, characterized in that it has a display device, and the display device includes a gate drive circuit as described in any one of claim 7 to claim 9. An information processing device, characterized in that it has a display device, and the display device includes a gate drive circuit as described in any one of claim 10 to claim 12.