TWI875006B - Electronic device - Google Patents

Abstract

The present application provides an electronic device. The electronic device includes a plurality of pixel units arranged in an array. A first pixel unit of the pixel units includes an input circuit, a switch circuit, first and second capacitors, a driving circuit, and a load circuit. The input circuit is controlled by a second scan signal and has an input terminal receiving a data signal and an output terminal coupled to a first node. The switch circuit is coupled between a first power terminal and the first node and controlled by a driving enable signal. The first capacitor is coupled between the first node and a second power terminal. The second capacitor is coupled between the first node and a second node. The driving circuit has an input terminal coupled to a third power terminal, an output terminal coupled to a third node, and a control terminal coupled to the second node. The load circuit is coupled between the third node and a fourth power terminal.

Description

Electronic devices

The present disclosure relates to an electronic device, and in particular to an electronic device for eliminating or reducing the dark-state light leakage phenomenon of a light-emitting device.

Generally speaking, when zero grayscale or low grayscale data is written into a display device, a completely black or nearly black screen should be displayed on the panel of the display device. However, in the current circuit design of display devices, when zero grayscale or low grayscale data is written into the display device, the light-emitting diodes of the display panel or the light-emitting diodes of the backlight module may emit light due to unexpected surges, causing dark-state light leakage in the display device. The dark-state light leakage affects the display device's inability to display clear and correct images, and also reduces the user experience.

The present disclosure provides an electronic device, which includes a plurality of pixel units. The pixel units are configured into a pixel array. A first pixel unit among the plurality of pixel units receives a data signal, a first scan signal, a second scan signal, and a drive enable signal, and includes an input circuit, a first switch circuit, a first capacitor, a second capacitor, a drive circuit, and a load circuit. The input circuit is controlled by the second scan signal and has an input terminal for receiving the data signal and an output terminal coupled to a first node. The first switch circuit is coupled between a first power supply terminal and a first node and is controlled by the drive enable signal. The first capacitor is coupled between the first node and a second power supply terminal. The second capacitor is coupled between the first node and a second node. The driving circuit has an input terminal coupled to a third power terminal, an output terminal coupled to a third node, and a control terminal coupled to the second node. The load circuit is coupled between the third node and a fourth power terminal.

1: Light-emitting module

4,6: Display device

5,7: Electronic devices

10: Pixel array

11: Scan the drive

12: Data drive

13: Control the drive

20: Input circuit

20A: Input terminal

20B: Output terminal

21: Switching circuit

22,23: Reset circuit

24: Driving circuit

24A: Input terminal

24B: Output terminal

24C: Control terminal

25: Compensation circuit

26: Switching circuit

27: Load circuit

30: Reset phase

31: Compensation stage

32: Driving stage

40: LCD panel

41: Controller

42: Backlight module

50: Input unit

60:LED display panel

61: Controller

70: Input unit

200,210,220,230,240,250,260~PMOS transistors

270,271: LED

ARVDD,ARVSS: DC voltage

Cdc, Cst: capacitor

D1~Dn: data signal

DL1~DLn: data line

EM1~EMm: drive enable signal

GND: Ground

I20: Driving current

L1~Lm: control line

LH: High voltage level

LL: Low voltage level

N20~N23: Node

P(1,1)~P(m,n): pixel unit

P30, P31: Surge

S0~Sm: scanning signal

SL0~SLm: Scanning line

T20~T24: Power supply terminal

T30~T35: Time point

V23, Vref, Vrst: DC voltage

V20, V21, V22: voltage

Figure 1 shows a light-emitting module according to an embodiment of the present disclosure.

Figure 2 shows the circuit structure of a pixel unit according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of the main signals/voltages of the pixel unit P in FIG. 2 according to an embodiment of the present disclosure.

FIG. 4 shows a display device using the light-emitting module of FIG. 1 according to an embodiment of the present disclosure.

FIG. 5 shows an electronic device using the display device of FIG. 4 according to an embodiment of the present disclosure.

FIG. 6 shows a display device using the light-emitting module of FIG. 1 according to another embodiment of the present disclosure.

FIG. 7 shows an electronic device using the display device of FIG. 6 according to another embodiment of the present disclosure.

In order to make the purpose, features and advantages of the present disclosure more clear and easy to understand, the following examples are specifically cited and detailed descriptions are made in conjunction with the attached drawings. This disclosure specification provides different examples to illustrate the technical features of different implementations of the present disclosure. Among them, the configuration of each component in the embodiment is for illustrative purposes and is not used to limit the present disclosure. The ordinal numbers in the specification and the scope of the patent application, such as "first", "second", etc., do not have a sequential relationship, and are only used to mark and distinguish two different components with the same name. Therefore, the first element referred to in the specification can be called the second element in the scope of the patent application. In addition, the partial repetition of the figure numbers in the embodiments is for the purpose of simplifying the description and does not mean the correlation between different embodiments.

The present disclosure may be understood by reference to the following detailed description in conjunction with the accompanying drawings, and it should be noted that, for simplicity, only a portion of an electronic device may be illustrated in the accompanying drawings. In addition, the number and size of each component in the accompanying drawings are for illustration only and are not intended to limit the present disclosure. It should be understood that components or devices may exist in various forms. In this specification, relative terms such as "above" and "below" may be used to describe the positional relationship of one component of the diagram relative to another component. It should be understood that if the device of the diagram is flipped so that it is upside down, the component "above" will become the component "below". It must be understood that when an element or layer is referred to as being "electrically connected" to another element or layer, it may be directly electrically connected or connected to other elements or layers, or have other elements or layers interposed therebetween. Conversely, if a component or layer is "connected" to other components or layers, there will be no other components or layers in between.

In this specification, words such as "include" and/or "have" are open-ended words, and therefore should be interpreted as "including but not limited to...". Therefore, when the terms "include" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components. In addition, there may be a certain error between any two values or directions used for comparison.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in some embodiments of the present disclosure.

FIG. 1 shows a light-emitting module according to an embodiment of the present disclosure. Referring to FIG. 1, the light-emitting module 1 includes a pixel array 10, a scan driver 11, a data driver 12, and a control driver 13. The scan driver 11 is coupled to a plurality of scan lines SL0~SLm, and provides scan signals S0~Sm to the scan lines SL0~SLm respectively. The scan signals S0~Sm are enabled sequentially, and the duration of each scan signal S0~Sm being enabled is the same but does not overlap with each other. The data driver 12 is coupled to a plurality of data lines DL1~DLn, and provides data signals D1~Dn to the data lines DL1~DLn respectively. As shown in FIG. 1, data lines DL1-DLn and scan lines SL0-SLm are interlaced. The control driver 13 is coupled to a plurality of control lines L1-Lm, and provides drive enable signals EM1-EMm to the control lines L1-Lm respectively. The drive enable signals EM1-EMm are enabled sequentially. In this embodiment, m is a positive integer greater than or equal to 1. n is a positive integer greater than or equal to 1. Therefore, according to the definition of m and n, the light-emitting module 1 includes at least 2 scan lines SL0-SL1 (m=1), one data line D1 (n=1), and one control line L1 (m=1).

The pixel array 10 includes a plurality of pixel units P(1,1)~P(m,n), and these pixel units P(1,1)~P(m,n) are arranged into m pixel rows (horizontally) and n pixel lines (vertically). The m pixel rows correspond to m scan lines SL1~SLm, and also correspond to m control lines L1~Lm. The n pixel rows correspond to n data lines DL1~DLn. Each pixel unit P(x,y) is coupled to the scan line SLx corresponding to the pixel row and the previous scan line SLx-1, a data line DLy, and a control line Lx to receive two scan signals Sx and Sx, a data signal Dy, and a drive enable signal EM, wherein x is any integer from 1 to m, and y is any integer from 1 to n.

For example, when x=1 and y=1, the pixel unit P(1,1) is coupled to the scanning line SL1(x=1) corresponding to the first pixel row and the previous scanning line SL0(x=1, x-1=0), the data line DL1(y=1), and the control line L1(x=1) to receive the scanning signals S1 and S0, the data signal D1, and the drive enable signal EM1; when x=2 and y=1, the pixel unit P(2,1) is coupled to the scanning line SL2 corresponding to the second pixel row and the previous scanning line SL1, the data line DL1, and the control line L2 to receive the scanning signals S2 and S1, the data signal D1, and drive enable signal EM2; when x=1 and y=2, the pixel unit P(1,2) couples the scan line SL1 corresponding to the first pixel row and the previous scan line SL0, the data line DL2, and the control line L1 to receive scan signals S1 and S0, data signal D2, and drive enable signal EM1; when x=2 and y=2, the pixel unit P(2,2) couples the scan line SL2 corresponding to the second pixel row and the previous scan line SL1, the data line DL2, and the control line L2 to receive scan signals S2 and S1, data signal D2, and drive enable signal EM2.

Referring to Figure 1, all pixel units arranged in the same pixel row (vertical direction) are coupled to the same data line, and all pixel units arranged in the same pixel column (horizontal direction) are coupled to the same two adjacent scanning lines and the same control line. For example, the pixel units P(1,1)~P(m,1) arranged in the first pixel row are coupled to the same data line DL1 to receive the data signal D1; and the pixel units P(1,1)~P(1,n) arranged in the first pixel column are coupled to the same two adjacent scanning lines SL0 and SL1 to receive the scanning signals S0 and S1, and are further coupled to the same control line L1.

FIG. 2 shows a circuit structure of a pixel unit according to an embodiment of the present disclosure. All pixel units P(1,1)-P(m,n) of the pixel array 10 have the same structure, and for the sake of clarity, FIG. 2 only shows pixel unit P(1,1), i.e., x=1 and y=1. As described above, pixel unit P(1,1) is coupled to adjacent scan lines SL0 and SL1, data line DL1, and control line L1 to receive scan signals S0 and S1, data signal D1, and drive enable signal EM1. Referring to Figure 2, the pixel unit (1,1) includes an input circuit 20, a switch circuit 21, reset circuits 22 and 23, a drive circuit 24, a compensation circuit 25, a switch circuit 26, a load circuit 27, and capacitors Cst and Cdc.

Referring to FIG. 2 , the input circuit 20 has an input terminal 20A and an output terminal 20B. The input terminal 20A is coupled to the data line DL1 to receive the data signal D1. The output terminal 20B is coupled to the node N20. The input circuit 20 is further coupled to the scan line SL1 and is controlled by the scan signal S1 to determine whether to transmit the data signal D1 to the node N20. In one embodiment, the input circuit 20 includes a P-type metal oxide semiconductor (PMOS) transistor 200. The PMOS transistor 200 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 200 is coupled to the input terminal 20A of the input circuit 20, and is coupled to the data line DL1 through the input terminal 20A. The drain of the PMOS transistor 200 is coupled to the output terminal 20B of the input circuit 20, and is coupled to the node N20 through the output terminal 20B. The gate of the PMOS transistor 200 is coupled to the scanning line SL1 to receive the scanning signal S1. The PMOS transistor 200 determines its on/off state according to the scanning signal S1.

The switch circuit 21 is coupled between the power terminal T20 and the node N20. The switch circuit 21 is further coupled to the control line L1 and is controlled by the drive enable signal EM1 to determine the on/off state of the switch circuit 21. In one embodiment, the switch circuit 21 includes a PMOS transistor 210. The PMOS transistor 210 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 210 is coupled to the power terminal T20. When the light-emitting module 1 is operating, the power terminal T20 receives the DC voltage Vref. The drain of the PMOS transistor 210 is coupled to the node N20. The gate of the PMOS transistor 210 is coupled to the control line L1 to receive the drive enable signal EM1. The PMOS transistor 210 determines its on/off state according to the drive enable signal EM1.

The first electrode plate of the capacitor (also called reset capacitor) Cst is coupled to the node N20, and the second electrode plate thereof is coupled to the node N21. The first electrode plate of the capacitor Cdc is coupled to the node N20, and the second electrode plate thereof is coupled to the power terminal T23. When the light-emitting module 1 is operating, the power terminal T23 receives the DC voltage V23. In this embodiment, the DC voltage V23 can be a positive voltage or a negative voltage. There is a specific proportional relationship between the capacitance value of the capacitor Cdc and the capacitance value of the capacitor Cst. According to one embodiment, the ratio between the capacitance value of the capacitor Cdc and the capacitance value of the capacitor Cst is in the range of 0.39 to 1.26 (0.39<Cdc/Cst<1.26).

The reset circuit 22 is coupled between the power terminal T20 and the node N20. The reset circuit 22 is further coupled to the scan line SL0 and is controlled by the scan signal S0 to determine whether to perform a reset operation. In one embodiment, the reset circuit 22 includes a PMOS transistor 220. The PMOS transistor 220 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 220 is coupled to the power terminal T20. The drain of the PMOS transistor 220 is coupled to the node N20. The gate of the PMOS transistor 220 is coupled to the scan line SL0 to receive the scan signal S0. The PMOS transistor 220 determines its on/off state according to the scanning signal S0. When the PMOS transistor 220 is in the on state according to the scanning signal S0, the reset circuit 22 performs a reset operation; when the PMOS transistor 220 is in the off state according to the scanning signal S0, the reset circuit 22 does not perform a reset operation.

The reset circuit 23 is coupled between the power terminal T21 and the node N21. The reset circuit 23 is further coupled to the scanning line SL0 and is controlled by the scanning signal S0 to determine whether to perform a reset operation. In one embodiment, the reset circuit 23 includes a PMOS transistor 230. The PMOS transistor 230 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 230 is coupled to the power terminal T21. When the light-emitting module 1 is operating, the power terminal T21 receives a DC voltage Vrst. The drain of the PMOS transistor 230 is coupled to the node N21. The gate of the PMOS transistor 230 is coupled to the scanning line SL0 to receive the scanning signal S0. The PMOS transistor 230 determines its on/off state according to the scanning signal S0. When the PMOS transistor 230 is in the on state according to the scanning signal S0, the reset circuit 23 performs a reset operation; when the PMOS transistor 230 is in the off state according to the scanning signal S0, the reset circuit 23 does not perform a reset operation.

The driving circuit 24 has an input terminal 24A, an output terminal 24B, and a control terminal 24C. The input terminal 24A is coupled to the power terminal T22, the output terminal 24B is coupled to the node N22, and the control terminal 24C is coupled between the nodes N21. The driving circuit 24 determines its on/off state according to the driving voltage V21 on the node N21. In one embodiment, the driving circuit 24 includes a PMOS transistor 240. The PMOS transistor 240 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 240 is coupled to the input terminal 24A of the driving circuit 24, and is coupled to the power terminal T22 through the input terminal 24A. When the light-emitting module 1 is operating, the power terminal T22 receives the DC voltage ARVDD. The drain of the PMOS transistor 240 is coupled to the output terminal 24B of the driving circuit 24, and is coupled to the node N22 through the output terminal 24B. The gate of the PMOS transistor 240 is coupled to the control terminal 24C of the driving circuit 24, and is coupled to the node N21 through the control terminal 24C. The PMOS transistor 240 determines its on/off state according to the driving voltage V21 on the node N21.

The compensation circuit 25 is coupled between the node N21 and the node N22. The compensation circuit 25 is further coupled to the scan line SL1 and is controlled by the scan signal S1 to determine whether the compensation circuit 25 performs a compensation operation on the critical voltage (Vth) of the PMOS transistor 250. In one embodiment, the compensation circuit 25 includes a PMOS transistor 250. The PMOS transistor 250 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 250 is coupled to the node N22. The drain of the PMOS transistor 250 is coupled to the node N21. The gate of the PMOS transistor 250 is coupled to the scanning line SL1 to receive the scanning signal S1. The PMOS transistor 250 determines its on/off state according to the scanning signal S1. When the PMOS transistor 250 is in the on state according to the scanning signal S1, the compensation circuit 25 performs a compensation operation; when the PMOS transistor 250 is in the off state according to the scanning signal S1, the compensation circuit 25 does not perform a compensation operation.

The switch circuit 26 is coupled between the node N22 and the node N23. The switch circuit 26 is further coupled to the control line L1 and is controlled by the drive enable signal EM1 to determine the on/off state of the switch circuit 26. In one embodiment, the switch circuit 26 includes a PMOS transistor 260. The PMOS transistor 260 includes three electrodes, namely a gate (control electrode), a source (first electrode), and a drain (second electrode). The source of the PMOS transistor 260 is coupled to the node N22. The drain of the PMOS transistor 260 is coupled to the node N23. The gate of the PMOS transistor 260 is coupled to the control line L1 to receive the drive enable signal EM1. The PMOS transistor 260 determines its on/off state according to the driving enable signal EM1.

Referring to FIG. 2 , the load circuit 27 is coupled between the node N23 and a power terminal T24. When the light-emitting module 1 is in operation, the power terminal T24 receives the DC voltage ARVSS. In one embodiment, the DC voltage ARVSS can be a voltage lower than the DC voltage ARVDD, a ground (GND) voltage, or a 0 volt voltage. In the disclosed embodiment, the load circuit 27 includes at least one load element. In the embodiment of FIG. 2 , the load circuit 27 includes two load elements connected in series between the node N23 and the power terminal T24. In this embodiment, the two load elements are implemented by light-emitting diodes 270 and 271. As shown in FIG. 2, the anode end of the light emitting diode 270 is coupled to the node N23, the anode end of the light emitting diode 271 is coupled to the cathode end of the light emitting diode 270, and the cathode end of the light emitting diode 271 is coupled to the power terminal T24. In one embodiment, the light emitting diodes 270 and 271 may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot light emitting diode (quantum dot, QD, which may be, for example, QLED, QDLED), but are not limited thereto.

FIG. 3 is a schematic diagram showing the main signals/voltages of the pixel unit P(1,1) according to an embodiment of the present disclosure. The operation of the pixel unit P(1,1) will be described below with reference to FIG. 2 and FIG. 3.

When the light-emitting module 1 is operated, the pixel unit P(1,1) can operate in a plurality of scanning cycles. Each scanning cycle may include three operation phases: a reset phase 30, a compensation phase 31, and a drive phase 32. During each scanning cycle, the scanning signals S0 and S1 initially have a high voltage level LH (i.e., the scanning signals S0 and S1 are initially in a disabled state) to turn off the PMOS transistors 200, 220, 230, and 250, and the drive enable signal EM1 initially has a low voltage level LL (i.e., the drive enable signal EM1 is initially in an enabled state) to turn on the PMOS transistors 210 and 260. At this time, the LEDs 170 and 171 are driven by the driving current I20 generated during the previous scanning cycle.

During each scanning cycle, when the light-emitting diodes 170 and 171 are about to be re-driven, at time point T30, the drive enable signal EM1 is switched from the low voltage level LL to the high voltage level LH (i.e., the drive enable signal EM1 is switched from the enabled state to the disabled state). At this time, PMOS transistors 210 and 260. PMOS transistors 200, 220, 230, and 250 remain in the off state.

At time point T31 after time point T30, the scanning signal S0 switches from the high voltage level LH to the low voltage level LL (i.e., the scanning signal S0 switches from the disabled state to the enabled state) to turn on the PMOS transistors 220 and 230. During the period from time point T31 to T32, the scanning signal S0 remains at the low voltage level LL, i.e., the PMOS transistors 220 and 230 remain in the on state. Since the PMOS transistor 220 is turned on, the voltage V20 on the node N20 is equal to the DC voltage Vref; since the PMOS transistor 230 is turned on, the voltage V21 on the node N21 is equal to the DC voltage Vrst. Therefore, capacitor Cst stores the difference voltage between DC voltage Vref and Vrst. Through this operation, capacitor Cst can be reset to store a known voltage, so that pixel unit P(1,1) is not affected by the data signal D1 during the previous scanning cycle. According to the above, the period from time point T31 to T32 corresponds to the reset phase 30 of pixel unit P(1,1).

At time point T32, the scanning signal S0 switches from the low voltage level LL to the high voltage level LH (i.e., the scanning signal S0 switches from the enabled state to the disabled state) to turn off the PMOS transistors 220 and 230.

At time point T33 following time point T32, the scanning signal S1 switches from the high voltage level LH to the low voltage level LL (i.e., the scanning signal S1 switches from the disabled state to the enabled state) to turn on the PMOS transistors 200 and 250. During the period from time point T33 to T34, the scanning signal S1 remains at the low voltage level LL, i.e., the PMOS transistors 200 and 250 remain in the on state. Since the PMOS transistor 200 is turned on, the data signal D1 on the data line DL1 is transmitted to the node N20. The voltage V20 on the node N20 is equal to the voltage (Vdata) of the data signal D1. At this time, since the PMOS transistor 250 is in the on state and the PMOS transistor 260 is in the off state, the current generated by the PMOS transistor 240 flows from its drain through the on PMOS transistor 250 to its gate. The voltage V21 on the node N21 changes with this current until it reaches the voltage (ARVDD-Vth) and causes the PMOS transistor 240 to enter the cut-off region, where Vth is the critical voltage of the PMOS transistor 240.

Due to process or environmental variations, the critical voltages of the PMOS transistors 240 of the pixel units P(1,1)~P(m,n) on the same substrate may be different, resulting in that even if multiple pixel units receive data signals of the same voltage level, the load circuits of these pixel units are driven to different degrees. During each scanning cycle, the operation of the PMOS transistor 250 in the compensation circuit 25 makes the voltage V21 on the node N21 of each pixel unit equal to the voltage (ARVDD-Vth), thereby compensating for the difference in critical voltages of different pixel units. According to the above, since the DC voltage ARVDD is known, the compensation operation of the compensation circuit 25 can obtain the critical voltage Vth of the PMOS transistor 240 through the voltage V21 on the node N21. According to the above, the period from time point T33 to T34 corresponds to the compensation stage (or can be called the TFT critical voltage acquisition stage) 31 of the pixel unit P(1,1).

At time point T34, the scanning signal S1 switches from the low voltage level LL to the high voltage level LH (i.e., the scanning signal S1 switches from the enabled state to the disabled state) to turn off the PMOS transistors 200 and 250.

At time point T35 after time point T34, the drive enable signal EM1 is switched from the high voltage level LH to the low voltage level LL (i.e., the drive enable signal EM1 is switched from the disabled state to the enabled state) to turn on the PMOS transistors 210 and 260. Since the PMOS transistor 210 is turned on, the voltage V20 on the node N20 is instantly pulled down from the voltage Vdata of the data signal D1 to the DC voltage Vref. Through the coupling effect of the capacitor Cst, the voltage V21 on the node N21 decreases, and the decrease is (Vdata-Vref), that is, the gate voltage of the PMOS transistor 240 decreases by (Vdata-Vref). The PMOS transistor 240 is turned on according to the voltage V21 at this time, and generates a driving current I20. The driving current I20 is provided to the light-emitting diodes 270 and 271 of the load circuit 27 through the turned-on PMOS transistor 260 to light up the light-emitting diodes 270 and 271. According to the above, after the time point T35, it is the driving stage 32 of the pixel unit P(1,1) until the driving enable signal EM1 is switched from the low voltage level LL to the high voltage level LH again or the scanning signal S0 is switched from the high voltage level LH to the low voltage level LL again.

Referring to FIG. 2 and FIG. 3, it is assumed that the capacitor Cdc is not provided in the pixel unit P(1,1). At time point T35, the drive enable signal EM1 switches from the high voltage level LH to the low voltage level LL. At the moment when the drive enable signal EM1 switches from the high voltage level LH to the low voltage level LL, based on the DC voltage Vref, the voltage V20 on the node N20 has a short downward surge. Based on the coupling effect of the capacitor Cst, the voltage V21 on the node N21 (i.e., the gate voltage of the PMOS transistor 240) also has a short downward surge. The PMOS transistor 240 generates a large instantaneous current according to the short-term surge of its gate voltage, so that the voltage V22 on the node N23 has a short upward surge P31. Referring to Figures 2 and 3, when the data signal D1 represents zero grayscale or low grayscale data, at the moment when the drive enable signal EM1 switches from the high voltage level LH to the low voltage level LL, the voltage V22 on the node N23 has a surge P31, which instantly lights up the LEDs 270 and 271, causing dark-state light leakage in the pixel unit P(1,1).

According to the disclosed embodiment, a capacitor Cdc is provided, which is coupled between the node N20 and the power terminal T23. At the moment when the drive enable signal EM1 switches from the high voltage level LH to the low voltage level LL, the downward short-term surge of the voltage V20 on the node N20 is reduced due to the provision of the capacitor Cdc, and the downward short-term surge of the voltage V21 on the node N21 (i.e., the gate voltage of the PMOS transistor 240) is also reduced. The instantaneous current generated by the PMOS transistor 240 is reduced, so that the upward short-term surge of the voltage V22 on the node N23 is reduced.

As shown in FIG. 3, compared with the surge P31 when the capacitor Cdc is not set, the surge P30 of the voltage V22 when the capacitor Cdc is set is smaller. In this way, when the data signal D1 represents zero grayscale or low grayscale data, at the moment when the drive enable signal EM1 switches from the high voltage level LH to the low voltage level LL, the smaller surge P30 of the voltage V22 on the node N23 will not light up the LEDs 270 and 271, or drive the LEDs 270 and 271 to emit light with lower brightness, which reduces the dark state light leakage phenomenon of the pixel unit P(1,1).

In the circuit structure of the pixel unit P(1,1) of this case, as the capacitance value of the capacitor Cdc increases, the upward short-term surge of the voltage V22 becomes smaller when the driving enable signal EM1 switches from the high voltage level LH to the low voltage level LL, resulting in a better effect of improving the dark state light leakage phenomenon.

According to the embodiment disclosed herein, the present case only needs to add a capacitor Cdc, which is coupled to the node N20 where the reset capacitor Cst and the reset circuit 22 are coupled together, to eliminate or mitigate the dark state light leakage phenomenon of the light-emitting module 1.

In the above-mentioned embodiments, the PMOS transistors 200, 210, 220, 230, 240, 250, and 260 are implemented as PMOS transistors with a single gate structure. In other embodiments, the PMOS transistors 200, 210, 220, 230, 240, 250, and 260 can be implemented as PMOS transistors with a dual gate structure.

FIG. 4 shows a display device using the above disclosed light-emitting module according to an embodiment of the present disclosure. Referring to FIG. 4, the display device 4 is a liquid crystal display (LCD) device, including an LCD panel 40, a controller 41, and a backlight module 42. The controller 41 operatively couples the LCD panel 40 and the backlight module 42, and provides control signals, such as a clock signal, a start signal, or image data, to the LCD panel 40 and the backlight module 42. In this embodiment, the backlight module 42 is implemented by the light-emitting module 1 shown in FIG. 1.

FIG. 5 shows an electronic device using the display device 4 disclosed above according to an embodiment of the present disclosure. Referring to FIG. 5, the electronic device 5 includes an input unit 50 and the display device 4 shown in FIG. 4. The input unit 50 is operatively coupled to the display device 4 and provides input signals (e.g., image signals) to the display device 4. The controller 41 provides control signals to the LCD panel 40 and the backlight module 42 based on these input signals. In one embodiment, the electronic device 5 may also include an antenna device, a sensing device, or a splicing device, but not limited thereto. The electronic device 5 may be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but not limited thereto. It should be noted that the electronic device can be any combination of the above arrangements, but is not limited to this.

FIG. 6 shows a display device using the above disclosed light-emitting module according to another embodiment of the present disclosure. Referring to FIG. 6, the display device 6 is a micro light-emitting diode (Micro LED) display device, including an LED display panel 60 and a controller 61. The controller 61 is operatively coupled to the LED display panel 60 and provides a control signal, such as a clock signal, a start signal, or image data, to the LED display panel 60. In this embodiment, the LED display panel 60 is implemented by the light-emitting module 1 shown in FIG. 1.

FIG. 7 shows an electronic device using the display device 6 disclosed above according to another embodiment of the present disclosure. Referring to FIG. 7, the electronic device 7 includes an input unit 70 and the display device 6 shown in FIG. 6. The input unit 70 is operatively coupled to the display device 6 and provides input signals (such as image signals) to the display device 6. The controller 61 provides control signals to the LED display panel 60 based on these input signals. In one embodiment, the electronic device 7 may also include an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device 7 may be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above arrangements, but is not limited to this.

According to the above, the pixel unit proposed in this case includes not only the input circuit 20, the switch circuit 21, the reset circuits 22 and 23, the drive circuit 24, the compensation circuit 25, the switch circuit 26, the load circuit 27, and the capacitor Cst, but also the capacitor Cdc. By setting the capacitor Cdc, the surge on the anode end of the light-emitting diode can be reduced. In this way, when the data signal D1 represents zero grayscale or low grayscale data, the dark state light leakage phenomenon of the pixel unit can be reduced.

As long as the features of each embodiment do not violate the spirit of the invention or conflict with each other, they can be mixed and matched at will. Although the present disclosure has been disclosed as above with the preferred embodiment, it is not used to limit the present disclosure. Anyone with common knowledge in the relevant technical field can make some changes and embellishments without departing from the spirit and scope of the present disclosure. For example, the system, device or method described in the embodiment of the present disclosure can be implemented by a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present disclosure shall be defined by the scope of the attached patent application.

20: Input circuit 20A: Input terminal 20B: Output terminal 21: Switching circuit 22, 23: Reset circuit 24: Drive circuit 24A: Input terminal 24B: Output terminal 24C: Control terminal 25: Compensation circuit 26: Switching circuit 27: Load circuit 200, 210, 220, 230, 240, 250, 260~PMOS transistor 270, 271: Light-emitting diode ARVDD, ARVSS: DC voltage Cdc, Cst: Capacitor D1: Data signal DL1: Data line EM1: Drive enable signal GND: ground I20: drive current L1: control line N20~N23: node P(1,1): pixel unit S0~S1: scan signal SL0~SL1: scan line T20~T24: power supply terminal V23, Vref, Vrst: DC voltage V20, V21, V22: voltage

Claims (16)

An electronic device includes: a plurality of pixel units arranged in a pixel array, wherein a first pixel unit among the pixel units receives a data signal, a first scanning signal, a second scanning signal, and a drive enable signal, and includes: an input circuit controlled by the second scanning signal, and having an input terminal for receiving the data signal and an output terminal coupled to a first node; a first switch circuit coupled between a first power terminal and the first node, and controlled by the drive enable signal; a first capacitor coupled between the first node and a second power terminal; a second capacitor coupled between the first node and a second node; a drive circuit having an input terminal coupled to a third power terminal, an output terminal coupled to a third power terminal, and an output terminal coupled to a third power terminal. An output terminal of a third node and a control terminal coupled to the second node; and a load circuit coupled between the third node and a fourth power terminal, wherein the first pixel unit further includes: a first reset circuit coupled between the first power terminal and the first node and controlled by the first scanning signal; a second reset circuit coupled between a fifth power terminal and the second node and controlled by the first scanning signal; a compensation circuit coupled between the second node and the third node and controlled by the second scanning signal; and a second switch circuit coupled between the third node and a fourth node and controlled by the drive enable signal; wherein the load circuit is coupled between the fourth node and the fourth power terminal. An electronic device as claimed in claim 1, wherein the ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is in the range of 0.39 to 1.26. An electronic device as claimed in claim 1, wherein the second power supply terminal receives a DC voltage. An electronic device as claimed in claim 1, wherein, for the first pixel unit, the first scanning signal and the second scanning signal are enabled in sequence, and the period during which the first scanning signal is enabled does not overlap with the period during which the second scanning signal is enabled. As in claim 1, the electronic device, wherein during the period when the first scanning signal and the second scanning signal are enabled, the drive enable signal is in a disabled state, and after the second scanning signal is enabled, the drive enable signal switches from the disabled state to an enabled state. An electronic device as claimed in claim 1, wherein the input circuit comprises: a transistor having a first electrode coupled to the input end of the input circuit, a second electrode coupled to the output end of the input circuit, and a control electrode for receiving the second scanning signal. As in the electronic device of claim 1, the first switch circuit includes: a transistor having a first electrode coupled to the first power terminal, a second electrode coupled to the first node, and a control electrode receiving the drive enable signal. As in claim 1, the driving circuit comprises: a transistor having a first electrode, a second electrode, and a control electrode, respectively coupled to the input terminal of the driving circuit, the output terminal of the driving circuit, and the second node. An electronic device as claimed in claim 1, wherein the first reset circuit comprises: a first transistor having a first electrode coupled to the first power supply terminal, a second electrode coupled to the first node, and a control electrode receiving the first scanning signal; and wherein the second reset circuit comprises: a second transistor having a first electrode coupled to the fifth power supply terminal, a second electrode coupled to the second node, and a control electrode receiving the first scanning signal. An electronic device as claimed in claim 1, wherein the compensation circuit comprises: a transistor having a first electrode coupled to the third node, a second electrode coupled to the second node, and a control electrode receiving the second scanning signal. An electronic device as claimed in claim 1, wherein the second switch circuit comprises: a transistor having a first electrode coupled to the third node, a second electrode coupled to the fourth node, and a control electrode receiving the drive enable signal. As in claim 1, the load circuit comprises: at least one first load element coupled between the fourth node and the fourth power terminal. The electronic device of claim 1 further includes a display panel, wherein the pixel unit is a part of the display panel. As in claim 13, the electronic device, wherein the display panel is a micro light-emitting diode (Micro Light-Emitting Diode, Micro LED) display panel. The electronic device of claim 1 further includes a display panel and a backlight module, wherein the pixel unit is a part of the backlight module. As in claim 15, the electronic device, wherein the display panel is a liquid crystal display (LCD) panel.