TWI854251B - Pixel circuit, OLED display device and information processing device - Google Patents

Abstract

The present invention mainly discloses a pixel circuit, which is used to form an OLED pixel unit with an OLED element, and includes: a data driving unit, a capacitor, a first switch unit, and a second switch unit, wherein the data driving unit is coupled to the capacitor, the first switch unit and the second switch unit. In particular, the present invention uses five TFT elements to form the data driving unit, uses one TFT element as the first switch unit, and uses one TFT element as the second switch unit. According to this design, the pixel circuit of the present invention has the functions of Vth compensation and short-term afterimage improvement. Therefore, for an OLED display panel including the pixel circuit of the present invention, even in the process of switching from displaying a half-black/half-white image to displaying a full-grayscale (48) image, the so-called short-term afterimage phenomenon will not occur.

Description

Pixel circuit, OLED display device and information processing device

The present invention relates to the technical field of OLED display devices, and in particular to a pixel circuit used to form an OLED pixel unit with an OLED element.

It is known that flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays. Liquid crystal displays are a type of non-self-luminous flat panel displays that have been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays that are currently in mainstream applications.

FIG1 is a block diagram of a known OLED display. As shown in FIG1 , the structure of the OLED display 1a mainly includes: an OLED display panel 11a, a gate drive unit 12a (or scan drive unit), a source drive unit 13a (or data drive unit), a display controller 14a, and a voltage conversion unit 15a, wherein the OLED display panel 11a includes M×N OLED pixel units, and each of the OLED pixel units is composed of a pixel circuit 111a and an OLED element 112a.

Traditionally, the pixel circuit 111a adopts a 2T1C structure, that is, it includes two thin-film transistor (TFT) components and a capacitor. In recent years, in order to improve the uneven brightness of the OLED element 112a caused by the difference in the transistor threshold voltage (Vth) and the cross-voltage increase caused by the aging of the OLED element 112a, the pixel circuit 111a using the 4T1C or 5T1C structure has been proposed and has been actually applied in the production of the OLED display panel 11a. Unfortunately, the existing pixel circuit 111a still has the problem of uneven brightness of the OLED element 112a caused by the difference in the threshold voltage, which eventually causes the so-called Mura phenomenon in some blocks of the OLED display panel 11a.

On the other hand, practical experience shows that due to the hysteresis effect of the TFT element of the pixel circuit 111a, the OLED display panel 11a may have a short-term afterimage phenomenon. To be more specific, when the OLED display panel 11a switches from displaying a half-black/half-white image to displaying a full grayscale (Gray level=48) image, the OLED display panel 11a will have the so-called short-term afterimage phenomenon. Practical experience also shows that after the short-term afterimage phenomenon occurs, the display screen of the OLED display panel 11a needs a certain amount of time to return to normal. Unfortunately, the pixel circuit of the prior art cannot solve the problem of short-term afterimage phenomenon.

From the above description, it can be seen that a new pixel circuit is urgently needed in this field.

The main purpose of the present invention is to provide a pixel circuit for forming an OLED pixel unit with an OLED element, and M×N OLED pixel units form an OLED panel. The pixel circuit of the present invention adopts a 7T1C structure, which can compensate for the difference in threshold voltage between the 7 transistors, so that each OLED element emits light with uniform brightness, ensuring that the OLED display panel will not have the so-called Mura phenomenon during the image display process. In addition, the pixel circuit of the present invention also has the function of improving short-term residual images. Therefore, for an OLED display panel including the pixel circuit of the present invention, even if the display is switched from displaying a half-black/half-white image to displaying a full-grayscale (48) image, the so-called short-term residual image phenomenon will not occur.

To achieve the above-mentioned object, the present invention proposes an embodiment of the pixel circuit, which includes: a data driving unit, having a first electrical terminal, a first control terminal, a second electrical terminal, a second control terminal, a third control terminal, a third electrical terminal, a fourth electrical terminal, a second control terminal, and a fifth electrical terminal, wherein the first electrical terminal is coupled to a first driving voltage, the first control terminal is coupled to a scanning signal, the second electrical terminal is coupled to a display data signal, the second control terminal is coupled to a first gate control signal, the third control terminal is coupled to a light-emitting control signal, the third electrical terminal is used to couple to the anode terminal of the OLED element, the second control terminal is coupled to a common voltage signal, and the third electrical terminal is coupled to the anode terminal of the OLED element. The fourth electrical terminal is coupled to the fifth electrical terminal; a storage capacitor is coupled between the first electrical terminal and the fifth electrical terminal; a first switch unit has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a second gate control signal, the first terminal is coupled to the fourth electrical terminal of the data drive unit, and the second terminal is coupled to a reset signal; and a second switch unit also has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the second gate control signal, the first terminal is coupled to a first common point between the anode terminal of the OLED element and the third electrical terminal of the data drive unit, and the second terminal is coupled to the second terminal of the first switch unit.

In one embodiment, the data drive unit includes: a first TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fifth electrical terminal of the data drive unit; a second TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the first electrical terminal and the gate terminal serve as the first electrical terminal and the first control terminal of the data drive unit, and the second electrical terminal is coupled to the first electrical terminal of the first TFT element; a third TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the first electrical terminal and the gate terminal serve as the second electrical terminal and the second control terminal of the data drive unit, and the second electrical terminal is coupled to the second TFT element. The invention relates to a first TFT element, a second common point between the first electrical terminal of the first TFT element and the first electrical terminal of the first TFT element; a fourth TFT element, which has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the second electrical terminal serve as the fourth control terminal and the fourth electrical terminal of the data drive unit, and the first electrical terminal is coupled to the second electrical terminal of the first TFT element; and a fifth TFT element, which has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the second electrical terminal serve as the third control terminal and the third electrical terminal of the data drive unit, and the first electrical terminal is coupled to a third common point between the first electrical terminal of the fourth TFT element and the second electrical terminal of the first TFT element.

In one embodiment, the first switch unit includes a sixth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, which respectively serve as the control terminal, the first terminal and the second terminal of the first switch unit S1.

In one embodiment, the second switch unit includes a seventh TFT element having a gate terminal, a first electrical terminal and a second electrical terminal serving as the control terminal, the first terminal and the second terminal of the second switch unit respectively.

In one embodiment, during a frame display period, the first gate control signal has a low level time period, the second gate control signal has a first low level time period, a second low level time period and a third low level time period, the common voltage signal also has a first low level time period, a second low level time period and a third low level time period, the scanning signal has a high level time period, and the light modulation signal has a high level time period and a low level time period.

In one embodiment, wherein: the first low level time period of the common voltage signal is between the first low level time period and the second low level time period of the second gate control signal, and the second low level time period of the common voltage signal is between the second low level time period and the third low level time period of the second gate control signal; the low level time period of the first gate control signal and the third low level time period of the common voltage signal have the same time period width and are located in the same time period, and the low level time period of the first gate control signal The first low level time segment of the second gate control signal, the second low level time segment and the third low level time segment of the second gate control signal and the first low level time segment, the second low level time segment and the third low level time segment of the common voltage signal are all within the high level time segment of the luminescence control signal; The high level time segment of the scanning signal is within the high level time segment of the luminescence control signal; and the low level time segment of the luminescence control signal is a luminescence time segment of the OLED element.

The present invention also provides an OLED display device, which includes a display driving circuit and an OLED display panel, wherein the OLED display panel includes M×N pixel units, and each of the pixel units is composed of a pixel circuit and an OLED element; the pixel circuit includes: a data driving unit, having a first electrical terminal, a first control terminal, a second electrical terminal, a second control terminal, a third control terminal, a third electrical terminal, a fourth electrical terminal, a second control terminal, and a fifth electrical terminal, wherein the first electrical terminal is coupled to a first driving voltage, the first control terminal is coupled to a scanning signal, the second electrical terminal is coupled to a display data signal, the second control terminal is coupled to a first gate control signal, the third control terminal is coupled to a light regulation signal, and the third electrical terminal is coupled to a fifth electrical terminal. The first control terminal is coupled to the anode terminal of the OLED element, the second control terminal is coupled to a common voltage signal, and the fourth electrical terminal is coupled to the fifth electrical terminal; a storage capacitor is coupled between the first electrical terminal and the fifth electrical terminal; a first switch unit has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a second gate control signal, the first terminal is coupled to the fourth electrical terminal of the data drive unit, and the second terminal is coupled to a reset signal; and a second switch unit also has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the second gate control signal, the first terminal is coupled to a first common point between the anode terminal of the OLED element and the third electrical terminal of the data drive unit, and the second terminal is coupled to the second terminal of the first switch unit.

In one embodiment, the data drive unit includes: a first TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal serves as the fifth electrical terminal of the data drive unit; a second TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the first electrical terminal and the gate terminal serve as the first electrical terminal and the first control terminal of the data drive unit, and the second electrical terminal is coupled to the first electrical terminal of the first TFT element; a third TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the first electrical terminal and the gate terminal serve as the second electrical terminal and the second control terminal of the data drive unit, and the second electrical terminal is coupled to the second TFT element. a second common point between the first electrical terminal of the data drive unit and the first electrical terminal of the first TFT element; a fourth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the second electrical terminal serve as the fourth control terminal and the fourth electrical terminal of the data drive unit, and the first electrical terminal is coupled to the second electrical terminal of the first TFT element; and a fifth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the second electrical terminal serve as the third control terminal and the third electrical terminal of the data drive unit, and the first electrical terminal is coupled to a third common point between the first electrical terminal of the fourth TFT element and the second electrical terminal of the first TFT element.

In one embodiment, the first switch unit includes a sixth TFT element having a gate terminal, a first electrical terminal and a second electrical terminal serving as the control terminal, the first terminal and the second terminal of the first switch unit S1, respectively.

In one embodiment, the second switch unit includes a seventh TFT element having a gate terminal, a first electrical terminal and a second electrical terminal serving as the control terminal, the first terminal and the second terminal of the second switch unit respectively.

In one embodiment, during a frame display period, the first gate control signal has a low level time period, the second gate control signal has a first low level time period, a second low level time period and a third low level time period, the common voltage signal also has a first low level time period, a second low level time period and a third low level time period, the scanning signal has a high level time period, and the light modulation signal has a high level time period and a low level time period.

In one embodiment, wherein: the first low level time period of the common voltage signal is between the first low level time period and the second low level time period of the second gate control signal, and the second low level time period of the common voltage signal is between the second low level time period and the third low level time period of the second gate control signal; the low level time period of the first gate control signal and the third low level time period of the common voltage signal have the same time period width and are located in the same time period, and the low level time period of the first gate control signal The first low level time segment of the second gate control signal, the second low level time segment and the third low level time segment, and the first low level time segment, the second low level time segment and the third low level time segment of the common voltage signal are all within the high level time segment of the luminescence control signal; the high level time segment of the scanning signal is within the high level time segment of the luminescence control signal; and the low level time segment of the luminescence control signal is a luminescence time segment of the OLED element.

The present invention also provides an information processing device having the OLED display device of the present invention as described above.

In one embodiment, the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

1a:OLED display

11a: OLED display panel

111a: Pixel circuit

112a: OLED element

12a: Gate drive unit

13a: Source drive unit

14a: Display controller

15a: Voltage conversion unit

1:OLED display

11: OLED display panel

12: Gate drive unit

13: Source drive unit

14: Display controller

15: Voltage conversion unit

111: Pixel circuit

1D: Data drive unit

Cst: Storage capacitor

S1: First switch unit

S2: Second switch unit

1DT1: First electrical terminal

1DT2: Second electrical terminal

1DT3: The third electrical terminal

1DT4: Fourth electrical terminal

1DT5: Fifth electrical terminal

1DC1: First control terminal

1DC2: Second control terminal

1DC3: The third control terminal

1DC4: Fourth control terminal

M1: first TFT element

M2: Second TFT element

M3: The third TFT element

M4: the fourth TFT element

M5: The fifth TFT element

M6: Sixth TFT element

M7: Seventh TFT element

FIG. 1 is a block diagram of a known OLED display; FIG. 2 is a block diagram of an OLED display including a pixel circuit of the present invention; FIG. 3 is a circuit topology diagram of a pixel circuit of the present invention; and FIG. 4 is a working timing diagram of multiple signals used to control the pixel circuit of the present invention.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

The present invention provides a pixel circuit for forming an OLED pixel unit with an OLED element, and M×N OLED pixel units form an OLED panel. The pixel circuit of the present invention adopts a 7T1C architecture, which can compensate for the difference in threshold voltage (Vth) between the 7 transistors, so that each OLED element emits light evenly, ensuring that the OLED display panel will not have the so-called Mura phenomenon during the image display process. In addition, the pixel circuit of the present invention also has the function of improving short-term residual images. Therefore, for an OLED display panel including the pixel circuit of the present invention, even if the display is switched from displaying a half-black/half-white image to displaying a full grayscale (Gray level=48) image, the so-called short-term residual image phenomenon will not occur.

FIG2 is a block diagram of an OLED display including a pixel circuit of the present invention. As shown in FIG2, the structure of the OLED display mainly includes: an OLED display panel 11, a gate drive unit 12 (or scanning unit), a source drive unit 13 (or data drive unit), a display controller 14, and a voltage conversion unit 15, wherein the OLED display panel 11 includes M×N OLED pixel units, and each of the OLED pixel units is composed of an OLED element 112 and a pixel circuit 111 of the present invention. FIG3 is a circuit topology diagram of a pixel circuit of the present invention. As shown in FIG3 , the pixel circuit 111 of the present invention mainly includes: a data driving unit 1D, a storage capacitor Cst, a first switch unit S1, and a second switch unit S2.

As shown in FIG3 , the data drive unit 1D has a first electrical terminal 1DT1, a first control terminal 1DC1, a second electrical terminal 1DT2, a second control terminal 1DC2, a third control terminal 1DC3, a third electrical terminal 1DT3, a fourth electrical terminal 1DT4, a fourth control terminal 1DC4, and a fifth electrical terminal 1DT5, wherein the first electrical terminal 1DT1 is coupled to a first driving voltage ELVDD, and the first control terminal 1DC1 is coupled to a scanning signal Sc an(n), the second electrical terminal 1DT2 is coupled to a display data signal Data, the second control terminal 1DC2 is coupled to a first gate control signal Gate(n), the third control terminal 1DC3 is coupled to a light modulation signal EM(n), the third electrical terminal 1DT3 is used to couple to the anode terminal of an OLED element 112, the fourth control terminal 1DC4 is coupled to a common voltage signal Com(n), and the fourth electrical terminal 1DT4 is coupled to the fifth electrical terminal 1DT5.

To explain in more detail, the data-driven unit 1D includes: a first TFT element M1, a second TFT element M2, a third TFT element M3, a fourth TFT element M4, and a fifth TFT element M5. In one embodiment, the five TFT elements (M1-M5) included in the data-driven unit 1D are all P-type TFT elements, and all have a gate terminal, a first element electrical terminal (i.e., drain terminal) and a second element electrical terminal (i.e., source terminal). As shown in FIG. 3 , the gate terminal of the first TFT element M1 serves as the fifth electrical terminal 1DT5 of the data-driven unit 1D, and the first element electrical terminal and the gate terminal of the second TFT element M2 serve as the first electrical terminal 1DT1 and the first control terminal 1DC1 of the data-driven unit 1D, respectively. Furthermore, the second element electrical terminal of the second TFT element M2 is coupled to the first element electrical terminal of the first TFT element M1.

As shown in FIG3 , the first element electrical terminal and the gate terminal of the third TFT element M3 serve as the second electrical terminal 1DT2 and the second control terminal 1DC2 of the data drive unit 1D, and the second element electrical terminal thereof is coupled to a second common point CN2 between the first element electrical terminal of the second TFT element M2 and the first element electrical terminal of the first TFT element M1. On the other hand, the gate terminal and the second element electrical terminal of the fourth TFT element M4 serve as the fourth control terminal 1DC4 and the fourth electrical terminal 1DT4 of the data drive unit 1D, and the first element electrical terminal thereof is coupled to the second element electrical terminal of the first TFT element M1. Furthermore, the gate terminal and the second element electrical terminal of the fifth TFT element M5 serve as the third control terminal 1DC3 and the third electrical terminal 1DT3 of the data driving unit 1D respectively, and the first element electrical terminal thereof is coupled to a third common point CN3 between the first element electrical terminal of the fourth TFT element M4 and the second element electrical terminal of the first TFT element M1.

On the other hand, as shown in FIG3 , the storage capacitor Cst is coupled between the first electrical terminal 1DT1 and the fifth electrical terminal 1DT5. Furthermore, the first switch unit S1 has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a second gate control signal Gate(n-1), the first terminal is coupled to the fourth electrical terminal 1DT4 of the data driving unit 1D, and the second terminal is coupled to a reset signal RES_X. On the other hand, the second switch unit S2 also has a control end, a first end and a second end, wherein the control end is coupled to the second gate control signal Gate(n-1), the first end is coupled to a first common point CN1 between the anode end of the OLED element 112 and the third electrical end 1DT3 of the data driving unit 1D, and the second end is coupled to the second end of the first switch unit S1.

To explain in more detail, the first switch unit S1 includes a sixth TFT element M6, and the second switch unit S2 includes a seventh TFT element M7. Similarly, the sixth TFT element M6 and the seventh TFT element M7 are also P-type TFT elements, and both have a gate terminal, a first element electrical terminal (i.e., drain terminal) and a second element electrical terminal (i.e., source terminal). According to the design of the present invention, the gate terminal, the first element electrical terminal and the second element electrical terminal of the sixth TFT element M6 serve as the control terminal, the first terminal and the second terminal of the first switch unit S1, respectively. And, the gate terminal, the first element electrical terminal and the second element electrical terminal of the seventh TFT element M7 serve as the control terminal, the first terminal and the second terminal of the second switch unit S2, respectively.

The present invention also designs the timing waveforms of the first gate control signal Gate(n), the second gate control signal Gate(n-1), the common voltage signal Com(n), the scanning signal Scan(n) and the luminous modulation signal EM(n). FIG. 4 is a working timing diagram of multiple signals used to control the pixel circuit of the present invention. As shown in FIG. 3 and FIG. 4, during a frame display period, the first gate control signal Gate(n) has a low level time period (i.e., time period T3), and the second gate control signal Gate(n-1) has a first low level time period, a second low level time period and a third low level time period, which are respectively marked as time periods T1_1, T1_2 and T1_3. Furthermore, the common voltage signal Com(n) also has a first low level time period, a second low level time period and a third low level time period, which are marked as time periods T2_1, T2_2 and T3 respectively. It is worth noting that since the low level time period of the first gate control signal Gate(n) and the third low level time period of the common voltage signal Com(n) have the same time period width and are located in the same time period, they are both marked as time period T3 in FIG. 4 .

As shown in FIG. 4 , the scanning signal Scan(n) has a high level time period, and the luminous modulation signal EM(n) has a high level time period and a low level time period. In particular, the low level time period of the luminous modulation signal EM(n) is a luminous time period of the OLED element 112, and is therefore marked as time period T4 in FIG. 4 .

According to the design of the present invention, the first low level time period (i.e., T2_1) of the common voltage signal Com(n) is between the first low level time period (i.e., T1_1) and the second low level time period (i.e., T1_2) of the second gate control signal Gate(n-1), and the second low level time period (i.e., T2_2) of the common voltage signal Com(n) is between the second low level time period (i.e., T1_2) and the third low level time period (i.e., T1_3) of the second gate control signal Gate(n-1). Furthermore, the low level time period of the first gate control signal Gate(n) and the third low level time period (i.e., T3) of the common voltage signal Com(n) both fall within the high level time period of the scan signal Scan(n).

As shown in FIG4 , the first low level time period (T1_1), the second low level time period (T1_2) and the third low level time period (T1_3) of the second gate control signal Gate(n-1) and the first low level time period (T2_1), the second low level time period (T2_2) and the third low level time period (T3) of the common voltage signal Com(n) all fall within the high level time period of the luminous modulation signal EM(n). Moreover, the high level time period of the scanning signal Scan(n) also falls within the high level time period of the luminous modulation signal EM(n).

As shown in FIG3 and FIG4, within the time period T1_1, the second gate control signal Gate(n-1) and the scanning signal Scan(n) are both at a low level, so the first TFT element M1, the second TFT element M2, the sixth TFT element M6, and the seventh TFT element M7 are all turned on, so that the node voltages of the nodes N1 and N3 are both RES_X, completing the reset work of the anode terminal of the OLED element 112 and the storage capacitor Cst. On the other hand, at this time, the node voltage of the node N2 is ELVDD (i.e., the first driving voltage). It is worth noting that within the time period T1_1, the conduction of the first TFT element M1, the second TFT element M2, the sixth TFT element M6, and the seventh TFT element M7 helps to improve the short-term afterimage phenomenon.

As shown in FIG3 and FIG4, within the time period T2_1, the common voltage signal Com(n) and the scanning signal Scan(n) are both at a low level, so the first TFT element M1, the second TFT element M2 and the fourth TFT element M4 are turned on at the same time, so that the first driving voltage ELVDD charges the storage capacitor Cst through the second TFT element M2, the first TFT element M1 and the fourth TFT element M4 until the node voltage of the node N1 is charged to ELVDD+Vth_M1, where Vth_M1 is the threshold voltage of the first TFT element M1. When the node voltage of the node N1 is equal to ELVDD+Vth_M1, the first TFT element M1 is turned off, thereby stopping charging the storage capacitor Cst. It is worth noting that time period T1_1 is the first time period of short-term afterimage improvement, while time period T2_1 is the second time period of short-term afterimage improvement.

Furthermore, the circuit operates in the time period T1_2 in the same manner as it operates in the time period T1_1. Furthermore, the circuit operates in the time period T2_2 in the same manner as it operates in the time period T2_1. According to this circuit operation mode, the effect of improving short-term afterimages can be enhanced through circuit operation in the two time periods T1_2 and T2_2.

As shown in Figures 3 and 4, within the time period T3, the common voltage signal Com(n) and the first gate control signal Gate(n) are both at a low level, so the first TFT element M1, the third TFT element M3 and the fourth TFT element M4 are turned on at the same time, so that the display data signal Data charges the storage capacitor Cst through the third TFT element M3, the first TFT element M1 and the fourth TFT element M4 until the node voltage of the node N1 is charged to Vdata+Vth_M1, where Vth_M1 is the threshold voltage of the first TFT element M1. When the node voltage of the node N1 is equal to ELVDD+Vth_M1, the first TFT element M1 is turned off, thereby stopping charging the storage capacitor Cst and completing the work of data voltage writing and Vth compensation.

Finally, within the time period T4 (i.e., the luminous time period of the OLED element 112), the scanning signal Scan(n) and the luminous modulation signal EM(n) are both at a low level, so the first TFT element M1, the second TFT element M2 and the fifth TFT element M5 are turned on at the same time, thereby driving the OLED element 112 to emit light.

It is worth noting that during the operation of the pixel circuit 111 of the present invention, Vth is offset, so that the driving current of the OLED element 112 has nothing to do with Vth, thereby eliminating the phenomenon of Mura caused by uneven display brightness of the OLED element 112 due to inconsistent Vth. At the same time, the improvement of short-term residual image defects is completed during the initialization stage of the pixel circuit 1 of the present invention.

Thus, the above has completely and clearly described a pixel circuit of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a pixel circuit for forming an OLED pixel unit with an OLED element, and M×N OLED pixel units form an OLED panel. The pixel circuit of the present invention adopts a 7T1C structure, which can compensate for the difference in threshold voltage between the 7 transistors, so that each OLED element emits light with uniform brightness, ensuring that the OLED display panel will not have the so-called Mura phenomenon during the image display process. In addition, the pixel circuit of the present invention also has the function of improving short-term residual images. Therefore, for an OLED display panel including the pixel circuit of the present invention, even if the display is switched from displaying a half-black/half-white image to displaying a full-grayscale (48) image, the so-called short-term residual image phenomenon will not occur.

(2) The present invention also provides an OLED display device, which includes at least one display driving circuit and an OLED display panel, wherein the OLED display panel includes M×N OLED pixel units, and is characterized in that each of the OLED pixel units is composed of an OLED element and a pixel circuit of the present invention.

(3) The present invention also provides an information processing device having the OLED display device of the present invention as described above. Furthermore, the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

111: Pixel circuit

1D: Data drive unit

Cst: Storage capacitor

S1: First switch unit

S2: Second switch unit

1DT1: First electrical terminal

1DT2: Second electrical terminal

1DT3: The third electrical terminal

1DT4: Fourth electrical terminal

1DT5: Fifth electrical terminal

1DC1: First control terminal

1DC2: Second control terminal

1DC3: The third control terminal

1DC4: Fourth control terminal

M1: first TFT element

M2: Second TFT element

M3: The third TFT element

M4: the fourth TFT element

M5: The fifth TFT element

M6: Sixth TFT element

M7: Seventh TFT element

Claims (8)

A pixel circuit includes: a data drive unit, which is composed of a first TFT element, a second TFT element, a third TFT element, a fourth TFT element, and a fifth TFT element, and has a first electrical terminal coupled to a first driving voltage, a first control terminal coupled to a scanning signal, a second electrical terminal coupled to a display data signal, a second control terminal coupled to a first gate control signal, a third control terminal coupled to a light-emitting control signal, and is used to couple to an OLED element. a third electrical terminal connected to the anode terminal of the transistor, a fourth electrical terminal, a fourth control terminal coupled to a common voltage signal, and a fifth electrical terminal mutually coupled to the fourth electrical terminal; wherein the first TFT element, the second TFT element, the third TFT element, the fourth TFT element, and the fifth TFT element all have a gate terminal, a first element electrical terminal, and a second element electrical terminal, the second TFT element, the first TFT element, and the fifth TFT element are stacked, and the third TFT element is connected to the anode terminal of the transistor. The second element electrical terminal of the fourth TFT element is coupled to a first stacking point between the second TFT element and the first TFT element, and the second element electrical terminal of the fourth TFT element is coupled to a second stacking point between the first TFT element and the fifth TFT element; wherein the gate terminal of the first TFT element serves as the fifth electrical terminal, the first element electrical terminal and the gate terminal of the second TFT element serve as the first electrical terminal and the first control terminal respectively, and the first element electrical terminal of the third TFT element serves as the first control terminal. The first electrical terminal and the gate terminal are used as the second electrical terminal and the second control terminal respectively, the gate terminal of the fourth TFT element and the second element electrical terminal are used as the fourth control terminal and the fourth electrical terminal respectively, and the gate terminal and the second element electrical terminal of the fifth TFT element are used as the third control terminal and the third electrical terminal respectively; a storage capacitor is coupled between the first electrical terminal and the fifth electrical terminal; a first switch unit has a control terminal, a first terminal and a second terminal, wherein the control terminal The control terminal is coupled to a second gate control signal, the first terminal is coupled to the fourth electrical terminal of the data driving unit, and the second terminal is coupled to a reset signal; and a second switch unit, which also has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the second gate control signal, the first terminal is coupled to a first common point between the anode terminal of the OLED element and the third electrical terminal of the data driving unit, and the second terminal is coupled to the second terminal of the first switch unit; wherein, in a frame display During the period, the first gate control signal has a low level time period, the second gate control signal has a first low level time period, a second low level time period and a third low level time period, the common voltage signal also has a first low level time period, a second low level time period and a third low level time period, the scanning signal has a high level time period, and the light modulation signal has a high level time period and a low level time period; the first low level time period of the common voltage signal is between the second gate The first low level time period of the control signal is between the first low level time period and the second low level time period, and the second low level time period of the common voltage signal is between the second low level time period and the third low level time period of the second gate control signal; the low level time period of the first gate control signal and the third low level time period of the common voltage signal have the same time period width and are located in the same time period, and the low level time period of the first gate control signal is between the high level time period of the scanning signal ; The first low level time segment, the second low level time segment and the third low level time segment of the second gate control signal and the first low level time segment, the second low level time segment and the third low level time segment of the common voltage signal are all within the high level time segment of the luminescence modulation signal; the high level time segment of the scanning signal is within the high level time segment of the luminescence modulation signal; and the low level time segment of the luminescence modulation signal is a luminescence time segment of the OLED element. A pixel circuit as described in claim 1, wherein the first switch unit includes a sixth TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal as the control terminal, the first terminal and the second terminal of the first switch unit respectively. The pixel circuit as described in claim 2, wherein the second switch unit includes a seventh TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal serving as the control terminal, the first terminal and the second terminal of the second switch unit respectively. An OLED display device includes a display driving circuit and an OLED display panel, wherein the OLED display panel includes M×N pixel units, and each of the pixel units is composed of a pixel circuit and an OLED element; the pixel circuit includes: a data driving unit, which is composed of a first TFT element, a second TFT element, a third TFT element, a fourth TFT element, and a fifth TFT element, and has a first electrical terminal coupled to a first driving voltage, a first terminal coupled to a A first control terminal coupled to a scanning signal, a second electrical terminal coupled to a display data signal, a second control terminal coupled to a first gate control signal, a third control terminal coupled to a light modulation signal, a third electrical terminal for coupling to an anode terminal of an OLED element, a fourth electrical terminal, a fourth control terminal coupled to a common voltage signal, and a fifth electrical terminal coupled to the fourth electrical terminal; wherein the first TFT element, the second TFT element, the third TFT element, the fourth TFT element, and the fifth TFT element The elements all have a gate terminal, a first element electrical terminal and a second element electrical terminal, the second TFT element, the first TFT element and the fifth TFT element are stacked, the third TFT element is coupled to a first stacking point between the second TFT element and the first TFT element with its second element electrical terminal, and the fourth TFT element is coupled to a second stacking point between the first TFT element and the fifth TFT element with its second element electrical terminal; wherein the gate terminal of the first TFT element serves as the fifth electrical terminal, the The first element electrical terminal and the gate terminal of the second TFT element serve as the first electrical terminal and the first control terminal respectively, the first element electrical terminal and the gate terminal of the third TFT element serve as the second electrical terminal and the second control terminal respectively, the gate terminal and the second element electrical terminal of the fourth TFT element serve as the fourth control terminal and the fourth electrical terminal respectively, and the gate terminal and the second element electrical terminal of the fifth TFT element serve as the third control terminal and the third electrical terminal respectively; a storage capacitor is coupled to the first TFT element; a first switch unit having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to a second gate control signal, the first terminal is coupled to the fourth electrical terminal of the data drive unit, and the second terminal is coupled to a reset signal; and a second switch unit having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the second gate control signal, the first terminal is coupled to a first electrical terminal between the anode terminal of the OLED element and the third electrical terminal of the data drive unit, and the second terminal is coupled to a reset signal. A common contact, and the second end is coupled to the second end of the first switch unit; wherein, during a frame display period, the first gate control signal has a low level time period, the second gate control signal has a first low level time period, a second low level time period and a third low level time period, the common voltage signal also has a first low level time period, a second low level time period and a third low level time period, the scanning signal has a high level time period, and the light modulation signal has a high level time period and a low level time period; the public The first low level time period of the common voltage signal is between the first low level time period and the second low level time period of the second gate control signal, and the second low level time period of the common voltage signal is between the second low level time period and the third low level time period of the second gate control signal; the low level time period of the first gate control signal and the third low level time period of the common voltage signal have the same time period width and are located in the same time period, and the low level time period of the first gate control signal is within the scanning period. The first low level time segment of the second gate control signal, the second low level time segment and the third low level time segment of the common voltage signal are all within the high level time segment of the luminescence control signal; the high level time segment of the scanning signal is within the high level time segment of the luminescence control signal; and the low level time segment of the luminescence control signal is a luminescence time segment of the OLED element. An OLED display device as described in claim 4, wherein the first switch unit includes a sixth TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal as the control terminal, the first terminal and the second terminal of the first switch unit respectively. The OLED display device as described in claim 5, wherein the second switch unit includes a seventh TFT element having a gate terminal, a first element electrical terminal and a second element electrical terminal serving as the control terminal, the first terminal and the second terminal of the second switch unit respectively. An information processing device, characterized in that it has at least one OLED display device as described in any one of claim 4 to claim 6. The information processing device as described in claim 7, wherein the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

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