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TWI850789B - Method for manufacturing VCSEL with controllable optical path, high thermal conductivity and low resistance - Google Patents

Method for manufacturing VCSEL with controllable optical path, high thermal conductivity and low resistance Download PDF

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TWI850789B
TWI850789B TW111138070A TW111138070A TWI850789B TW I850789 B TWI850789 B TW I850789B TW 111138070 A TW111138070 A TW 111138070A TW 111138070 A TW111138070 A TW 111138070A TW I850789 B TWI850789 B TW I850789B
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dbr
optical path
vcsel
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thermal conductivity
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TW202324865A (en
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潘德烈
李承遠
李佳勳
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大陸商深圳市德明利光電有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18311—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement using selective oxidation
    • H01S5/18313—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement using selective oxidation by oxidizing at least one of the DBR layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Semiconductor Lasers (AREA)

Abstract

本發明涉及一種光學路徑可控高導熱、低電阻的VCSEL製作方法，其中該方法包括以下步驟：將一MQW層上方的主要DBR AlxiGa1-xiAs/AlyGa1-yAs(xi>y，0

Figure 111138070-A0305-02-0001-2
y
Figure 111138070-A0305-02-0001-3
1，且xi由上至下逐漸變大)中高Al%組分AlxiGa1-xiAs中的週邊部分進行完全氧化，使其轉變成Al2O3，在所需的光學路徑上形成一AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構並使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構從上至下逐漸變窄，同時通過控制較臨近MQW的低Al%組分AlzGa1-zAs的氧化速率，繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，其中Al%組分滿足z>xi>y；將週邊部分完全氧化所形成的Al2O3以化學蝕刻方式去除，保留光學路徑的AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構；及去除週邊部分的Al2O3所形成的空間以原子層沉積、濺鍍、蒸鍍及電鍍中的一種或多種組合方式填充歐姆金屬，以形成低電阻的電學導通路徑。 The present invention relates to a method for manufacturing a VCSEL with controllable optical path, high thermal conductivity and low resistance, wherein the method comprises the following steps: placing a main DBR Al xi Ga 1-xi As/Al y Ga 1-y As (xi>y, 0
Figure 111138070-A0305-02-0001-2
y
Figure 111138070-A0305-02-0001-3
1, and xi gradually increases from top to bottom) in the peripheral part of the high Al% component Al xi Ga 1-xi As is completely oxidized to convert it into Al 2 O 3 , forming an Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure on the required optical path and making the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure gradually narrow from top to bottom. At the same time, by controlling the oxidation rate of the low Al% component Al z Ga 1-z As close to the MQW, the size of the current aperture of the central unoxidized Al z Ga 1-z As is controlled, wherein the Al% component satisfies z>xi>y; the Al 2 O 3 formed by the complete oxidation of the peripheral part is removed by chemical etching, and the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure of the optical path is retained. 1-xi As/Al y Ga 1-y As DBR stacking structure; and the space formed by removing the peripheral Al 2 O 3 is filled with ohmic metal by one or more combinations of atomic layer deposition, sputtering, evaporation and electroplating to form a low-resistance electrical conduction path.

Description

光學路徑可控高導熱、低電阻的VCSEL製作方法 Method for manufacturing VCSEL with controllable optical path, high thermal conductivity and low resistance

本發明涉及VCSEL技術領域，尤其涉及一種光學路徑可控高導熱、低電阻的VCSEL製作方法。 The present invention relates to the field of VCSEL technology, and in particular to a method for manufacturing a VCSEL with controllable optical path, high thermal conductivity and low resistance.

現有的諧振腔反射鏡是由AlxGa1-xAs/AlyGa1-yAs以外延方式堆疊而成。由於其折射率差異小，導致需要比較多對AlxGa1-xAs/AlyGa1-yAs堆疊以達到接近99%的反射率。電流局限由氧化工藝將AlGaAs轉化成Al2O3，週邊被氧化的形成電流局限層，沒被氧化的形成電流通道。整體的電流通道較小、且AlGaAs本身就是比較難摻雜的半導體材料，相較於金屬而言電阻較高。 The existing resonant cavity reflector is made of Al x Ga 1-x As/ Aly Ga 1-y As epitaxially stacked. Due to the small difference in refractive index, more pairs of Al x Ga 1-x As/ Aly Ga 1-y As need to be stacked to achieve a reflectivity close to 99%. The current confinement is achieved by converting AlGaAs into Al 2 O 3 through an oxidation process. The oxidized part forms a current confinement layer, and the unoxidized part forms a current channel. The overall current channel is small, and AlGaAs itself is a semiconductor material that is difficult to dope, and has a higher resistance than metal.

鑒於上述狀況，有必要提出一種光學路徑可控、高導熱、低電阻的VCSEL製作方法及VCSEL。 In view of the above situation, it is necessary to propose a VCSEL manufacturing method and VCSEL with controllable optical path, high thermal conductivity and low resistance.

為了解決上述技術問題，本發明採用的技術方案為：一種光學路徑可控高導熱、低電阻DBR對疊層的VCSEL製作方法，包括以下步驟：將一MQW層上方的主要DBR AlxiGa1-xiAs/AlyGa1-yAs(xi>y，0

Figure 111138070-A0305-02-0003-5
y
Figure 111138070-A0305-02-0003-6
1，且xi由上至下逐漸變大)中高Al%組分AlxiGa1-xiAs中的週邊部分進行完全氧化，使其轉變成Al2O3，在所需的光學路徑上形成一AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構並使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構從上至下逐漸變窄，同時通過控制較臨近MQW的低Al%組分AlzGa1-zAs的氧化速率，繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，其中Al%組分滿足z>xi>y；將週邊部分完全氧化所形成的Al2O3以化學蝕刻方式去除，保留光學路徑的AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構；及 去除週邊部分的Al2O3所形成的空間以原子層沉積、濺鍍、蒸鍍及電鍍中的一種或多種組合方式填充歐姆金屬，以形成低電阻的電學導通路徑。 In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for manufacturing a VCSEL with a controllable optical path, high thermal conductivity, and low resistance DBR stack, comprising the following steps: placing a main DBR Al xi Ga 1-xi As/Al y Ga 1-y As (xi>y, 0
Figure 111138070-A0305-02-0003-5
y
Figure 111138070-A0305-02-0003-6
1, and xi gradually increases from top to bottom) in the peripheral part of the high Al% component Al xi Ga 1-xi As is completely oxidized to convert it into Al 2 O 3 , forming an Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure on the required optical path and making the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure gradually narrow from top to bottom. At the same time, by controlling the oxidation rate of the low Al% component Al z Ga 1-z As close to the MQW, the size of the current aperture of the central unoxidized Al z Ga 1-z As is controlled, wherein the Al% component satisfies z>xi>y; the Al 2 O 3 formed by the complete oxidation of the peripheral part is removed by chemical etching, and the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure of the optical path is retained. 1-xi As/Al y Ga 1-y As DBR stacking structure; and the space formed by removing the peripheral Al 2 O 3 is filled with ohmic metal by one or more combinations of atomic layer deposition, sputtering, evaporation and electroplating to form a low-resistance electrical conduction path.

進一步的，還包括之前的外延成長、平臺蝕刻/上電極製作。 Furthermore, it also includes the previous epitaxial growth, platform etching/upper electrode fabrication.

進一步的，還包括在去除週邊部分的Al2O3之前通過光阻保護MQW臨近Al2O3。 Furthermore, the method further includes protecting the MQW near Al 2 O 3 by using a photoresist before removing the peripheral portion of Al 2 O 3 .

進一步的，除週邊部分的Al2O3採用蝕刻工藝。 Furthermore, the Al 2 O 3 except the peripheral portion is subjected to an etching process.

進一步的，還包括之後的二次檯面蝕刻、下電極製作、介電層塗布及焊墊蒸鍍。 Furthermore, it also includes the subsequent secondary surface etching, bottom electrode manufacturing, dielectric layer coating and pad evaporation.

本發明的有益效果在於：通過氧化高Al%組分AlxiGa1-xiAs形成該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構，通過控制氧化速率，使得光學路徑可控，通過使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構由上至下逐漸變窄，形成一個敞口型，更加方便電流通過；且通過控制低Al%組分AlzGa1-zAs的氧化速率繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，從而控制整個電流通道，使得電流通道可控。以歐姆金屬作為電流局限層取代現有的Al2O3，降低了電阻並且提高了導熱能力。 The beneficial effects of the present invention are: the Al xi Ga 1-xi As /Al y Ga 1-y As DBR stacking structure is formed by oxidizing the high Al% component Al xi Ga 1-xi As, and the optical path is controllable by controlling the oxidation rate, and the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure is gradually narrowed from top to bottom to form an open type, which is more convenient for current to pass; and the oxidation rate of the low Al% component Al z Ga 1-z As is controlled to control the size of the central unoxidized Al z Ga 1-z As current aperture, thereby controlling the entire current channel, making the current channel controllable. Ohm metal is used as a current confinement layer to replace the existing Al 2 O 3 , which reduces the resistance and improves the thermal conductivity.

1:VCSEL 1:VCSEL

10:襯底 10: Lining

11:下DBR層 11: Lower DBR layer

12:MQW層 12:MQW layer

13:上DBR層 13: Upper DBR layer

130:歐姆金屬填充 130: Ohm metal filling

14:上電極 14: Upper electrode

15:光阻 15: Photoresist

16:電極接觸層 16: Electrode contact layer

17:下電極 17: Lower electrode

2:外延結構 2: Epitaxial structure

20:一次蝕刻檯面 20: Etch the countertop once

21:二次蝕刻檯面 21: Secondary etching of the table surface

(a)~(g):步驟 (a)~(g): Steps

圖1是本發明實施例一種光學路徑可控高導熱、低電阻的VCSEL製作方法及VCSEL的在AlyGa1-yAs中y=0時的工藝結構流程示意圖；圖2是本發明實施例一種光學路徑可控高導熱、低電阻的VCSEL製作方法及VCSEL的流程示意圖。 FIG1 is a method for manufacturing a VCSEL with controllable optical path, high thermal conductivity and low resistance and a schematic diagram of the process structure flow of the VCSEL when y=0 in AlyGa1 -yAs according to an embodiment of the present invention; FIG2 is a method for manufacturing a VCSEL with controllable optical path, high thermal conductivity and low resistance and a schematic diagram of the process flow of the VCSEL according to an embodiment of the present invention.

為了使本發明的目的、技術方案及優點更加清楚明白，以下結合附圖及實施例，對本發明一種光學路徑可控高導熱、低電阻的VCSEL製作方法及VCSEL進行進一步詳細說明。應當理解，此處所描述的具體實施例僅用以解釋本發明，並不用於限定本發明。 In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following is a further detailed description of a VCSEL manufacturing method with controllable optical path, high thermal conductivity and low resistance and a VCSEL in combination with the attached figures and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

請參照圖1-圖2，一種光學路徑可控高導熱、低電阻DBR對疊層的VCSEL 1製作方法，包括以下步驟：將一MQW層12上方的主要DBR AlxiGa1-xiAs/AlyGa1-yAs(xi>y，0

Figure 111138070-A0305-02-0005-7
y
Figure 111138070-A0305-02-0005-8
1，且xi由上至下逐漸變大)中高Al%組分AlxiGa1-xiAs的部分進行完全氧化，使其轉變成Al2O3，在所需的光學路徑上形成一AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構並使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構從上至下逐漸變窄，同時通過控制較臨近MQW的低Al%組分AlzGa1-zAs的氧化速率，繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，其中Al%組分滿足z>xi>y；將週邊部分完全氧化所形成的Al2O3以化學蝕刻方式去除，保留光學路徑的AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構；及去除週邊部分的Al2O3所形成的空間以原子層沉積、濺鍍、蒸鍍及電鍍中的一種或多種組合方式填充歐姆金屬，以形成低電阻的電學導通路徑。 Referring to FIG. 1-2, a method for manufacturing a VCSEL 1 with a controllable optical path and a high thermal conductivity and low resistance DBR stack includes the following steps: placing a main DBR Al xi Ga 1-xi As/Al y Ga 1-y As (xi>y, 0
Figure 111138070-A0305-02-0005-7
y
Figure 111138070-A0305-02-0005-8
1, and xi gradually increases from top to bottom) is completely oxidized to convert the high Al% component Al xi Ga 1-xi As into Al 2 O 3 , forming an Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure on the desired optical path and making the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure gradually narrow from top to bottom. At the same time, by controlling the oxidation rate of the low Al% component Al z Ga 1-z As close to the MQW, the size of the current aperture of the central unoxidized Al z Ga 1-z As is controlled, wherein the Al% component satisfies z>xi>y; the Al 2 O 3 formed by the complete oxidation of the peripheral part is removed by chemical etching, retaining the Al xi Ga 1-xi As/Al y Ga 1-y As of the optical path. y Ga 1-y As DBR stacking structure; and the space formed by removing the peripheral Al 2 O 3 is filled with ohmic metal by one or more combinations of atomic layer deposition, sputtering, evaporation and electroplating to form a low-resistance electrical conduction path.

通過氧化高Al%組分AlxiGa1-xiAs形成AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構，通過控制氧化速率，使得光學路徑可控，通過使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構由上至下逐漸變窄，形成一個敞口型，更加方便電流通過；且通過控制低Al%組分AlzGa1-zAs的氧化速率繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，從而控制整個電流通道，使得電流通道可控，由於整個電流通道通過控制形成了一個近似漏斗的形狀，可以更好地方便電流通過。以歐姆金屬作為電流局限層取代現有的Al2O3，降低了電阻並且提高了導熱能力。可以理解的，xi由上至下逐漸變大，即Al%由上到下逐漸變大，藉以控制中心光電學路徑的幾何形狀。 By oxidizing the high Al% component Al xi Ga 1-xi As to form an Al xi Ga 1-xi As/ Aly Ga 1-y As DBR stacking structure, the optical path is controllable by controlling the oxidation rate, and the Al xi Ga 1-xi As/ Aly Ga 1-y As DBR stacking structure is gradually narrowed from top to bottom to form an open type, which is more convenient for current to pass; and by controlling the oxidation rate of the low Al% component Al z Ga 1-z As, the size of the current aperture of the central unoxidized Al z Ga 1-z As is controlled, thereby controlling the entire current channel, making the current channel controllable. Since the entire current channel is controlled to form a funnel-like shape, it can better facilitate the passage of current. Ohm metal is used as a current confinement layer to replace the existing Al 2 O 3 , which reduces the resistance and improves the thermal conductivity. It can be understood that xi gradually increases from top to bottom, that is, Al% gradually increases from top to bottom, so as to control the geometry of the central optoelectronic path.

進一步的，還包括之前的外延成長、平臺蝕刻/上電極製作。 Furthermore, it also includes the previous epitaxial growth, platform etching/upper electrode fabrication.

進一步的，還包括在去除週邊部分的Al2O3之前通過光阻保護MQW臨近Al2O3。 Furthermore, the method further includes protecting the MQW near Al 2 O 3 by using a photoresist before removing the peripheral portion of Al 2 O 3 .

進一步的，除週邊部分的Al2O3採用蝕刻工藝。即可以根據需要選用濕法蝕刻或幹法蝕刻工藝進行。 Furthermore, the Al 2 O 3 in the peripheral part is etched by a wet etching process or a dry etching process as required.

進一步的，還包括之後的二次檯面蝕刻、下電極製作、介電層塗布及焊墊蒸鍍。 Furthermore, it also includes the subsequent secondary surface etching, bottom electrode manufacturing, dielectric layer coating and pad evaporation.

可以理解的，整體流程依次包括：(a)外延成長，形成一外延結構2，一般主要包括一上DBR層13、一MQW層12、一下DBR層11和一襯底10；(b)一次平臺蝕刻/上電極製作，一次平臺蝕刻使該上DBR層13形成一一次蝕刻檯面20，上電極製作即在該一次蝕刻檯面20上形成複數個上電極14，一般可採用蒸鍍的方式形成電極；(c)氧化法形成HC-DBR(High contract conductivity-distributed Bragg reflectors，高折射率對比-分散式布拉格反射鏡)，即將該MQW層12上方的主要DBR AlxiGa1-xiAs/AlyGa1-yAs(x>y，0

Figure 111138070-A0305-02-0006-9
y
Figure 111138070-A0305-02-0006-10
1)中高Al%組分AlxiGa1-xiAs的部分進行完全氧化，使其轉變成Al2O3，在所需的光學路徑上形成該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構，並通過控制較臨近MQW的低Al%組分AlzGa1-zAs的氧化速率，繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，其中Al%組分滿足z>xi>y；(d)光阻保護MQW臨近Al2O3，即將該MQW層12上面、露出在該一次蝕刻檯面20外的Al2O3用光阻保護起來，一般可通過塗布工藝形成一光阻15，且化學蝕刻去除週邊Al2Q3，即將週邊部分完全氧化所形成的Al2O3以化學蝕刻方式去除，保留光學路徑的AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構並使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構從上至下逐漸變窄，同時通過控制較臨近該MQW層12的低Al%組分AlzGa1-zAs的氧化速率，繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小；(e)一歐姆金屬填充130，即通過以原子層沉積、濺 鍍、蒸鍍及電鍍中的一種或多種組合方式以原子層沉積、濺鍍、蒸鍍及電鍍中的一種或多種組合方式填充歐姆金屬以形成低電阻的電學導通路徑；(f)二次檯面蝕刻，即蝕刻該MQW層12下方、該襯底10上方的該下DBR層11部分，形成一二次蝕刻檯面21；(g)下電極製作，即在該二次蝕刻檯面21外的一電極接觸層16(該下DBR層11與該襯底10之間的部分)上形成一下電極17，且介電層塗布及焊墊蒸鍍。 As can be understood, the overall process includes: (a) epitaxial growth to form an epitaxial structure 2, which generally mainly includes an upper DBR layer 13, an MQW layer 12, a lower DBR layer 11 and a substrate 10; (b) a platform etching/upper electrode manufacturing, in which the upper DBR layer 13 is etched to form a primary etching table 20, and the upper electrode manufacturing is to form a plurality of upper electrodes 14 on the primary etching table 20, and the electrode can generally be formed by evaporation; (c) oxidation method to form HC-DBR (High contract conductivity-distributed Bragg reflectors, high refractive index contrast-distributed Bragg reflectors), that is, the main DBR Al xi Ga 1-xi As/Al y Ga 1-y As (x>y, 0
Figure 111138070-A0305-02-0006-9
y
Figure 111138070-A0305-02-0006-10
1) The Al xi Ga 1-xi As with a high Al% component is completely oxidized to be converted into Al 2 O 3 , forming the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure on the desired optical path, and by controlling the oxidation rate of the Al z Ga 1-z As with a low Al% component close to the MQW, the size of the current aperture of the central unoxidized Al z Ga 1-z As is controlled, wherein the Al% component satisfies z>xi>y; (d) Photoresist is used to protect the MQW close to Al 2 O 3 , i.e., the Al 2 O 3 on the MQW layer 12 and exposed outside the primary etching table 20 is protected by photoresist, which can generally be formed by a coating process to form a photoresist 15, and the peripheral Al 2 Q 3 is removed by chemical etching. That is, the Al 2 O 3 formed by the complete oxidation of the peripheral part is removed by chemical etching, the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure of the optical path is retained and the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure is gradually narrowed from top to bottom. At the same time, by controlling the oxidation rate of the low Al% component Al z Ga 1-z As close to the MQW layer 12, the unoxidized Al z Ga 1-z As in the center is controlled. As the size of the current aperture; (e) an ohmic metal filling 130, that is, filling the ohmic metal by one or more combinations of atomic layer deposition, sputtering, evaporation and electroplating to form a low-resistance electrical conduction path; (f) secondary surface etching, that is, etching the A secondary etching table 21 is formed on the portion of the lower DBR layer 11 below the MQW layer 12 and above the substrate 10; (g) a lower electrode is fabricated, i.e., a lower electrode 17 is formed on an electrode contact layer 16 (the portion between the lower DBR layer 11 and the substrate 10) outside the secondary etching table 21, and a dielectric layer is coated and a pad is evaporated.

明顯地，每一對AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊層的厚度滿足諧振腔λ/2neff的要求，其中λ為雷射器主要放射波長、neff為該波長在每對DBR堆疊層的等效折射率。 Obviously, the thickness of each pair of Al xi Ga 1-xi As/ Aly Ga 1-y As DBR stack layers meets the requirement of the resonance cavity λ/2n eff , where λ is the main emission wavelength of the laser and n eff is the equivalent refractive index of the wavelength in each pair of DBR stack layers.

本發明還提供一種光學路徑可控、高導熱、低電阻的VCSEL 1，包括該襯底10、該電極接觸層16、該下DBR層11、該MQW層12、該上DBR層13，其中，該上DBR層13內的光學路徑上的堆疊結構由下至上逐漸變大，該堆疊結構的兩側填充有歐姆金屬。 The present invention also provides a VCSEL 1 with controllable optical path, high thermal conductivity and low resistance, comprising the substrate 10, the electrode contact layer 16, the lower DBR layer 11, the MQW layer 12, and the upper DBR layer 13, wherein the stacking structure on the optical path in the upper DBR layer 13 gradually increases from bottom to top, and both sides of the stacking structure are filled with ohmic metal.

進一步的，在該MQW層12上方的設有電流孔徑，該電流孔徑的外徑小於該堆疊結構的外徑。即該堆疊結構的外徑大於該電流孔徑的外徑，形成漏斗形狀，使得電流能夠更方便地進入電流孔徑內，從而提高效率。 Furthermore, a current aperture is provided above the MQW layer 12, and the outer diameter of the current aperture is smaller than the outer diameter of the stacked structure. That is, the outer diameter of the stacked structure is larger than the outer diameter of the current aperture, forming a funnel shape, so that the current can enter the current aperture more conveniently, thereby improving efficiency.

進一步的，該堆疊結構的光學路徑由AlxiGa1-xiAs/AlyGa1-yAs形成。 Furthermore, the optical path of the stacked structure is formed by Al xi Ga 1-xi As/ Aly Ga 1-y As.

可以理解的，VCSEL即垂直腔面發射雷射器(Vertical-Cavity Surface-Emitting Laser，簡稱VCSEL，又譯垂直共振腔面射型鐳射)；MQW即Multiple Quantum Well，多量子阱；ALD即Atomic layer deposition，原子層沉積；DBR即Distributed Bragg Reflector，分佈時布拉格反射鏡。Al即鋁，Ga即鎵，As即砷，Al2O3即氧化鋁泛指VCSEL結構中AlGaAs經氧化而得以Al2O3為主而含有少量的的Ga2O3、GaAs或AlAs的混合物。 As you can understand, VCSEL stands for Vertical-Cavity Surface-Emitting Laser (VCSEL), MQW stands for Multiple Quantum Well, ALD stands for Atomic layer deposition, and DBR stands for Distributed Bragg Reflector. Al stands for aluminum, Ga stands for gallium, As stands for arsenic, and Al 2 O 3 stands for aluminum oxide, which refers to the AlGaAs in the VCSEL structure that is oxidized to Al 2 O 3 as the main component and contains a small amount of Ga 2 O 3 , GaAs or AlAs.

需要說明，若本發明實施例中有涉及方向性指示(諸如上、下、左、右、前、後……)，則該方向性指示僅用於解釋在某一特定姿態(如附圖所示)下各部件之間的相對位置關係、運動情況等，如果該特定姿態發生改變時，則該方向性指示也相應地隨之改變。 It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention, the directional indications are only used to explain the relative position relationship and movement status of the components under a certain specific posture (as shown in the attached figure). If the specific posture changes, the directional indication will also change accordingly.

綜上所述，本發明提供的一種光學路徑可控高導熱、低電阻的VCSEL製作方法及VCSEL，通過氧化高Al%組分AlxiGa1-xiAs形成該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構，通過控制氧化速率，使得光學路徑可控，通過使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構由上至下逐漸變窄，形成一個敞口型，更加方便電流通過；且通過控制低Al%組分AlzGa1-zAs的氧化速率繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，從而控制整個電流通道，使得電流通道可控。以歐姆金屬作為電流局限層取代現有的Al2O3，降低了電阻並且提高了導熱能力。 In summary, the present invention provides a method for manufacturing a VCSEL with controllable optical path, high thermal conductivity and low resistance, and a VCSEL, which forms the AlxiGa1 -xiAs / AlyGa1 -yAs DBR stacked structure by oxidizing the high Al% component AlxiGa1 - xiAs , and controls the oxidation rate to make the optical path controllable. The AlxiGa1 -xiAs/ AlyGa1 -yAs DBR stacked structure is gradually narrowed from top to bottom to form an open type, which is more convenient for current flow. The oxidation rate of the low Al% component AlzGa1 -zAs is controlled to control the size of the current aperture of the central unoxidized AlzGa1 -zAs , thereby controlling the entire current channel, making the current channel controllable. Using ohm metal as the current confinement layer instead of the existing Al 2 O 3 reduces the electrical resistance and improves the thermal conductivity.

以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本專業的技術人員，在不脫離本發明技術方案範圍內，當可利用上述揭示的技術內容做出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。 The above is only the preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as the preferred embodiment, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes by using the above disclosed technical contents within the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

1:VCSEL 1:VCSEL

10:襯底 10: Lining

11:下DBR層 11: Lower DBR layer

12:MQW層 12:MQW layer

13:上DBR層 13: Upper DBR layer

130:歐姆金屬填充 130: Ohm metal filling

14:上電極 14: Upper electrode

15:光阻 15: Photoresist

16:電極接觸層 16: Electrode contact layer

17:下電極 17: Lower electrode

2:外延結構 2: Epitaxial structure

20:一次蝕刻檯面 20: Etch the countertop once

21:二次蝕刻檯面 21: Secondary etching of the table surface

(a)~(g):步驟 (a)~(g): Steps

Claims (5)

一種光學路徑可控高導熱、低電阻DBR對疊層的VCSEL製作方法，其特徵在於，包括以下步驟：將一MQW層上方的主要DBR AlxiGa1-xiAs/AlyGa1-yAs(xi>y，0
Figure 111138070-A0305-02-0010-11
y
Figure 111138070-A0305-02-0010-13
1，且xi由上至下逐漸變大)中高Al%組分AlxiGa1-xiAs中的週邊部分進行完全氧化，使其轉變成Al2O3，在所需的光學路徑上形成一AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構並使該AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構從上至下逐漸變窄，同時通過控制較臨近MQW的低Al%組分AlzGa1-zAs的氧化速率，繼而控制中心未被氧化的AlzGa1-zAs電流孔徑的大小，其中Al%組分滿足z>xi>y；將週邊部分完全氧化所形成的Al2O3以化學蝕刻方式去除，保留光學路徑的AlxiGa1-xiAs/AlyGa1-yAs DBR堆疊結構；及去除週邊部分的Al2O3所形成的空間以原子層沉積、濺鍍、蒸鍍及電鍍中的一種或多種組合方式填充歐姆金屬，以形成低電阻的電學導通路徑。 A method for manufacturing a VCSEL with a controllable optical path and high thermal conductivity and low resistance DBR stack, comprising the following steps: placing a main DBR Al xi Ga 1-xi As/Al y Ga 1-y As (xi>y, 0
Figure 111138070-A0305-02-0010-11
y
Figure 111138070-A0305-02-0010-13
1, and xi gradually increases from top to bottom) in the peripheral part of the high Al% component Al xi Ga 1-xi As is completely oxidized to convert it into Al 2 O 3 , forming an Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure on the required optical path and making the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure gradually narrow from top to bottom. At the same time, by controlling the oxidation rate of the low Al% component Al z Ga 1-z As close to the MQW, the size of the current aperture of the central unoxidized Al z Ga 1-z As is controlled, wherein the Al% component satisfies z>xi>y; the Al 2 O 3 formed by the complete oxidation of the peripheral part is removed by chemical etching, and the Al xi Ga 1-xi As/Al y Ga 1-y As DBR stacking structure of the optical path is retained. 1-xi As/Al y Ga 1-y As DBR stacking structure; and the space formed by removing the peripheral Al 2 O 3 is filled with ohmic metal by one or more combinations of atomic layer deposition, sputtering, evaporation and electroplating to form a low-resistance electrical conduction path. 如請求項1所述之光學路徑可控高導熱、低電阻DBR對疊層的VCSEL製作方法，其中，還包括之前的外延成長、平臺蝕刻/上電極製作。 A method for manufacturing a VCSEL with a controllable optical path, high thermal conductivity, and low resistance DBR stack as described in claim 1, which also includes the previous epitaxial growth, platform etching/upper electrode manufacturing. 如請求項1所述之光學路徑可控高導熱、低電阻DBR對疊層的VCSEL製作方法，其中，還包括在去除週邊部分的Al2O3之前通過光阻保護MQW臨近Al2O3。 The method for manufacturing a VCSEL with a controllable optical path, high thermal conductivity, and low resistance DBR stack as described in claim 1, further comprising protecting the MQW near Al 2 O 3 by using a photoresist before removing the peripheral portion of Al 2 O 3 . 如請求項1所述之光學路徑可控高導熱、低電阻DBR對疊層的VCSEL製作方法，其中，除週邊部分的Al2O3採用蝕刻工藝。 A method for manufacturing a VCSEL with a stack of DBR layers with controllable optical path, high thermal conductivity and low resistance as described in claim 1, wherein the Al 2 O 3 except the peripheral portion is etched using an etching process. 如請求項1所述之光學路徑可控高導熱、低電阻DBR對疊層的VCSEL製作方法，其中，還包括之後的二次檯面蝕刻、下電極製作、介電層塗布及焊墊蒸鍍。 A method for manufacturing a VCSEL with a controllable optical path, high thermal conductivity, and low resistance DBR stack as described in claim 1, which also includes subsequent secondary surface etching, bottom electrode manufacturing, dielectric layer coating, and pad evaporation.
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