CN120006216A

CN120006216A - VCSEL device and method for manufacturing the same

Info

Publication number: CN120006216A
Application number: CN202510165826.1A
Authority: CN
Inventors: 韦晚霞; 严进一; 鲍辉; 方瑞禹
Original assignee: Shanghai Xinwei Semiconductor Co ltd
Current assignee: Shanghai Xinwei Semiconductor Co ltd
Priority date: 2025-02-14
Filing date: 2025-02-14
Publication date: 2025-05-16

Abstract

The invention provides a VCSEL device and a preparation method thereof. The preparation method of the VCSEL device comprises the step of forming a second seed layer by adopting a mode of combining a sputtering process and an evaporation process. The second seed layer with the second thickness formed based on the evaporation process is large in grain size, small in number of grain boundaries and disordered in grain boundary direction, and can reduce the lateral corrosion rate in the wet corrosion process, so that the problem of cavities caused by lateral corrosion is effectively solved, the luminous efficiency of the VCSEL device is ensured, and meanwhile, the reliability and the service life of the device are improved.

Description

VCSEL device and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a VCSEL device and a preparation method thereof.

Background

A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser with a lasing direction perpendicular to the plane of the PN junction. VCSEL has advantages of easy integration, good beam quality, high modulation bandwidth, long service life, single-mode output, etc., and is widely applied to the fields of communication, medical treatment, industrial processing, safety protection, etc.

Referring to fig. 1, the process of preparing a P-side electrode structure by using a conventional VCSEL mainly includes forming a TiW layer 101 and an Au layer 102 as seed layers on an epitaxial structure 100 by sequentially using a sputtering process. Then, a patterned photoresist layer is formed on the seed layer, and in turn, an electroplated Au layer 103 is formed on the seed layer using an electroplating process for blocking. Next, a protective layer 104 is sputtered on the Au plating layer 103, and the material may be TiW. Finally, photoresist is removed and non-contact areas in the seed layer are etched away. Wherein the etching of the seed layer may be divided into two steps. As shown in fig. 2, the first step is to etch the Au layer 102 in the seed layer, and in this step, in addition to etching the longitudinal surface of the Au layer 102, lateral etching occurs in the Au layer 102 and the Au layer 103, thereby resulting in the P-side electrode structure having an inverted "T" shape. As shown in fig. 3 and 4, the second step is etching the TiW layer 101 in the seed layer, i.e., a second etching. And in this step, the exposed portion of the TiW layer 101 is removed, and the protective layer 104 is also removed. And, the TiW layer 101 may also suffer from lateral corrosion, which may result in the formation of voids C on the sides of the seed layer. The presence of the cavity C is detrimental to the adequate coverage of the dielectric film on the metal surface, thereby severely affecting the lifetime and reliability of the VCSEL.

In order to solve the problem of lateral corrosion, the prior art generally adopts two schemes, namely, a first scheme is to prepare a corrosive liquid for simultaneously corroding the TiW layer 101 and the Au layer 102, and the depth of lateral corrosion is reduced by one-time corrosion. The second scheme is that a barrier layer and a dry etching TiW layer 101 are formed, and the directionality of dry etching is utilized to avoid secondary lateral corrosion generated by wet etching the TiW layer 101, so that the depth of a cavity C is relieved. However, the first solution is easy to cause corrosion residue by one-time corrosion and has poor removal effect. And the second scheme has limited effect of improving the depth of the cavity C, and the process is complicated.

Therefore, a new method for fabricating a VCSEL device is needed to solve the above technical problems.

Disclosure of Invention

The invention aims to provide a VCSEL device and a preparation method thereof, which are used for solving at least one problem of how to relieve lateral corrosion and how to improve the performance of the VCSEL device in the process of preparing a P-surface electrode structure of the VCSEL device.

In order to solve the above technical problems, the present invention provides a method for manufacturing a VCSEL device, including:

The method comprises the steps of providing an epitaxial structure, and sequentially sputtering a first seed layer and a second seed layer with a first thickness on the epitaxial structure;

Forming a second seed layer with a second thickness on the second seed layer with the first thickness by adopting an evaporation process;

Forming a patterned metal layer on the second seed layer having the second thickness;

forming a protective layer on the surface of the patterned metal layer;

Removing the exposed part of the second seed layer by adopting a first wet etching process;

And removing the exposed parts of the first seed layer and the protective layer by adopting a second wet etching process.

Optionally, in the method for manufacturing a VCSEL device, the first thickness is smaller than the second thickness.

Optionally, in the method for manufacturing a VCSEL device, the material of the first seed layer includes TiW, and the thickness range is 40nm to 80nm.

Optionally, in the method for manufacturing a VCSEL device, the material of the second seed layer includes Au, the first thickness ranges from 5nm to 20nm, and the second thickness ranges from 60nm to 150nm.

Optionally, in the method for manufacturing a VCSEL device, the forming a patterned metal layer on the second seed layer having the second thickness includes:

The second seed layer is provided with a contact area and a non-contact area, and a patterned photoresist layer is formed on the second seed layer so as to shield the non-contact area and expose the contact area;

and forming the patterned metal layer on the surface of the contact area by adopting an electroplating process by taking the patterned photoresist layer as a barrier.

Optionally, in the method for manufacturing a VCSEL device, the patterned metal layer is made of Au, and the thickness of the patterned metal layer ranges from 1 μm to 3 μm.

Optionally, in the preparation method of the VCSEL device, a sputtering process is adopted to form the protective layer on the patterned metal layer, and after the protective layer is formed, the patterned photoresist layer is removed;

the material of the protective layer comprises TiW, and the thickness range is 20 nm-50 nm.

Optionally, in the preparation method of the VCSEL device, the etching solution used in the first wet etching process includes I ₂, KI and H ₂ O, and the etching time range is 30 s-60 s, and the etching solution used in the second wet etching process includes H ₂O₂, and the etching time range is 120 s-180 s.

Optionally, in the method for manufacturing a VCSEL device, after removing the exposed portions of the first seed layer and the protective layer by using a second wet etching process, the method for manufacturing a VCSEL device further includes:

An electrode structure is formed on a side of the epitaxial structure remote from the first seed layer.

Based on the same conception, the invention also provides a VCSEL device, and the VCSEL device is prepared by adopting the preparation method of the VCSEL device.

In summary, the present invention provides a VCSEL device and a method for fabricating the same. Compared with the prior art, the preparation method of the VCSEL device adopts a mode of combining a sputtering process and an evaporation process to form the second seed layer. The second seed layer with the second thickness formed based on the evaporation process is large in grain size, small in number of grain boundaries and disordered in grain boundary direction, and can reduce the lateral corrosion rate in the wet corrosion process, so that the problem of cavities caused by lateral corrosion is effectively solved, the luminous efficiency of the VCSEL device is ensured, and meanwhile, the reliability and the service life of the device are improved.

Drawings

Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

Fig. 1 is a schematic diagram of a prior art semiconductor structure prior to etching of a P-side electrode structure.

Fig. 2 is a schematic diagram of a prior art semiconductor structure after etching an Au layer in a seed layer.

FIG. 3 is a schematic diagram of a prior art semiconductor structure in which voids are formed after etching a TiW layer in a seed layer.

Fig. 4 is an SEM photograph of a semiconductor structure in which deeper voids are formed in a P-side electrode structure according to the prior art.

Fig. 5 is a flowchart of a method for fabricating a P-side electrode structure of a VCSEL device in an embodiment of the present invention.

Fig. 6 is a flow chart of a method of fabricating an epitaxial structure of a VCSEL device in an embodiment of the present invention.

Fig. 7 to 17 and 19 are schematic diagrams of semiconductor structures corresponding to steps in a method for fabricating a VCSEL device according to an embodiment of the present invention.

Fig. 18 is an SEM photograph of a semiconductor structure in which a shallower cavity is formed in a P-side electrode structure according to an embodiment of the present invention.

And, in the drawings:

100-epitaxial structure, 101-TiW layer, 102-Au layer, 103-electroplated Au layer, 104-protective layer and C-cavity;

200-substrate, 201-N side bragg reflective layer, 202-N side confinement layer, 203-active layer, 204-P side confinement layer, 205-oxide confinement material layer, 205 a-oxide, 205 b-oxide confinement window, 206-P side bragg reflective layer, 207-contact layer, 208-first patterned photoresist layer, 209-passivation layer, 210-first seed layer, 211-second seed layer having a first thickness, 212-second seed layer having a second thickness, 213-second patterned photoresist layer, 214-patterned metal layer, 215-protective layer, 216-N side electrode structure.

Detailed Description

The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments. It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.

Referring to fig. 5, the present embodiment provides a method for manufacturing a VCSEL device, including:

step S10, providing an epitaxial structure, and sequentially sputtering a first seed layer and a second seed layer with a first thickness on the epitaxial structure;

step S20, forming a second seed layer with a second thickness on the second seed layer with the first thickness by adopting an evaporation process;

Step three S30, forming a patterned metal layer on the second seed layer having the second thickness;

Step four, S40, forming a protective layer on the surface of the patterned metal layer;

Step five S50, removing the exposed part of the second seed layer by adopting a first wet etching process;

and step six, adopting a second wet etching process to remove the exposed parts of the first seed layer and the protective layer.

Based on this, in the method for manufacturing a VCSEL device according to the present embodiment, the second seed layer is formed by a combination of a sputtering process and an evaporation process when the P-surface electrode structure is manufactured. And the second seed layer with the second thickness formed based on the evaporation process has large grain size, small grain boundary number and disordered grain boundary direction, and can reduce the lateral corrosion rate in the wet corrosion process, so that the cavity problem caused by the lateral corrosion is effectively relieved, and the reliability and the service life of the VCSEL device are improved while the luminous efficiency of the VCSEL device is ensured.

The following specifically describes a method for manufacturing the VCSEL device according to the present embodiment with reference to fig. 5 to 19.

In step S10, referring to FIGS. 6-11, an epitaxial structure is provided, and a first seed layer 210 and a second seed layer 211 having a first thickness are sequentially formed on the epitaxial structure by sputtering.

It should be noted that the existing VCSEL devices may be classified into various types, and the preparation method provided in this embodiment may be applicable to the preparation of any VCSEL device. In addition, since the epitaxial structures of different types of VCSEL devices are slightly different in preparation process, the oxidation-limited VCSEL device is taken as an example in this embodiment, and the preparation process of the epitaxial structures is specifically described:

In a substep S101, referring to fig. 7, a substrate 200 is provided.

Alternatively, the material of the substrate 200 includes, but is not limited to, gaAs.

In the second substep S102, referring to fig. 7, an N-side bragg reflector (Distributed Bragg Reflector, DBR) 201, an N-side confinement layer 202, an active layer 203, a P-side confinement layer 204, an oxidation confinement material layer 205, a P-side bragg reflector 206, and a contact layer 207 are sequentially formed on the substrate 200.

Further, the N-side bragg reflective layer 201 and the P-side bragg reflective layer 206 form a resonant cavity of the VCSEL device. And the DBR is a film system formed by stacking two materials with 1/4 wavelength optical thickness and different refractive indexes, and the two materials are alternately overlapped according to a high refractive index and a low refractive index. When the optical path difference between the two DBR reflectors is an integral multiple of the wavelength, the light generates in-phase interference enhancement in the resonant cavity, and continuously oscillates in the cavity, and finally the laser output can be formed when the gain is larger than the loss. Optionally, the N-side bragg reflective layer 201 and the P-side bragg reflective layer 206 include, but are not limited to, alGaAs and AlAs that are periodically stacked.

The N-plane confinement layer 202 and the P-plane confinement layer 204 are both separate confinement heterostructures (Separate Confinement Heterostructure, SCH) and are respectively disposed on opposite sides of the active layer 203 for limiting carrier overflow and adjusting beam quality. Optionally, the material of the N-plane confinement layer 202 and the P-plane confinement layer 204 includes, but is not limited to, alGaAs. And the active layer 203 includes a plurality of quantum wells, and the quantum wells are alternately grown of semiconductor materials of two different bandgaps, so as to enable electrons and holes to recombine in the quantum wells and emit photons. Alternatively, the materials of the quantum well include, but are not limited to, inGaAs and AlGaAs. And, the oxidation limiting material layer 205 is generally made of high-alumina material, so that an oxidation limiting window can be formed under the oxidation effect, and the current and the optical field can be limited. The contact layer 207 is located on the top surface of the P-surface bragg reflection layer 206, which is not only beneficial to forming an electrical connection with a P-surface electrode structure formed subsequently, but also can protect the substrate 200 and other film layers from being corroded in subsequent processes. Optionally, the material of the contact layer 207 includes, but is not limited to, gaAs.

In a third step S103, referring to fig. 8, a first patterned photoresist layer 208 is formed on the surface of the contact layer 207, and the contact layer 207, the P-surface bragg reflection layer 206, the oxidation limiting material layer 205, the P-surface limiting layer 204, the active layer 203 and the N-surface limiting layer 202 are etched in sequence with the first patterned photoresist layer 208 as a barrier to expose a portion of the surface of the N-surface bragg reflection layer 201 and form a mesa structure of the VCSEL device.

Optionally, a dry and/or wet etching process is used for mesa etching. The purpose of the mesa etching is that, on one hand, the side surface of the oxidation limiting material layer 205 can be exposed through etching so as to form an oxidation limiting window later, so that the current and light field can be limited, on the other hand, the size and shape of the mesa can be precisely controlled through etching, the laser output can be precisely controlled, the side wall morphology of the VCSEL device can be improved through etching, scattering and reflection can be reduced, the light extraction efficiency can be improved, and the device performance can be optimized. Further, after mesa etching, the first patterned photoresist layer 208 is removed.

In a fourth sub-step S104, referring to fig. 8, 9 and 10, a wet oxidation process is performed to oxidize both sides of the oxidation limiting material layer 205 and form an oxidation limiting window 205b in the middle.

As can be seen from the above, after the mesa etching, the side walls of the oxidation limiting material layer 205 are exposed, and then the semiconductor structure is placed in an oxidation furnace with a high-temperature vapor environment to perform wet oxidation treatment, so that the portions of the structure, which are oriented to the center, of the two sides of the oxidation limiting material layer 205 are oxidized to form the oxide 205a. And stopping the continuous oxidation after reaching the preset wet oxidation process time, and forming a passivation layer 209 on the surface of the semiconductor structure to prevent further oxidation. Optionally, the passivation layer 209 may be made of SiN _x, where x is a positive integer.

As shown in fig. 9 and 10, both sides of the oxidation limiting material layer 205 are oxidized to form the oxide 205a, while the central region is not oxidized for use as the oxidation limiting window 205b. The material of the oxide 205a is mainly Al ₂O₃, which has the characteristics of low refractive index and high resistance, and can limit the optical field and current, and improve the device performance. The oxidation limiting window 205b helps to increase the side-mode suppression ratio of the VCSEL device, enabling a more stable single-mode laser output.

And the preparation of the epitaxial structure is completed based on the process. It should be noted that the above preparation process is only an exemplary illustration of the preparation of an epitaxial structure in an oxidation-limited VCSEL device, and the embodiment is not limited to a specific type of the epitaxial structure and a preparation method thereof.

Further, referring to fig. 11, after the epitaxial structure is formed, a P-side electrode structure needs to be formed on the contact layer 207. Therefore, it is necessary to remove a portion of the passivation layer 209 on the top surface of the contact layer 207 by a dry or wet etching process, and then sequentially form a first seed layer 210 and a second seed layer 211 having a first thickness on the surface of the contact layer 207 by a sputtering process. Optionally, the first seed layer 210 and the second seed layer 211 having the first thickness are conductive. The material of the first seed layer 210 includes but is not limited to TiW, and has a thickness ranging from 40nm to 80nm, for example, 40nm, 60nm or 80nm. The material of the second seed layer 211 includes Au, and the first thickness ranges from 5nm to 20nm, for example, from 5nm, 10nm, or 20nm.

The metal film formed by the sputtering process has ordered lattice structure, high density and good surface flatness. And the TiW material has good adhesion as the bottom layer of the seed layer, and under the action of the sputtering process, the connection tightness of the first seed layer 210 and the contact layer 207 can be improved, so that the device has better stability. The Au material has excellent conductivity and corrosion resistance, and the surface layer of the Au material serving as the second seed layer can improve the conductivity of the P-surface electrode structure. In this embodiment, a thin Au layer is formed on the surface of the first seed layer 210 by using a sputtering process, so that the process characteristics of the sputtering process are utilized to ensure that the two seed layers can be tightly connected, thereby giving consideration to the conductivity and stability of the device.

In step S20, referring to fig. 12, an evaporation process is used to form the second seed layer 212 with the second thickness on the second seed layer 211 with the first thickness.

It should be noted that the Au layer formed by the sputtering process has an ordered lattice structure, i.e., grains are regularly grown in a direction perpendicular to the substrate 200, and a columnar structure is formed. This results in a faster lateral corrosion rate of Au than in the longitudinal direction during wet etching, which causes cavitation problems due to lateral undercutting. In contrast, the Au layer formed by the evaporation process exhibits disorder in the grain boundary direction, and the grown grains have larger size and fewer grain boundaries. And, the corrosion rate of Au is greatly affected by the grain size, and the larger the grain size, the lower the corrosion rate. Based on this, in the subsequent wet etching process, the second seed layer 212 with the second thickness formed by the evaporation process is large in grain size and arranged in a disordered manner, so that the lateral etching rate can be effectively reduced, the problem of voids caused by lateral etching can be alleviated, and the performance of the device can be improved.

Therefore, in this embodiment, the first thickness is much smaller than the second thickness, so that most of the Au seed layer is formed through the evaporation process, so as to sufficiently alleviate the lateral corrosion problem of the Au seed layer. Optionally, the second thickness ranges from 60nm to 150nm, for example from 60nm,100nm or 150nm.

Referring to fig. 13 and 14, a patterned metal layer 214 is formed on the second seed layer 212 having the second thickness.

Since the seed layer has a contact region and a non-contact region, and the contact region is used to make electrical connection, the patterned metal layer 214 needs to be formed on the contact region. Specifically, the process of forming the patterned metal layer 214 includes, as shown in fig. 13, first forming a patterned photoresist layer (renamed as a second patterned photoresist layer 213 in this embodiment) on the second seed layer to block the non-contact region and expose the contact region. And forming the patterned metal layer 214 on the surface of the contact region by using the second patterned photoresist layer 213 as a barrier and adopting an electroplating process. Optionally, the patterned metal layer 214 may comprise Au and may have a thickness ranging from 1 μm to 3 μm, for example, 1 μm, 2 μm or 3 μm.

In step four S40, referring to fig. 14 and 15, a passivation layer 215 is formed on the surface of the patterned metal layer 214.

Specifically, the second patterned photoresist layer 213 is used as a barrier, and a sputtering process is used to form a protective layer 215 on the top surface of the patterned metal layer 214 and the top surface of the second patterned photoresist layer 213. Wherein the protective layer 215 is used to prevent longitudinal corrosion of the patterned metal layer 214 during subsequent corrosion of the second seed layer. Optionally, the material of the protective layer 215 includes TiW, and the thickness range is 20 nm-50 nm, for example, 20nm, 30nm or 50nm.

Further, after the protective layer 215 is formed by sputtering, the second patterned photoresist layer 213 is removed. At the same time, the portion of the protective layer 215 on the second patterned photoresist layer 213 is removed, and the portion of the protective layer 215 on the patterned metal layer 214 remains, as shown in fig. 15.

In step five, referring to fig. 16, a first wet etching process is used to remove the exposed portion of the second seed layer.

In step six, referring to fig. 17 and 18, a second wet etching process is used to remove the exposed portions of the first seed layer 210 and the protection layer 215.

Since the patterned metal layer 214 is formed on the contact region of the second seed layer, the non-contact region uncovered by the patterned metal layer 214 is exposed. And to remove the non-contact region, a first wet etching process may be used to remove the second seed layer in the non-contact region, and then a second wet etching process may be used to remove the first seed layer 210 in the non-contact region, and also remove the protection layer 215. And, after the two wet etching processes, the remaining first seed layer 210, the second seed layer and the patterned metal layer 214 form a P-plane electrode structure of the VCSEL device.

Optionally, the etching solution adopted in the first wet etching process includes, but is not limited to, I ₂, KI and H ₂ O, and the etching time range is 30 s-60 s. And the etching solution adopted in the second wet etching process comprises, but is not limited to, H ₂O₂ at 40 ℃, and the etching time range is 120 s-180 s.

Further, as can be seen from comparing fig. 4 and fig. 18, when the second seed layer is formed by sputtering, and after the two wet etching processes, the lateral etching of the TiW seed layer and the Au seed layer is serious, and the depth of the formed cavity C is about 780nm, the subsequently formed dielectric layer cannot completely cover the exposed Au, which seriously affects the device performance. And most of the structures in the second seed layer formed by the preparation method provided by the embodiment are formed by an evaporation process, so that the problem of lateral corrosion can be effectively relieved. Thus, after the first wet etching process, the remaining second seed layer has a lower lateral etching degree and a more regular morphology. And the lateral etching degree of the first seed layer 210 is also greatly reduced based on the barrier protection of the remaining second seed layer during the second wet etching process. Therefore, after the two wet etching processes, according to fig. 18, it can be intuitively seen that the lateral etching depth of the first seed layer 210 and the second seed layer is reduced by half, and the depth of the formed cavity C is only about 337nm, so that the subsequently formed dielectric layer can completely cover the Au seed layer, effectively preventing the intrusion of water vapor, and facilitating the subsequent device aging and reliability verification.

Further, as shown in fig. 19, after the P-side electrode structure is formed, the preparation method further includes thinning the back surface of the substrate 200, and then preparing an electrode structure, i.e., an N-side electrode structure 216, on the back surface of the substrate 200 by using an evaporation or sputtering process. The back surface of the substrate 200 refers to a side surface of the substrate 200 away from the N-surface bragg reflection layer 201. And after the N-side electrode structure 216 is formed, a thermal annealing process is performed to form a good ohmic contact between the metal and the semiconductor. And after the processes of detection, cutting, sorting, packaging and the like, the VCSEL device can be prepared and completed. For the process after the P-surface electrode structure is formed, the description of this embodiment is omitted here.

Based on the same concept, the present embodiment also provides a VCSEL device. Referring to fig. 19, the VCSEL device is fabricated by the above-described fabrication method of the VCSEL device.

In summary, the present embodiment provides a VCSEL device and a method for manufacturing the same. The preparation method of the VCSEL device comprises the step of forming the second seed layer by adopting a mode of combining a sputtering process and an evaporation process. The second seed layer with the second thickness formed based on the evaporation process is large in grain size, small in number of grain boundaries and disordered in grain boundary direction, and can reduce the lateral corrosion rate in the wet corrosion process, so that the cavity problem caused by the lateral corrosion is effectively relieved, the luminous efficiency of the VCSEL device is ensured, and meanwhile, the reliability and the service life of the device are improved.

It should also be appreciated that while the present invention has been disclosed in the context of a preferred embodiment, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for preparing a VCSEL device, comprising:

Providing an epitaxial structure; wherein a first seed layer and a second seed layer having a first thickness are sequentially sputtered on the epitaxial structure;

Using an evaporation process, forming the second seed layer having a second thickness on the second seed layer having the first thickness;

forming a patterned metal layer on the second seed layer having a second thickness;

forming a protective layer on the surface of the patterned metal layer;

Using a first wet etching process to remove the exposed portion of the second seed layer;

A second wet etching process is used to remove the exposed portions of the first seed layer and the protection layer.

2 . The method for preparing a VCSEL device according to claim 1 , wherein the first thickness is smaller than the second thickness.

3 . The method for preparing a VCSEL device according to claim 1 , wherein the first seed layer is made of TiW and has a thickness ranging from 40 nm to 80 nm.

4 . The method for preparing a VCSEL device according to claim 1 , wherein the material of the second seed layer comprises Au, and the first thickness ranges from 5 nm to 20 nm, and the second thickness ranges from 60 nm to 150 nm.

5. The method for preparing a VCSEL device according to claim 1, wherein the process of forming a patterned metal layer on the second seed layer having the second thickness comprises:

The second seed layer has a contact area and a non-contact area, and a patterned photoresist layer is formed on the second seed layer to shield the non-contact area and expose the contact area;

The patterned photoresist layer is used as a barrier and an electroplating process is adopted to form the patterned metal layer on the surface of the contact area.

6 . The method for preparing a VCSEL device according to claim 1 , wherein the material of the patterned metal layer comprises Au, and the thickness ranges from 1 μm to 3 μm.

7. The method for preparing a VCSEL device according to claim 5, characterized in that the protective layer is formed on the patterned metal layer by a sputtering process; and after the protective layer is formed, the patterned photoresist layer is removed;

Wherein, the material of the protection layer includes TiW, and the thickness ranges from 20nm to 50nm.

8. The method for preparing a VCSEL device according to claim 1, characterized in that the etching solution used in the first wet etching process comprises: _I2 , KI and _H2O , and the etching time ranges from: 30s to 60s; and the etching solution used in the second wet etching process comprises: _H2O2 , and the etching time ranges from: 120s to _180s .

9. The method for preparing a VCSEL device according to claim 1, characterized in that after removing the exposed portion of the first seed layer and the protective layer by a second wet etching process, the method for preparing a VCSEL device further comprises:

An electrode structure is formed on a side of the epitaxial structure away from the first seed layer.

10. A VCSEL device, characterized in that the VCSEL device is prepared by the method for preparing a VCSEL device according to any one of claims 1 to 9.