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TWI762091B - 三維薄膜電晶體陣列中準備薄膜電晶體通道區域之製程 - Google Patents

三維薄膜電晶體陣列中準備薄膜電晶體通道區域之製程 Download PDF

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TWI762091B
TWI762091B TW109144865A TW109144865A TWI762091B TW I762091 B TWI762091 B TW I762091B TW 109144865 A TW109144865 A TW 109144865A TW 109144865 A TW109144865 A TW 109144865A TW I762091 B TWI762091 B TW I762091B
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維諾 普拉亞
傑 周
伍意 亨利 簡
伊萊 哈拉利
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美商森恩萊斯記憶體公司
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Abstract

一種製程包括：(a)提供具有平面的半導體基板；(b)於半導體基板之平面上形成薄膜層，一層位於另一層頂部，包括第一及一第二隔離層，第一隔離層提供相對在第二隔離層中更高濃度摻雜的第一摻雜物；(c)沿著大致正交於平面之一方向蝕刻通過薄膜層，以產生具有側壁的溝槽，側壁曝露薄膜層；(d)共形地沉積半導體材料在溝槽之側壁上；(e)在一預定溫度及一預定時間，將第一隔離層進行退火，使得第一隔離層作為第一摻雜物的源極，第一摻雜物摻雜鄰近第一隔離層的半導體材料之一部分；以及(f)選擇性蝕刻半導體材料以移除摻雜部分，而不移除其餘部分。

Description

三維薄膜電晶體陣列中準備薄膜電晶體通道區域之製程
本發明是關於一種製程使用於製作半導體電路。特別地是，本發明關於一種製程用於製作薄膜電晶體之三維陣列，如薄膜記憶電晶體。
薄膜記憶體之三維陣列如在美國專利案第10,121,553號所敘述，其於西元2018年11月6日獲證，專利名稱為「三維陣列中電容性耦合的非揮發性薄膜電晶體串」。專利’553公開一種在NOR型記憶體串之三維陣列，其中每一NOR型記憶體串包含沿著水平方向的半導體材料條形成之薄膜記憶電晶體，每一半導體材料條包含位於兩水平導電半導體層之間的一通道材料之水平層。導電半導體層分別形成用於NOR型記憶體串的一共汲區及一共源區
以下詳細說明，關於在半導體基底之一平面上方形成的薄膜電晶體。用語”水平”以及”垂直”是指分別大致平行及大致正交於該平面之一方向。為了說明目的，X方向及Y方向是指平行於該平面的兩個正交方向，且Z方向正交於X方向及Y方向。
圖1(a)示出在一中間形成步驟處的一種三維薄膜電晶體陣 列之結構100。圖1(a)為結構100之一垂直截面圖。如圖1(a)所示，結構100示出主動堆疊101-1、101-2及101-3-它們是半導體條帶之許多平行主動堆疊的其中三個-由溝槽109彼此隔開。在圖1(a)中，每一主動堆疊包含一選定數量的主動條帶110，每個主動條帶藉著隔離層106與其相鄰者隔開(例如隔離層108-2及108-3將主動條帶110-2與主動條帶110-1及110-3隔開)。(主動堆疊沿著X方向設置，每個堆疊沿著Y方向在長度上延伸，每一主動條帶也沿著Y方向在長度上延伸且沿著Z方向堆疊。)此外，在本詳細描述中，當一材料或層通常由一第一參考符號(例如n)代表時，該材料或該層的特定實施例則由與第一參考符號連字符的一第二參考符號來區分(例如n-1,n-2等等)。
在一實施例中，每一主動堆疊包含8個主動條帶110-1、110-2...110-8。為了方便說明，僅圖示每一主動堆疊中101-1、101-2及101-3的三個主動條帶(例如主動條帶110-1、110-2及110-3)。一般而言，在三維薄膜電晶體陣列中，可提供任何適當數量的主動堆疊(例如1、2、4、16、32、64、128...)以及任何適當數量的主動條帶(例如1、2、4、8、16...)。在圖1(a)中，主動條帶(例如每條5奈米寬)分別藉由隔離層106彼此隔開(例如隔離層106-1、106-2及106-3)。每一主動條帶包含共汲區(common drain region)、共源區(common source region)及本體氧化層(body oxide layer)在其中(例如在主動條帶中110-1具有共汲區102-1、共源區103-1及本體氧化層104-1)。每一共汲區也提供一鄰近的金屬層以減少沿著長邊的電阻(例如共汲區102-1接觸如鎢(tungsten)的金屬層108-1)。在一些實施例中，一犧牲層SiN替代金屬層108-1，用以在隨後步驟中由金屬取代。
在上一步驟中，由溝槽109的側壁各向同性地(isotropically)蝕刻本體氧化層104(例如本體氧化層104-1、104-2及104-3)至凹陷。然後，一本質(intrinsic)或低摻雜的半導體材料(通道半導體材料)共形地沉積在溝槽109的側壁上。通道半導體材料如圖1(a)所示之層107，舉例來說，旨在作為每個主動條帶中薄膜儲存電晶體之共汲區及共源區之間的通道區。
為了產生通道區，一分離的蝕刻步驟-典型的各向異性地(anisotropic)蝕刻-隨後被執行，由溝槽109的側壁移除通道半導體材料而不破壞沉積於本體氧化層104上凹處內的通道半導體材料。圖1(b)示出分離的蝕刻後最後結構100的一實施例。然而，因為分離的蝕刻步驟產生一高的長寬比(例如每一溝槽109為60奈米寬及2微米深)，如箭頭A所指，鄰近本體氧化層的通道半導體材料通常會因橫向蝕刻(sideway etching)而太薄，且如箭頭B所指，溝槽109的底部留下沒有預期的縱樑(stringers)。過度細化之鄰近本體氧化層的通道半導體材料及在溝槽的側壁上餘留的縱樑都是不希望的。此外，若已提供了金屬層108，各向異性地(anisotropic)蝕刻可能濺鍍金屬而造成汙染。
根據本發明之一實施例，一種製程包括：(a)提供具有一平面的一半導體基板；(b)於半導體基板之平面上方形成複數個薄膜層，薄膜層之其一位於另一薄膜層之頂部，包括在薄膜層中一第一及一第二隔離層，其中第一隔離層提供一相對在第二隔離層中更高濃度摻雜的第一摻雜物；(c)沿著大致正交於平面之一方向蝕刻通過薄膜層，以產生一具有側壁的溝槽，其中側壁曝露薄膜層；(d)共形地沉積一半導體材料(例如一非晶 矽及一多晶矽)在溝槽之側壁上；(e)在一預定溫度及一預定時間，將第一隔離層進行退火處理，使得第一隔離層作為第一摻雜物的一源極，第一摻雜物摻雜鄰近第一隔離層的半導體材料之一部分；以及(f)選擇性蝕刻(例如乾式或濕式蝕刻)半導體材料以移除半導體材料之摻雜部分，而不移除半導體材料之其餘部分。本製程也可包含蝕刻薄膜層，使得第一隔離層從溝槽之側壁凹進。
在一實施例中，第一隔離層可以包含一有機矽層(例如碳氫化矽SiOCH或碳化矽SiOC)、一氮化矽層或一矽酸鹽玻璃(例如硼矽玻璃BSG或磷矽酸鹽玻璃PSG)，以及(ii)選擇性蝕刻使用一蝕刻劑，其可包含四甲基氫氧化胺(TMAH)、氫氧化鉀(KOH)或乙二胺鄰苯二酚(EDP)。在本案例中，退火步驟包括一快速熱退火步驟，以及其中預定溫度位於攝氏650度至820度之間，且較佳大約為750度。
在另一實施例中，第一隔離層可以是碳摻雜，其碳摻雜濃度約為1020cm-3或更高，以及選擇性蝕刻使用一蝕刻劑，其包含乙二胺鄰苯二酚(EDP)。在本例中，退火步驟包括一快速熱退火步驟，以及其中該預定溫度位於攝氏600度至820度之間，且較佳大約為750度。
在另一實施例中，於鄰近且位於半導體材料上方，沉積具有高摻雜一第二摻雜物之一額外材料。一退火步驟將第二摻雜物擴散至半導體材料，以調整半導體材料中一有效摻雜濃度。此有效摻雜濃度可決定半導體材料中作為一通道區的一薄膜電晶體之一閾限電壓。在某些實施例中，第一摻雜物可以是硼，及第二摻雜物可以是磷，或是反之亦然。
在另一實施例中，第一隔離層包含一有機矽層(例如具有一 摻雜濃度大於1.0×1022cm-3的BSG或PSG)、一氮化矽層或一矽酸鹽玻璃，以及選擇性蝕刻使用一蝕刻劑，其可以包含氯原子、氫氟酸(氣態或在一氫氟酸水溶液中)或一碳氫化合物氣體(fluorocarbon gas)。在本例中，退火步驟包括一快速熱退火步驟，以及其中預定溫度位於攝氏600度至820度之間，且較佳大約為750度。在各種適宜的比例中一合適的氫氟酸水溶液包含氫氟酸、硝酸及乙酸。一覆蓋層可以沉積於共形沉積的半導體材料上方。
通過以下結合附圖的詳細說明，可以更好地理解本發明。
100:結構
105:基板
101-1、101-2、101-3:主動堆疊
102、102-1、102-2、102-3:共汲區
103、103-1、103-2、103-3:共源區
104、104-1、104-2、104-3:本體氧化層
106、106-1、106-2、106-3、106-4:隔離層
107、107-1、107-2、107-3:通道半導體材料(層)
108-1、108-2、108-3:金屬層
109:溝槽
110、110-1、110-2、110-3:主動條帶
120:PSG層
121:緩衝氧化層
122:覆蓋層
A、B:箭頭
X、Y、Z:方向
圖1(a)為在一中間形成步驟處的一種三維薄膜電晶體陣列之結構100。
圖1(b)為一分離蝕刻之後最終結構100之一實施例。
圖2(a)為根據本發明之一實施例的最後結構100，其在溝槽109之側壁上部分的通道半導體材料107被標記為107-1，而鄰近本體氧化層104之硼摻雜部分的通道半導體材料107被標記為107-2。
圖2(b)為利用未摻雜多晶矽相對一預定摻雜濃度或更高的矽摻雜具有顯著不同蝕刻速率之蝕刻劑，以進行選擇性蝕刻後的最後結構100。
圖3顯示經過圖2(b)之選擇性蝕刻後，將例如10奈米厚的磷矽酸玻璃(PSG)之一薄層120沉積在根據本發明之一實施例的結構100上。
圖4(i)及圖4(ii)描繪本發明之一替代實施例，其中隔離層106摻雜其鄰近的通道半導體材料107以供選擇性移除。
圖5(i)及圖5(ii)描繪本發明之一第二實施例，其中隔離層106摻雜其鄰近的通道半導體材料107以供選擇性移除。
圖6(i)、圖6(ii)及圖6(iii)描繪本發明之一第三實施例，其中隔離層106摻雜其鄰近的通道半導體材料107以供選擇性移除。
本發明避免了過度細化之鄰近本體氧化層的通道半導體材料以及在溝槽的側壁上餘留的縱樑。相較於取決於分離蝕刻的方向性，本發明之方法化學性地轉換鄰近本體氧化層之凹處內部分的通道半導體材料，或溝槽之側壁上部分的通道半導體材料，抑或兩者，以使得一隨後的蝕刻步驟可選擇性地由溝槽之側壁移除部分的通道半導體材料。
根據本發明之第一實施例，沉積時圖1(a)中結構100之本體氧化層104為重摻雜硼(例如p+型)，而共汲層102及共源層103為砷摻雜(例如n+型)。在本實施例中，本體氧化層104舉例來說可以是一具有摻雜濃度約為1.0×1020cm-3或更高之50奈米厚的有機矽層(例如碳氫化矽SiOCH)。共形地沉積通道半導體材料層107(例如本質多晶矽)之後，執行一退火步驟(例如在750℃下進行10分鐘的一快速熱退火(RTA)步驟)。因為退火步驟，硼由本體氧化層104向外擴散至其鄰近部分的通道半導體材料107，造成在此部分的摻雜濃度例如於大約5.0×1018cm-3及大約1.0×1019cm-3之間。於此期間，一些數量的砷也可以由共汲層102及共源層103向外擴散至其各別鄰近部分的通道半導體材料107。不過，在650℃以上時，硼的擴散速率要比砷的擴散速率高很多，因此砷擴散相較下就無關緊要。圖2(a)示出最後結構100，在溝槽109之側壁上部分的通道半導體材料107被標記為107-1，而 鄰近本體氧化層104之硼摻雜部分的通道半導體材料107被標記為107-2。
因為四甲基氫氧化胺(TMAH)對於未摻雜的多晶矽蝕刻速率相較於摻雜多晶矽至少大約1018cm-3摻雜濃度者高了至少五倍，利用一選擇性蝕刻使用例如四甲基氫氧化胺(TMAH)，可以由溝槽109之側壁移除通道半導體材料107-1，留下本體氧化層104之凹處內的通道半導體材料107-2。選擇性蝕刻可以是等向性(isotropic)濕式或乾式蝕刻。最後結構如圖2(b)所示。
其他具有高選擇性的蝕刻劑也可以使用，其高選擇性是指對於未摻雜的多晶矽蝕刻速率高於摻雜多晶矽者。舉例來說，氫氧化鉀(KOH)對於未摻雜的多晶矽相較於摻雜濃度超過1020cm-3之多晶矽者，其具有20：1的選擇性。同樣地，乙二胺鄰苯二酚(EDP)的水溶液對於未摻雜的多晶矽相較於摻雜濃度超過7.0×1019cm-3之多晶矽者，其具有50：1的選擇性。
根據本發明之另一實施例，沉積時圖1(a)中結構100之本體氧化層104為摻雜碳，而共汲層102及共源層103為砷摻雜(例如n+型)。在本實施例中，本體氧化層104舉例來說可以是一具有碳摻雜濃度約為5.0×1020cm-3或更高之50奈米厚的碳摻雜氧化物。共形地沉積通道半導體材料層107(例如所需摻雜濃度的原位(in situ)硼摻雜多晶矽)之後，執行一退火步驟(例如在750℃下進行10分鐘的一快速熱退火(RTA)步驟)。因為退火步驟，碳由本體氧化層104向外擴散至其鄰近部分的通道半導體材料107，造成在此部分的摻雜濃度例如至大約5.0×1020cm-3。
因為乙二胺鄰苯二酚(EDP)對於未摻雜的多晶矽蝕刻速率 相較於至少約1020cm-3摻雜濃度之碳摻雜多晶矽高了至少一百倍，利用一選擇性蝕刻使用例如EDP，可以由溝槽109之側壁移除通道半導體材料107-1，留下本體氧化層104之凹處內碳摻雜的通道半導體材料107-2。選擇性蝕刻可以是等向性(isotropic)濕式或乾式蝕刻。
與本發明之方法有關的一個考慮因素為影響最後的薄膜電晶體之閾值電壓(Vth)。在一實施例中，在摻雜濃度為5.0×1019cm-3的情形下，其結果電壓Vth相對較少摻雜濃度5.0×1018cm-3時，可以獲得所需理想的1.5伏特更多。在這方面，採用高選擇性無論是KOH或EDP，其最後的薄膜電晶體之電壓Vth可能太高。為了微調(fine-tune)摻雜濃度，可以在圖2(b)的選擇性蝕刻之後，對通道半導體材料107-2進行反摻雜(counter-dope)。根據本發明之一實施例，在圖2(b)的選擇性蝕刻之後，可以將例如10奈米厚的磷矽酸玻璃(PSG)之一薄層120沉積在結構100上，如圖3所示。然後在隨後的退火步驟中，使磷矽酸玻璃(PSG)中的磷擴散至通道半導體材料107-2。憑經驗決定在磷矽酸玻璃(PSG)中的初始摻雜濃度以及隨後的RTA步驟之溫度及時間，以在所得薄膜電晶體實現一給定之所需電壓Vth。一般而言，在溫度低於1000℃，在多晶矽中磷具有相對硼較大的擴散速率。在退火步驟之後，PSG層120可以通過濕式等向性(isotropic)蝕刻移除(例如使用氫氟酸HF)。
或者，除了轉換通道半導體材料107鄰近本體氧化層104之部分內的摻雜濃度的方法以外，轉換位在溝槽109之側壁上通道半導體材料107之部分也是可行。根據本發明一實施例，隔離層106最初被沉積為例如具有磷摻雜濃度大於5.0×1020cm-3的重摻雜n++型矽結晶(c- silicon(SiOC))。在本實施例中，可以沉積通道半導體材料107原位(in situ)摻雜至通道區所需的摻雜濃度(例如1.0×1018cm-3)。在本體氧化層104中沒有高摻雜濃度的情形下，一隨後的快速退火(RTA)步驟將通道半導體材料107鄰近隔離層106之部分轉變為n型半導體材料107-3，如圖4(i)所示。使用氫氟酸或一碳氫化合物氣體，在n++型多晶矽(例如摻雜濃度為3.0×1020cm-3或更高)相對p型多晶矽之一高達40：1之選擇性的情況下，可以移除n型通道半導體材料107-3。選擇性的差異據信是由磷摻雜分布之密度所引起(請見2013年固態科學與技術雜誌(Solid State Science and Technology),2(9)，第380-383頁)。最後結構請見圖4(ii)。可以注意的是，不同於前述其他實施例，在本實施例中，雖然通道半導體材料之一些部分107-3仍保留在溝槽109之側壁上，主動條帶中最後的通道區還是實現了彼此的電性隔離。
根據本發明之另一實施例，隔離層106最初被沉積為例如具有硼摻雜濃度大於5.0×1021cm-3的重摻雜p++型硼矽玻璃(BSG)。在本實施例中，可以沉積10奈米厚通道半導體材料107原位(in situ)摻雜至通道區所需的摻雜濃度(例如1.0×1018cm-3)。一快速退火步驟(例如在600℃下持續期間為14分鐘，包含通道半導體材料107之沉積時間)將通道半導體材料107鄰近隔離層106之部分轉變為10奈米厚p型半導體材料107-3，如圖5(i)所示。在600℃，硼擴散實際上快於砷，使得擴散進入通道半導體材料107鄰近共源區103及共汲區102之部分為無關緊要的(例如少於1.0奈米)。可以注意的是，在圖5(i)及(ii)中緩衝氧化層121可以加入隔離層106及鄰近的共源區103之間，以避免硼擴散至共源區103。此外，隔離層106、緩衝氧化層121及本體氧化層104在一前次氧化蝕刻步驟中被凹陷。
採用一氫氟酸水溶液(例如以容積計量1份氫氟酸至50份硝酸(nitric acid)及100份乙酸(acetic acid))，在p型多晶矽(例如摻雜濃度為5.0×1021cm-3或更高)相對未摻雜或輕摻雜多晶矽之一高達50：1之選擇性的情況下，可以將p型通道半導體材料107-3移除。利用較低百分比的硝酸(HNO3)可以實現更高的選擇性。在一乾式蝕刻步驟中，為了達到相同結果，氫氟酸(HF)、硝酸(HNO3)及乙酸(CH3COOH)蒸氣可被使用(請見例如Hwang等人的美國專利案第4,681,657號)。最後結構請見圖5(ii)。
又或者，PSG可以被做為隔離層106，而非BSG。根據本發明之一實施例，圖6(i)-6(iii)描繪本發明之一第三替代實施例，其中隔離層106摻雜其鄰近的通道半導體材料107以選擇性移除。如圖6(i)所示，隔離層106最初被沉積為例如具有磷摻雜濃度大於1.0×1022cm-3的重摻雜PSG。在本實施例中，可以沉積通道半導體材料107為550℃的原位(in situ)摻雜非晶矽(amorphous silicon)或625℃的多晶矽，以達到通道區所需的摻雜濃度(例如1.0×1018cm-3)。此外，在溫度為650℃或更低的情況下，可以提供2奈米氧化矽或氮化矽的覆蓋層122來預防磷從通道半導體材料107擴散出來。在此實施例中，鄰近金屬層108的共源區103及共汲區102皆被提供以降低電阻率。
然而，圖6(ii)描繪一快速退火步驟在820℃下進行60秒或更少，將通道半導體材料107鄰近隔離層106之部分轉變為重摻雜n型通道半導體材料107-3，同時激發磷摻雜物(例如至一大約3.0×1020cm-3的平衡摻雜濃度)。沉積的非晶矽也被結晶為通道半導體材料107-2。在820℃下，砷由共源區103及共汲區102擴散至通道半導體材料107是微不足道的。
然後，將覆蓋層122各向同性地移除。採用一原子氯氣(atomic chlorine gas)，在n型多晶矽(例如摻雜濃度約為3.0×1020cm-3或更高)相對輕摻雜p型多晶矽之一高達6：1之選擇性的情況下，可以將重摻雜n型通道半導體材料107-3移除，如圖6(iii)所描繪。
以上詳細描述提供說明本發明的特定實施例，但並不以此為限。本發明範圍內的各種修改和變化都是可能的。以下申請權利範圍闡述了本發明。
100:結構
105:基板
101-1、101-2、101-3:主動堆疊
102-1、102-2、102-3:共汲區
103-1、103-2、103-3:共源區
104-1、104-2、104-3:本體氧化層
106-1、106-2、106-3、106-4:隔離層
107-2:通道半導體材料(層)
109:溝槽

Claims (19)

  1. 一種三維薄膜電晶體陣列中準備薄膜電晶體通道區域之製程，包括：提供一半導體基板，其具有一平面；於該半導體基板之該平面上方形成複數個薄膜層，該些薄膜層之其一者位於該些薄膜層另一者之頂部，包括在該些薄膜層中一第一及一第二隔離層，其中該第一隔離層提供一相對在該第二隔離層中更高濃度摻雜的第一摻雜物；沿著大致正交於該平面之一方向蝕刻通過該些薄膜層，以產生一具有側壁的溝槽，該側壁曝露該些薄膜層；共形地沉積一半導體材料在該溝槽之該側壁上；在一預定溫度及一預定時間退火該第一隔離層，使得該第一隔離層作為該第一摻雜物的一源極，該第一摻雜物摻雜鄰近該第一隔離層的該半導體材料之一部分，且選擇性蝕刻該半導體材料以移除該半導體材料之該摻雜部分，而不移除該半導體材料之其餘部分。
  2. 如申請專利範圍第1項所述之製程，更包括：蝕刻該些薄膜層，使得該第一隔離層從該溝槽之該側壁凹進。
  3. 如申請專利範圍第1項所述之製程，其中該半導體材料包括一非晶矽及一多晶矽的至少其一。
  4. 如申請專利範圍第1項所述之製程，其中選擇性蝕刻包括一乾式蝕刻步驟。
  5. 如申請專利範圍第1項所述之製程，其中(i)該第一隔離層以下至少一或多 者：一有機矽層(organosilicon)、一氮化矽層及一矽酸鹽玻璃(silicate glass)，以及(ii)選擇性蝕刻使用一蝕刻劑，其包含以下至少一者：四甲基氫氧化胺(TMAH)、氫氧化鉀(KOH)及乙二胺鄰苯二酚(EDP)。
  6. 如申請專利範圍第5項所述之製程，其中退火步驟包括一快速熱退火步驟，以及其中該預定溫度位於攝氏650度至820度之間。
  7. 如申請專利範圍第5項所述之製程，其中該第一摻雜物包括硼。
  8. 如申請專利範圍第5項所述之製程，其中該有機矽層包括碳氫化矽(SiOCH)或碳化矽(SiOC)。
  9. 如申請專利範圍第1項所述之製程，其中該第一隔離層為碳摻雜，其碳摻雜濃度約為1020cm-3或更高，以及其中選擇性蝕刻使用一蝕刻劑，其包含乙二胺鄰苯二酚(EDP)。
  10. 如申請專利範圍第9項所述之製程，其中退火步驟包括一快速熱退火步驟，以及其中該預定溫度位於攝氏600度至820度之間。
  11. 如申請專利範圍第1項所述之製程，更包括沉積一高摻雜材料鄰近且於該半導體材料上方，該高摻雜材料包括一第二摻雜物，以及對該第二摻雜物進行退火以調整該半導體材料中一有效摻雜濃度。
  12. 如申請專利範圍第11項所述之製程，其中該有效摻雜濃度決定該半導體材料中作為一通道區的一薄膜電晶體之一閾限電壓。
  13. 如申請專利範圍第11項所述之製程，其中該第一摻雜物包括硼及該第二摻雜物包括磷。
  14. 如申請專利範圍第1項所述之製程，其中(i)該第一隔離層以下至少一或多者：一有機矽層(organosilicon)、一氮化矽層及一矽酸鹽玻璃(silicate glass)， 以及(ii)選擇性蝕刻使用一蝕刻劑，其包含以下至少一者：氯原子、氫氟酸(HF)及一碳氫化合物氣體(fluorocarbon gas)。
  15. 如申請專利範圍第14項所述之製程，其中退火步驟包括一快速熱退火步驟，以及其中該預定溫度位於攝氏600度至820度之間。
  16. 如申請專利範圍第14項所述之製程，其中該第一摻雜物包括磷。
  17. 如申請專利範圍第14項所述之製程，其中在一氫氟酸水溶液中提供該蝕刻劑，該氫氟酸水溶液包含氫氟酸及以下一或多者：硝酸及乙酸。
  18. 如申請專利範圍第1項所述之製程，更包括沉積一覆蓋層於共形沉積的該半導體材料上方。
  19. 如申請專利範圍第18項所述之製程，其中該第一隔離層包括具有硼或磷之一摻雜濃度大於1.0×1022cm-3的硼矽酸鹽玻璃或磷矽酸鹽玻璃。
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