1342118 修正日期·· 99.H.8 第96122496號之專利說明書修正本 九、發明說明： 【發明所屬之技術領域】 一種 三個 本發明係有關於-種輸入電路，特別是有關於 輸入電路’用以判斷於輸人腳位（inputpin)上戈 狀態。 【先前技術】 一般而言，根據輪入信號，積體電路之邏輯輸入腳 位（Μ)具有兩個邏輯狀態，例如高邏輯狀態與低邏輯 狀惡。在-些應用中，邏輯輸人腳位可能具有浮接狀態 /floating state)，其表示邏輯輸入腳位沒有接收任何信 號。因此’習知的輸入電路可用來判斷輸入腳位上的兩 個^態，例如浮接狀態與高邏輯狀態，或者浮接狀態與 低邏輯狀態。習知的輸入電路更可用來判斷輸入腳位上 白^三個狀態’例如浮接狀態、高邏輯狀態、與低邏輯狀 態。當輸入腳位處於浮接狀態時，習知輸入電路透過一 個電阻器將輸入腳位之位準拉高或拉低。例如，當輸入 腳位具有浮接狀⑮與$邏輯狀態，且輪人腳位正處於浮 接狀態時，習知的輸入電路透過耦接於輸入腳位與接地 之間的電阻器，將輸人腳位之位準拉低，且輸人電路則 輸入腳位之位準為低邏輯位準。當輸入腳位正處於 尚邏輯狀態時，前述習知的輸入電路判斷輸入腳位之位 準為高邏輯位準。然而，介於輸八腳位與接地之電阻器 所形成的路徑上會產生漏電流。因此，期望提供一種輸 〇^58-A32293TWF2(20100913) 6 1342118 修正曰期：99.丨1.8 第％U2496號之專利說明書修正本 入電路’其可判斷輸入腳位 處於低或高邏輯狀態時 “ ’且當輸入腳位 八了減少漏電流的產生。 【發明内容】 本發明提供—種輸入電路， 態，輸入電路包括位準 、4畊輸入端之狀 定單元由輪入電心…以及輸出單元。位準決 能信號控制的^ 5虎且在弟一致 、』日]弟期間，決定輸入信號之雷 ，， 且位準決定單元接收參考電塵，去 土，亚 時，位準决定單元決定以田^而處於浮接狀態 之電壓位準。輸電堊位準為參考電壓 … 羊輸出早讀接輸入端。在第 早兀由輸入電路之輪出屮 1輸出 士入 ^ ^ 輸出具有已決定之雷厭々^ .•隹 之輸入信號，以作為給屮 電土位準 丨户冷跑出k唬。在接續於 二期間，輸出單元根據第_ 、、 " 第 谠之已決定之電壓位準，且由 用』八乜 雷厭/*、、隹★认 輸出&輸出具有已決定之 電ε位準之輸入信號’以作為輸出信號。 本發明另提供一種輪人m ^ ^ 輸電路’用於判斷輸入端之狀 悲’輸入電路包括位準衫單元、類比數位轉換單元' 以及拾鎖⑽ch)模組。位準決定單元由輸入電路1342118 Revision Date··99.H.8 Patent Specification Revision No. 96022496 This ninth, invention description: [Technical Field of the Invention] One of the three inventions relates to an input circuit, and more particularly to an input circuit It is used to judge the input state of the input pin. [Prior Art] In general, according to the round-in signal, the logic input pin (Μ) of the integrated circuit has two logic states, such as a high logic state and a low logic state. In some applications, the logic input pin may have a floating state /floating state, which indicates that the logic input pin does not receive any signal. Thus, conventional input circuits can be used to determine two states on the input pin, such as a floating state and a high logic state, or a floating state and a low logic state. The conventional input circuit can be used to judge the three states of the input pin, such as a floating state, a high logic state, and a low logic state. When the input pin is in a floating state, the conventional input circuit pulls the position of the input pin high or low through a resistor. For example, when the input pin has a floating shape 15 and a logic state, and the wheel pin is in a floating state, the conventional input circuit transmits through a resistor coupled between the input pin and the ground. The position of the human foot is lowered, and the input circuit is leveled to a low logic level. When the input pin is in the logic state, the conventional input circuit determines that the input pin position is a high logic level. However, a leakage current is generated in the path formed by the resistor connected to the ground pin and the ground. Therefore, it is desirable to provide a transmission 〇58-A32293TWF2(20100913) 6 1342118 Revision period: 99.丨1.8 The patent specification of No. U2496 modifies the input circuit 'when it can judge the input pin is in the low or high logic state' 'And when the input pin is eight, the generation of leakage current is reduced. SUMMARY OF THE INVENTION The present invention provides an input circuit, state, input circuit including level, 4 input terminal of the input terminal by the wheeled core... and the output unit The positional decision signal control of the ^5 tiger and the brother in the same, "day" brother, decided to input the signal of the thunder, and the level determination unit receives the reference electric dust, to the soil, sub-time, the level decision unit decides The voltage level in the floating state is in the field ^. The power transmission level is the reference voltage... The sheep output is read early and the input end. In the early morning, the input circuit is out of the 屮1 output, and the output is determined. The Thunder is disgusted with the input signal of the 隹 以 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Level, and The input signal 'having the determined electric ε level' is outputted as the output signal by the singularity of the 乜 乜 / * * * * * * * * * 。 。 。 。 。 认 认 认 认 认 认 认 认 认 认 认 认 认 认 认 认 认 认 认The input end of the sorrow 'input circuit includes a level shirt unit, an analog digital conversion unit' and a pickup lock (10) ch) module. The level determining unit is input circuit
接收輸入信號，且在第一期門括姑# MJ -於W V 間根據第-致能信號來決 ^輸入彳“之電壓位準。類比數位轉換單元接收 人信號之已決定之電壓位準，根據輸 味心m + 將輸入信號轉換為數位信 拴鎖核、·且在接續於第—期間之—第二期間，由第二 0758-A32293TWF2(201009I3) 7 1342118 第96122496號之專利說明書修正本 修正日期：99.〗1.8 致能信號控制，以拴鎖數位信號作為輸出信號。 本發明另提供-種方法，適用於輸人電路，輸入雷 :具：輸入端，方法包括：決定輸入端上輸入信號之電 拾鎖輸人信號之已衫之電墨位準；輸出具有 疋之電壓位準之輸入信號，以作為輪出作號.以 根據'出信號來判斷輸入端之狀態；其中當輸入端處於 斤接狀恶時，決定輸入信號之電壓位準為參 壓位準。 电 為使本發明之上述目的、特徵和優點能更明顯易 言I明2特舉—較佳實施例，並配合所附圖式，作詳細 【實施方式】 第I圖縣示本發明實施例之輸人電路，其可 輸入端之兩個狀態。如第i圖所示，輪入電路！包括位 =單元H)及輸出單元η。輸入端可以是積體電路之 m腳位。位準決定單元1G由輸人電路丨之輸^ PlN接收輸入信號IN，且在致能信號EN—丨控制的第—期 間’決定輸入信號ΙΝ之電壓位準。在此第一期間中，钤 =11由輪出電路1之輸出端W輸出具有已“ 的電壓位準的輸入信號1N，以做為輸出信號out。在接 :於第-期間之第二期間中’輸出單元" 綠鎖（la剛輸人信號IN已決定的電壓位準= 勒出编ρ〇υτ輸出具t已決定的電墨位準的輸入信號川， 0758-A32293TWF2(20100913) 8 1342118 修正曰期：99.11.8 第96122496號之專利說明書修正本 =輸出信號OUT。根據輪出信號㈤丁，則可獲得輪 入食而P1N之狀態。 在本發明實施例中，信號之電壓位準㈣—參考位 準而可分^電壓位準與低電壓位準，在數位邏輯上， 刀別對應趣輯兩位準與邏輯低位準。 5本發明中’輸入端P1N之兩個狀態可以是浮接狀 悲…^輯狀態，或者是浮接狀態與低邏輯狀態。在下 面白勺况明中，將以輸入端p! N之浮接狀態與低邏輯狀 例來說明第1圖之實施例。 …、 如第】圖所示，輸入電路！更包括位準維持單元 =在弟二期間中，位準維持單元12由致能信號EN2 控制，以維持輸入端P1N之電壓值。位準維持單元】2防 止了當輸入端處於浮接狀態時，輸入端P|n之電壓值受到 雜訊干擾。輸入電路1也包括時序產生單元⑴― generat_Unit) 13’用以產生致能信號ΕΝ UEN 2。 致能信號ENJ與致能信號EN—2具有相反之電壓位準， 例如一者為高電壓位準，另一者為低電壓位準。 口口參閱第】圖，位準決定單元10包括開關i〇a及電阻 克腸。開關1〇a受到致能信號ENJ的控制。開關⑽ =第-魅接參考電屢VREF。在此實施例中，由於輸入 ^ P丨N之兩個狀態為浮接狀態與低邏輯狀態，來考電屏 vREF則為供電電壓（power vohage)。相反地，假使ς 入端PlN之兩個狀態為浮接狀態與高邏輯狀態，來考電辦 Vref則為接地電塵。電阻器】⑽之第—端糾開關】0a 〇758-A3229.-5TWF2i201〇〇9I3) 1342118 第96122496號之專利說明書修正本 紅日期：99.u_8 之第二端，且電阻器l〇b之第二端耦接輸入端Pin。 參閱第1圖’輸出單元包括反向器Ua、m 及lie，以及開關lid。反向器1 ia及1]b以串聯的方式 耦接。如第1圖所示，反向器lla耦接於節點Nn與輪 入端P1N之間，且反向器lib耦接於輸出端ρ〇υτ與節點 Nil之間。開關lid受致能信號ΕΝ—2所控制，且耦接反 向器1 1 c於輸入端ΡΙΝ與節點Ν 1 1之間。 位準維持單元12包括開關12a及121)，以及電阻哭 12c。開關12及12b以及電阻器〗2c以串聯的方式耦接 於參考電壓VREF與輸入端p1N之間。開關]2a受輸出信 5虎OUT所控制，且開關12b受致能信號EN—2所控制。 在另-實施例中，參考電壓VREF為接地，開—關12:受致 能信號EN_2的反向信號所控制。 第2圖係表示參考電壓Vref與致能信號EN丨間之 關係。輸入電路1之操作將根據第丨及2圖來說_明。在 此實施例中，所有的開關由高電壓位準信號來導通，且 由邏輯低位準信號來關閉。 麥閱第2圖，在第一期間pj，參考電壓由 開始上升，且具有高電壓位準，致能信號EN—丨則隨著參 考電壓vREF (供電電壓）上升。當致能信號en—1到達 高電壓位準以導通開關l〇a時，在位準決定單元·中， 於參考電壓VREF與輸入端PIN間形成第—路徑。假使輸 入端Ρινί處於浮接狀態，輸入信號IN之電壓位準則透過 第路徑且根據麥考電壓Vref而.拉高。位準決定單元 0758-A32293TWF2(201〇〇9l3) 1342118 修正日期：99,丨1.8 第96!22496號之專利說明書修正本 則決定輸入信號1 N之電壓位準為高電壓位準。換句話 說’位準决定單元10決定輸入信號m之電壓位準為泉 。考電壓之電壓位準。在第—期間ρ」，開關⑴被與致能 、仏5虎EN-】相反之致能信號EN—2閉，且具有高電覆位準 之輸入信號IN，透過反向器lla及⑽而輸出至輸出端Receiving the input signal, and inputting the voltage level of the input signal according to the first enable signal in the first period of the gate # MJ - between the WVs. The analogous digital conversion unit receives the determined voltage level of the human signal, Amendment of the patent specification of the second 0758-A32293TWF2 (201009I3) 7 1342118 No. 96922496 according to the scent heart m + converting the input signal into a digital letter lock nucleus, and during the second period following the first period Amendment date: 99.〗 1.8 Enable signal control, with the shackle digital signal as the output signal. The invention further provides a method suitable for inputting a circuit, input lightning: with: input, the method includes: determining the input end The electric signal of the input signal is input to the electric signal level of the shirt; the input signal having the voltage level of the 疋 is output as the rounding number. The state of the input end is judged according to the 'out signal; When the input end is in the stagnation state, the voltage level of the input signal is determined to be the reference level. The above-mentioned objects, features and advantages of the present invention can be made more obvious. Cooperate with DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Implementation] FIG. 1 shows an input circuit of an embodiment of the present invention, which can input two states of the terminal. As shown in the figure i, the wheeled circuit! includes bit = unit H) and The output unit η. The input terminal may be the m-pin of the integrated circuit. The level determining unit 1G receives the input signal IN from the input circuit P1N of the input circuit, and is determined by the first period of the enable signal EN_丨The voltage level of the input signal 。. During this first period, 钤=11 is output from the output terminal W of the wheel-out circuit 1 to the input signal 1N having the "voltage level" as the output signal out. In the second period of the first period, the 'output unit' green lock (the voltage level that has been determined by the input signal IN of the la = the output of the ρ 〇υ τ output has the determined ink level Input signal Chuan, 0758-A32293TWF2 (20100913) 8 1342118 Revision period: 99.11.8 Patent No. 96122496 Revision = Output signal OUT. According to the turn-off signal (5), the state of P1N can be obtained. In the embodiment of the present invention, the voltage level of the signal (4) - the reference level can be divided into the voltage level and the low voltage level, and in the digital logic, the knife corresponds to the interesting level and the logic level is low. In the invention, the two states of the input terminal P1N may be a floating state, a floating state, and a low logic state. In the following description, the floating state and the low logic of the input terminal p! For example, the embodiment of Fig. 1 is shown. ..., as shown in the figure, the input circuit! further includes a level maintaining unit = during the second period, the level maintaining unit 12 is controlled by the enable signal EN2 to maintain Voltage value at input terminal P1N. Level maintenance unit] 2 prevents When the input terminal is in the floating state, the voltage value of the input terminal P|n is interfered by noise. The input circuit 1 also includes a timing generating unit (1) - generat_Unit 13' for generating the enable signal ΕΝ UEN 2. The enable signal ENJ and the enable signal EN-2 have opposite voltage levels, for example one is a high voltage level and the other is a low voltage level. Referring to the figure, the level determining unit 10 includes a switch i〇a and a resistor. The switch 1A is controlled by the enable signal ENJ. Switch (10) = first - enchant reference power repeatedly VREF. In this embodiment, since the two states of the input ^ P丨N are the floating state and the low logic state, the test screen vREF is the power supply voltage (power vohage). Conversely, if the two states of the inverting terminal P1N are the floating state and the high logic state, the Vref is the grounding dust. Resistor] (10) The first-end correction switch] 0a 〇 758-A3229.-5TWF2i201〇〇9I3) 1342118 The patent specification No. 96122496 modifies the red date: the second end of 99.u_8, and the resistor l〇b The second end is coupled to the input terminal Pin. Referring to Figure 1, the output unit includes inverters Ua, m and lie, and switch lid. The inverters 1 ia and 1] b are coupled in series. As shown in FIG. 1, the inverter 11a is coupled between the node Nn and the terminal P1N, and the inverter lib is coupled between the output terminal ρ〇υτ and the node Nil. The switch lid is controlled by the enable signal ΕΝ-2, and is coupled between the input terminal ΡΙΝ1 and the node Ν 1 1 . The level maintaining unit 12 includes switches 12a and 121), and a resistor cry 12c. The switches 12 and 12b and the resistor 2c are coupled in series between the reference voltage VREF and the input terminal p1N. The switch 2a is controlled by the output signal 5, and the switch 12b is controlled by the enable signal EN-2. In another embodiment, the reference voltage VREF is grounded, and the on-off 12: is controlled by the inverted signal of the enable signal EN_2. Fig. 2 shows the relationship between the reference voltage Vref and the enable signal EN. The operation of the input circuit 1 will be described in accordance with Figures 2 and 2. In this embodiment, all of the switches are turned on by the high voltage level signal and are turned off by the logic low level signal. In the second picture, in the first period pj, the reference voltage starts to rise and has a high voltage level, and the enable signal EN-丨 rises with the reference voltage vREF (supply voltage). When the enable signal en-1 reaches the high voltage level to turn on the switch l〇a, in the level determining unit, a first path is formed between the reference voltage VREF and the input terminal PIN. If the input terminal Ρινί is in a floating state, the voltage level criterion of the input signal IN passes through the first path and is pulled high according to the McCaw voltage Vref. Level decision unit 0758-A32293TWF2 (201〇〇9l3) 1342118 Revision date: 99, 丨1.8 The revision of the patent specification No. 96!22496 determines that the voltage level of the input signal 1 N is a high voltage level. In other words, the level determining unit 10 determines the voltage level of the input signal m as a spring. Check the voltage level of the voltage. In the first period ρ", the switch (1) is closed with the enable signal EN-2 opposite to the enable, 仏5 tiger EN-], and has a high electric level input signal IN, which passes through the inverters 11a and (10). Output to output
Ldt K乍為輸出信號〇1]丁 D由於開關⑶也由致能信 號既2所關閉，因此位準維持單丨12處於閒置狀態 (inactive)。 Φ &當參考電墨V町上升至既定電壓（例如2.7V)時， 致能信號ΕΝ—1切換至低電壓位準，以關閉開關伽，且 致，信號EN_2切換至高電壓位準，以導通開關⑴。參 閱第2圖’致能信號εν」切換為低電壓位準時的時間以 ‘標記”τρ”來標示，且在時間TP後的期間稱為第二期間 Ρ—^。。在第二期間Ρ_2 ’輪入信號ΙΝ之高電壓位準被反 向态11a及lie所拾鎖（latch)，且具有高電壓位準之輸入 •信號ίΝ透過反向器山及爪來輸出至輸出端Ρ〇υτ，以 作為輸出信號OUT。因此，根據高電壓位 OUT，則可判斷輸入端PiN係處於浮接狀態。 ；u 此外，在苐二期間P_2，第一路徑被關閉的開關1〇a 所切斷。由於開關】2a及12b分別由輸出信號㈣及致 能信號ΕΝ—2導通，在位準維持單元u中，於參考電壓 VREF與輸入端PlN間形成第二路徑。此第二路徑將輸入信 號IN，高電璧位準的電壓值稍稍拉高，以防止輸入信號 ίΝ之高電壓位準的電壓值受到雜訊干擾。 0758-A32293TWF2(20l〇〇913) 1342118 第96122496號之專利說明書修正本 修正曰期：99.11.8 在第一期間P_]中，假使輸入端P1N處於低邏輯狀 悲，輸入k號IN則為低電壓位準。位準決定單元1 〇因 此決定輸入信號IN為低電壓位準。由於開關n d由致能 信號EN_2所關閉，具有低電壓位準之輸入信號m則透 過反向器11a及lib輸出至輸出端Ρ〇υτ，以作為輸出信 號out。第二路徑被關閉的開關】2b切斷，因此位準維 持單το 12處於閒置狀態。由於在第一期間p—丨導通的開 關1 Oa ’漏電流則產生在第一路徑。 接著，在第二期間P一2 , EN—〗切換為低電壓位準以 關閉開關]Oa。第一路徑因此切斷，且不再有漏電流流經 第一路經。致能信f虎EN—2則切換為高電壓位準，以導通 開關lid’輸入信號IN之低電壓位準被反向器山及… 检鎖，且具有低電壓位準之輸人錢_透過反向器山 及lib輸出至輸出端Ρ〇υτ，以作為輸出信號ο·因此， ，據低，壓位準之輸出信號〇υτ，可決定輸人端〜係 處於低邏輯狀態。 4外，在第二期間Ρ—2，由於開關12a被低電壓位 f之輸出錢晰_，㈣特單元U也處於閒置 =二f 準的情況下二 ^ — 弟及第—路徑皆被切斷，因此沒有漏 電的產生。在一些實施例中，a认 為浮接狀態與高邏輯狀_，一兩個狀態 電壓位準之接地電壓謂;二電7::則是具有低 入信號ίΝ則透過位準決定單=於夺接狀態’輸 之弟一路徑，並根據 〇758-A32293TWF2(20100913) 第96122496叙專顺3轉修正本 第96122496叙專顺3轉修正本 修正日期：99.11.8 >考電壓VREF而拉低。位 。 號IN為低電壓位準 ^疋早兀1〇因此決定輸入信 1…1〇則決定輸入信雜之為高電壓位準。 上所述’致能信號ΕΝ 1及EN ?夕链ρ私拍4士 電電壓而定。第3圖扦本_ Γ --之鈐怨你根據供 實浐如— 圖表不弟1圖中時序產生單元】3之 '匕丨吕號產生器13,包括徒吝。 卜 _ 匕枯包壓產生态30、分壓器31、 車又早το 32、計時器33、多 向器36。分壓器31包括電二二二、或閘35、以及反 ^ , 電阻裔31a及31b。比較單元32 包括比較器323及〇型正及哭以甘丄私早兀32 3 反态32b，其中，D型正反器 岳丨I τ降緣所驅動，且產生初始具有低電壓位準之押 — 彳d產生初始具有低電壓位準之控 制仏 5虎 C S 2。電壓產;^ 。·1ώ ΙΑ· 撼徂Φ + 屋生态J〇接收供電電壓VBAT，且根 ，電電壓VBAT產生電壓V—〗。在此實施例中，電壓產 =以由能隙電壓產生器（bandgap V。丨tage gene晰） 二貝轭。在分壓器3】中’電阻器31a與3ib以串聯的方 式轉接於供電電壓Vba丁與接地電壓GND之間。分壓器 3】根據-既定比例之供電電壓Vbat與接地電壓gnd間 之^來產生電壓V-2°此既定比例係根據電阻器31a 及31b之電阻值來決定。t匕較器32a之非反向端（+)接 4電坌V~】，其反向端（-)接收電屋γ—2。假設供電雷 壓^丁緩慢的上升，例如上升時間小於一】㈣（ms)， 如第4圖所示。比較器32a比較電壓vj與v_2，且產 士釔果彳5唬Rs，並根據比較結果改變結果信號RS之電 C位準夕工杰之一端接收結果信號RS，其另一端接收 0758-A32293TWF2f20l〇〇9i3) 1342118 修正曰期：99.11.8 第96122496號之專利說明書修正本 =…。在第一期間PJ ’剛 ”電壓V-1，比較器32,將結果信號心；低； 壓位準。接著，電塵V—2變成小於電壓 :為低私 則將結果信號RS改變為高電壓位 —t#父态；32a 電墨位準變為高電壓位準，因為D = : 降緣時會轉態，控制信號CSJ維持在低電墨-有= 35接收皆具有低電堡位準之控制㈣⑴及二: 輸出具有低電壓位準之選擇信-接著輸出#雪雷厭v 5至夕工态34。多工器 ί ?作為致能信號EN-“換句話 ^ —，致旎信號隨著供電電壓V -r-, 升。反向器3"妾收並反向致能信號⑼ 之致能信號ENJ以作為致能信號抓2:輪出反向 Μ = ㈣TP後，即在第二期間[2中，電壓V 2微 成大於電壓VI。在佴雨赍颅” -1又 上，比較器32:將二二 結果信㈣由高電壓位準改變準。由於 信號RS上產生-個爾。則在結果 且控制信號cs i P遺著供電⑽广。32因此被觸發， 或閘％接收具有高電塵位”:變為高位準。 電壓位準之控制作轳d之工制㈣cs」及具有低 信號ss輸出至m—2’/將具有高電厂堅位準之選擇 準之結果信號多：，接著輸出低電屢位 信號EN—】在供電電壓…致::口 。因此，致能 愿位準變為低電壓位準二=㈣”上由高電 。。36接收亚反向低電壓位 〇758-A32293TWF2(20!〇〇9i3) 14 1342118 修正曰期：99.11.8 苐96122496號之專利說明書修正本 準之致能信號EN】，且耠屮g人 為致能信號ΕΝ2^ί f向之致能信號既1以作 電壓位準。當計時/3^=制信號CS—2初始具有低 準時’計時器將控制信號cs-2改為高 =，。使件多工器34輸出結果信號rs以作為致能 假使供電電壓V。，也、主，i 於電壓產生器3。“=::第5圖所示’由 壓”則永遠大於電罐速地上升，電 + r 电壓V-1。比較器32a則一直產峰俏 ^位準之結果信號以〜型正反器％ 被 = 永遠處於低電壓位準。或= 接收白具有低電壓位準之控制信號cs】 :!壓位準之選擇信號％輸出至多工器;4。多工。將4 =輸出供電電壓Vbat以作為致能信㈣ : 3電電壓、等於叫致能信號ΕΝ-〗不會二 I::準;，位準。在此情況下，計時器A 控制;^ ” 3 3到達時間ΤΡ時，計時器3 3直接將 二“: 改變為高電壓位準’使得多工器輸出結果 ，以作為致能信號ΕΝ_1。 在二戶、知例中，時序產生單元1 3可以簡化。第 = 中時序產生單元13之另一實施例。時序 早凡包括计時器60以及反向器61。計時哭6〇 致:=Nj。當計時器6。到達介於第一期間。pj 2間的時間Tps夺，計時器6〇將致能信號 0758-A32293TWF2(2〇i〇〇9i3l 1342118 修正日期：99.11.8 第96丨22496號之專利說明書修正本 既】改變為低電廢位準。反向器3】接收並反向致能信 號ENU ’且輸出反向之致能信號既】’以作為致能信 號 EN_2。 士在些戶、方匕例令，當輸入電路1應用於積體電路 % ’致/匕{吕號EN—1與EN—2由積體電路之内部產生。 •第7圖係表示本發明實施例之輸入電路，其可判斷 ，^端之三個狀態，即浮接狀態、高邏輯狀態、以及低 避輯H如第7圖所示’輸人電路7包括位準決定電 路7〇、類比數位轉換單元71、以及拴鎖模組72。輸入端 可以是積體電路之邏輯輸入腳位。位準決定單元7〇由輸 入電路7之輸入端ρΙΝ接收輸入信號ΙΝ，且在第一期間 當致能信號ENJ是高電位時決定輸入信號⑼之電壓^ 準。類比數位轉換單元71接收具有已決定之電壓位準之 輸入信號IN ’且在第-期間内根據輸入信號ΓΝ已決定之 電壓位準將輸入信號ΙΝ轉換為數位信號rs。在接續於 第-期間之第二期間内，拴鎖模組72根據致能信號二 來拾鎖數位信號RS，以作為輸出信號〇UT。根據輪出； 唬OUT，則可判斷輸入端PiN之狀態。 ° 在本發明實施例中，電壓位準根據一參考位準而 分為高電壓位準與低電壓位準，在數位邏輯上，八L 應邏輯向位準與邏輯低位準。 '' 如第7圖所示，輸入電路更包括下拉單元73。下 早兀73耦接於輸入端IN與接地電壓gND之間。在 期間内，當輸入端PlN處於浮接狀態時將，下拉單-二 〇758-A32293TWF2(2〇l〇〇9i3) 16 1342118 第96122496號之專利說明書修正本 修正曰期：99.丨1.8 f輸入端^下拉至接地電遷嶋。輸入電路7還包括 ，序產生早元74，用以產生致能信號EN—】至en—2。致 能信號EN:】與致能信號EN—2具有相反之電壓位準。 、參閱第7圖，位準決定單元70包括開關7〇3及70d 以及電阻器70b及70C。開關7〇3及7〇由控制信號en】 f㈣°電口鳥與開關70a以串聯的方式轉接於供 电電塵VBA丁與輸入端&之間。電阻器7〇c與開關· 、串如的方式耦接於輸人# Pi、與接地電 之間。 在此實施例中，電阻器鳥及7〇c之電阻值相等。 參閱第7圖’類比數位轉換器71包括比較器川及 川’以及分壓器、71e。分壓器71e耗接於供電電麼〜丁 與接地電壓GND之間，且在第—期間由致能信號服i 控制而產生閾值電壓彻」及VTH」。分屢器川包括 開關7!d、以及電阻器71e至71g。電阻器…至^以 串聯的方式耗接於供電電壓Vba丁與接地電壓㈣之 間。開關7ld㈣致能信號EN」的控制。間值電麻 VTH」產生於介於電阻器〜與爪間的節點Ν7^，而 閾值電壓VTH—2產生於介於電阻器7]f與7】g間的節點 N7Ib。比較器、71a由非反向端⑴接收信们N，且由 ^向端（-)接收閾值電屋VTHJ。比較器&比㈣入 信號IN已決定之電壓位準與閾值電壓仰—卜並根 較結果產生結果信號RSJ。比較器71b由非反向端 接收信號IN，且由反向端（)接㈣值電壓 較器7lb比較輸入信號⑽已決定之電麼位準與閾值電墨 0758-A32293TWF2i20I00913) 1342118 修正日期：99.11.8 第96122496號之專利說明書修正本 VTH_2，並根據比較結果產生結果信號RS—2。結果信號 RS_i與結果信號Rs—2結合成為數位信號Rs。在此實旃 例中，結果信號RS—；!及Rs—2中每一者佔有】位元，因 此數位信號RS具有佔有2位元。 拴鎖模組72包括拴鎖器72a及72b。拴鎖器72a接 收來自比較器71a之結果信號RSJ，並在第二期間内根 據致能信號EN—2來㈣結果㈣RS」，以作為拾鎖信 唬outj。拴鎖器72b接收來自比較器7]b之結果信號 RS_2，並在第二期間内根據致能信號EN—2來拴鎖結果 信號RS—2，以作為拴鎖信號〇UT_2。拴鎖信號〇UTj 與0UT_2結合成為輸出信號〇υτ。在此實施例中，拾鎖 信號OUT—UOU丁—2中每一者估有！位元， 出 信號佔有2位元。 下拉單元73包括電阻器73a、開關7补及73c、以 及互斥或閘（X〇R) 73d。電阻器73a與開關7扑及73c 以串聯方式耦接於輸入端PIN與接地電壓GND之間。互 斥或閘73d接收拴鎖信號out—〗及〇υτ—2，並產生致处 信號ΕΝ—3。_ 73b受致能信號既2控制，且開關^ 受致能信號ΕΝ一3控制。 —輸入電路7之操作將配合第7及2圖來說明。在此 貫施例中’所有的開關根據高電壓位準信號而導通，且 根據低電壓位準信號而關閉。 參閱第2圖，在第一期間ρ」，供電電壓I丁由 始上升且具有高電壓位準’致能信號隨著供電電壓 ()758-A32293TWF2(201 ⑽ 913) 18 U42118 第96122496號之專利說明書修正本 修正日期·· 99.11.8 vBAT而上升。當致能信號EN—】到達高電壓位準時，開 關7〇a及70d導通。假使輸入端4處於浮接㈣，由於 電阻器7〇b與70c具有相同之電阻值，輸入信號IN之電 壓位準被拉至介於供電電壓I丁與接地電壓G肋間的 中間電壓。位準決定單元7〇因此決定輸入信號W之電 壓位準為中間電壓位準。同時，開關7]d導通，因此可 電壓VTH乂大於閣值·则―2。由於閲值電 ^ —大於輸入號1N之電壓位準，比較哭71a產 生低電壓位準之社果俨轳7丄 產 + 唬RSJ。由於輸入信?虎rN之電 壓位準大於閾值電壓VTH 2， 準之結果信號RS—2。— 產生而電壓位 當供電電壓vBAT上升至—既定電璧（例如2 知’致能信號ΕΝ 1切換至低兩厭仞.、隹α ^ "堡位準，且致能信號 電壓位#。茶閱第2圖’致能信號en】切換至 的Γ標號”TP，，來標記，且在時間TP之後 的期間柄為弟二期間Ρ_2。在第二期間ρ 及725被高電壓位準之致能信號ΕΝ2觸發。射：： 接收並拴鎖低電璧位準 -觸《，72a 轳οπτ 1 子果I，以作為拾鎖信 #〇 outj。拴鎖器 72b 號RS—2,以作為备鎖㈣丁拾2鎖;;以位準之結果信 準之栓鎖信號⑽丁因此，根據低電壓位 J断出輸入鳊ΡΙΝ處於浮接狀態。 — 此在第二期間ρ—2 ’互斥或閘 位準之拾鎖……高電壓位準之；^ 0758-A32293TWF2(2〇I(I〇913) 1M2118 第96122496號之專利說明書修正本 修正日期：99.】1.8 二生高電壓位準之致能信號EN」。開關心 被：電壓位準之致能信號EN—2導通，且開關73。高電厭 :準之致能信號EN-3導通。因此，輸入端〜下拉至： 地電壓GND，避免輸入端PiN浮接。 —假使輸入端Pin處於低邏輯狀態，在第一期間p ^， 輸入信號IN處於低電屢位準。位準決定單& 7〇因此決 疋輸入信號IN為低電壓位準。根據上述類比數位轉換單 凡71與拾鎖模組72之操作，在第二期間p 2，拾鎖哭 仏拴鎖低電壓位準之結果信號心以作為拾鎖信二 〇UTj ’且拴鎖器72b拴鎖低電壓位準之結果信號= 以作為拾鎖#號0UT_2。因此，根據低電壓 <立準之掩鎖 信號OUT—1及0UT—2 ’可判斷出輸入端p“於低邏輯 以相同之操作，假使輸入端Pin處於高邏輯狀態， 拴鎖72a拴鎖高電壓位準之結果信號RS—1以作為拴鎖 信號OUTJ’且拴鎖器72b拴鎖高電壓位準之結果信號 RS—2以作為拴鎖彳s號out—2。因此，根據高電壓位準之 拴鎖信號0UT—1及0UT_2，可判斷出輸入端心處於言 邏輯狀態。 在輸入端P1N處於低邏輯狀態與高邏輯狀態的情況 下，由於互斥或閘73d接收皆具有高/低電壓位準之拴鎖 信號0UT_1及〇UT_2 ’互斥或閘73d則產生低電壓位準 之致能信號EN—3，以關閉開關73c。因此下拉單元73處 於閒置狀態。 °处 〇758-A32293TWF2(20100913) 20 ΙΟ 第96丨22496號之專利說明書修正本Ldt K乍 is the output signal 〇1] D Because the switch (3) is also turned off by the enable signal 2, the level maintaining unit 12 is inactive. Φ & When the reference ink V is raised to a predetermined voltage (for example, 2.7V), the enable signal ΕΝ-1 is switched to the low voltage level to turn off the switching gamma, and the signal EN_2 is switched to the high voltage level to Turn on the switch (1). The time when the 'enable signal εν' is switched to the low voltage level in Fig. 2 is indicated by 'marker τρ', and the period after the time TP is referred to as the second period Ρ-^. . During the second period Ρ_2 'the high voltage level of the turn-in signal 被 is latched by the inverted states 11a and lie, and the input with the high voltage level • the signal 输出 is output through the reverser mountain and the claw The output terminal Ρ〇υτ is used as the output signal OUT. Therefore, according to the high voltage bit OUT, it can be judged that the input terminal PiN is in a floating state. ;u In addition, during the second period P_2, the first path is turned off by the switch 1〇a. Since the switches 2a and 12b are respectively turned on by the output signal (4) and the enable signal ΕΝ-2, a second path is formed between the reference voltage VREF and the input terminal P1N in the level maintaining unit u. This second path will input the signal IN, and the voltage value of the high power level will be slightly increased to prevent the voltage value of the high voltage level of the input signal from being disturbed by noise. 0758-A32293TWF2(20l〇〇913) 1342118 Patent Specification No. 96922496 Revision of this revision period: 99.11.8 In the first period P_], if the input terminal P1N is in a low logic state, the input k number IN is low. Voltage level. The level determining unit 1 determines the input signal IN to be a low voltage level. Since the switch n d is turned off by the enable signal EN_2, the input signal m having a low voltage level is output to the output terminal Ρ〇υτ through the inverters 11a and lib as the output signal out. The switch whose second path is closed] 2b is cut off, so the level maintaining single το 12 is in an idle state. Since the switch 1 Oa ' leakage current of the p-turn conduction during the first period is generated in the first path. Then, in the second period P-2, EN_〗 switches to a low voltage level to turn off the switch]Oa. The first path is thus cut off and no leakage current flows through the first path. The enable letter f tiger EN-2 is switched to a high voltage level, to turn on the switch lid' input signal IN low voltage level is reversed by the mountain and ... check lock, and has a low voltage level of the input money _ Through the reverser mountain and lib output to the output terminal Ρ〇υτ as an output signal ο· Therefore, according to the low, pressure level output signal 〇υτ, it can be determined that the input terminal is in a low logic state. 4, in the second period Ρ-2, because the switch 12a is outputted by the low voltage bit f _, (4) the special unit U is also in the idle = two f standard, the second brother and the first path are cut Broken, so there is no leakage. In some embodiments, a considers the floating state and the high logic state, the ground voltage of one or two state voltage levels is said; the second power 7:: has a low input signal, and the pass level determines the single = The state of the loser is the path of the younger brother, and according to 〇 758-A32293TWF2 (20100913), 96122496, the specialization of the 3rd turn, the correction of this 9612496, the specialization of the 3rd turn, the correction date: 99.11.8 > test voltage VREF low. Bit. The number IN is the low voltage level. If the input signal 1...1〇 is determined, the input signal is determined to be a high voltage level. The above-mentioned 'enable signal ΕΝ 1 and EN ? 夕 chain ρ private shot 4 electric voltage depends on. Figure 3 扦 _ 钤 钤 钤 钤 你 你 你 你 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据卜 _ 包 包 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压The voltage divider 31 includes an electric two-two, or a gate 35, and an anti-^, resistors 31a and 31b. The comparing unit 32 includes a comparator 323 and a type of positive and negative 32b inverse 32b, wherein the D-type flip-flop is driven by a falling edge, and generates an initial low voltage level. — - 彳d produces a control with a low voltage level initially 虎5虎 CS 2. Voltage production; ^. ·1ώ ΙΑ· 撼徂Φ + House Eco J〇 receives the supply voltage VBAT, and the root and electric voltage VBAT generate the voltage V_〗. In this embodiment, the voltage is produced by a bandgap voltage generator (bandgap V. 丨tage gene). In the voltage divider 3], the resistors 31a and 3ib are connected in series between the supply voltage Vba and the ground voltage GND. The voltage divider 3] generates a voltage V-2 according to a predetermined ratio between the supply voltage Vbat and the ground voltage gnd. The predetermined ratio is determined according to the resistance values of the resistors 31a and 31b. The non-inverting terminal (+) of the device 32a is connected to the electric terminal V~], and the opposite end (-) receives the electric house γ-2. Assume that the supply voltage is slowly rising, for example, the rise time is less than one (four) (ms), as shown in Figure 4. The comparator 32a compares the voltages vj and v_2, and the maternal 彳 唬 5 唬 Rs, and changes the result C of the result signal RS according to the comparison result to receive the result signal RS, and the other end receives 0758-A32293TWF2f20l〇 〇9i3) 1342118 Revision period: 99.11.8 The patent specification of No. 96122496 is amended. During the first period PJ 'just' voltage V-1, comparator 32, will result in signal heart; low; pressure level. Then, electric dust V-2 becomes less than voltage: low private, the result signal RS is changed to high Voltage bit—t#parent; 32a The ink level becomes a high voltage level, because D = : the transition state will change state, the control signal CSJ is maintained at low ink - there is = 35 reception has low power bunker Precise control (4) (1) and 2: Output selection signal with low voltage level - then output #雪雷厌v 5 to evening working state 34. Multiplexer ί as the enable signal EN-"in other words ^, The chirp signal rises with the supply voltage V - r-. The inverter 3" acknowledges and activates the enable signal EN9 of the reverse enable signal (9) as the enable signal to capture 2: turn the reverse Μ = (4) TP, that is, during the second period [2, the voltage V 2 is slightly Greater than the voltage VI. In the rainy skull, "1", comparator 32: the two-two result letter (four) is changed from the high voltage level. Since the signal RS produces - er, then the result is controlled and the signal cs i P is powered (10) Wide. 32 is therefore triggered, or the gate % receives a high dust level": becomes a high level. The voltage level control is used as the system of 轳d (4) cs" and has a low signal ss output to m-2'/ which will have a high power plant firmness. The result signal is more: then the low power relay signal EN is output. —] In the supply voltage ... to:: mouth. Therefore, the enable level becomes the low voltage level 2 = (four)" by the high power. 36 receiving the sub-reverse low voltage level 〇 758-A32293TWF2 (20! 〇〇 9i3) 14 1342118 Revision period: 99.11.8 The patent specification of 苐96122496 modifies the enable signal EN] of the standard, and the 人g person enables the signal ΕΝ2^ί f to enable the signal to be used as the voltage level. When timing / 3 ^ = system signal CS - 2 initially has a low on-time 'timer to change the control signal cs-2 to high =. The multiplexer 34 outputs the resulting signal rs as a enable supply voltage V. Also, main, i to the voltage generator 3. "=:: Figure 5 shows that 'by pressure' is always greater than the electric tank's rapid rise, electric + r voltage V-1. Comparator 32a has been producing the peak value of the position of the standard signal to ~ type positive Counter % is = always at low voltage level. or = Receive white control signal with low voltage level cs] :! Pressing level selection signal % output to multiplexer; 4. Multiplex. 4 = output power supply The voltage Vbat is used as the enabling signal (4): 3 electric voltage, equal to the calling signal ΕΝ-〗 will not be two I:: quasi; level. In this case, the timer A control; ^ ” 3 3 arrival time ,, timer 3 3 directly two ": change to high voltage level" so that the multiplexer outputs the result as the enable signal ΕΝ_1. In the two households, know, The timing generation unit 13 can be simplified. Another embodiment of the middle timing generation unit 13. The timing includes the timer 60 and the inverter 61. The timing is crying: = Nj. When the timer 6 arrives Between the first period and the time Tps between pj 2, the timer 6〇 will enable the signal 0758-A32293TWF2 (2〇i〇〇9i3l 1342118 Revision date: 99.11.8 No. 96丨22496 Patent Specification Amendment 】Change to low power waste level. Inverter 3] Receive and reverse enable signal ENU 'and output the reverse enable signal both] as the enable signal EN_2. When the input circuit 1 is applied to the integrated circuit % ' 致 / 匕 吕 EN EN EN 1 and EN _2 are generated from the inside of the integrated circuit. • Fig. 7 shows the input circuit of the embodiment of the present invention, which can be judged The three states of the ^ terminal, namely the floating state, the high logic state, and the low avoidance H are as shown in Fig. 7' The human circuit 7 includes a level determining circuit 7A, an analog digital converting unit 71, and a shackle module 72. The input terminal may be a logic input pin of the integrated circuit. The level determining unit 7 is input from the input circuit 7. ΙΝ receiving the input signal ΙΝ, and determining the voltage of the input signal (9) when the enable signal ENJ is high during the first period. The analog digital conversion unit 71 receives the input signal IN ' having the determined voltage level and is in the - During the period, the input signal ΙΝ is converted to a digital signal rs according to the determined voltage level of the input signal 。. During the second period following the first period, the shackle module 72 picks up the digital signal RS according to the enable signal 2 as the output signal 〇UT. According to the round out; 唬OUT, the state of the input terminal PiN can be judged. In the embodiment of the present invention, the voltage level is divided into a high voltage level and a low voltage level according to a reference level, and in the digital logic, eight L should be a logical level and a logic low level. As shown in FIG. 7, the input circuit further includes a pull-down unit 73. The lower early turn 73 is coupled between the input terminal IN and the ground voltage gND. During the period, when the input terminal P1N is in the floating state, the pull-down single-two-turn 758-A32293TWF2 (2〇l〇〇9i3) 16 1342118 Patent No. 96922496 is amended. The revision period: 99.丨1.8 f The input terminal ^ is pulled down to the grounding current. The input circuit 7 further includes an order generating early element 74 for generating the enable signals EN_] to en-2. The enable signal EN:] has an opposite voltage level to the enable signal EN-2. Referring to FIG. 7, the level determining unit 70 includes switches 7〇3 and 70d and resistors 70b and 70C. The switches 7〇3 and 7〇 are switched between the power supply electric dust VBA and the input terminal & in a series connection by the control signal en] f(d). The resistor 7〇c is coupled between the input #Pi and the grounding power in a manner of a switch and a string. In this embodiment, the resistance values of the resistor bird and 7 〇c are equal. Referring to Fig. 7, the analog-to-digital converter 71 includes a comparator Chuanchuan and a voltage divider, 71e. The voltage divider 71e is consumed between the power supply voltage and the ground voltage GND, and is controlled by the enable signal to generate the threshold voltage "VTH" and "VTH" during the first period. The relay device includes a switch 7!d and resistors 71e to 71g. The resistors ... to ^ are connected in series between the supply voltage Vba and the ground voltage (4). The switch 7ld (four) enables the control of the signal EN". The interim value VTH is generated from the node Ν7^ between the resistors and the claws, and the threshold voltage VTH-2 is generated at the node N7Ib between the resistors 7]f and 7]g. The comparator, 71a receives the signal N from the non-inverting terminal (1), and receives the threshold electric house VTHJ from the terminal (-). Comparator & (4) Incoming signal IN has determined the voltage level and threshold voltage — 卜 根 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The comparator 71b receives the signal IN from the non-inverting terminal, and compares the input signal (10) by the reverse terminal () to the voltage value comparator 7lb. The level of the signal is determined by the threshold signal and the threshold ink 0758-A32293TWF2i20I00913) 1342118 Revision date: 99.11 .8 Patent Specification No. 96122496 modifies this VTH_2 and produces a resulting signal RS-2 based on the comparison. The resulting signal RS_i is combined with the resulting signal Rs-2 to become a digital signal Rs. In this example, each of the resulting signals RS_;! and Rs-2 occupies a bit, and thus the digital signal RS has 2 bits. The shackle module 72 includes latches 72a and 72b. The latch 72a receives the result signal RSJ from the comparator 71a, and (4) the result (4) RS" according to the enable signal EN-2 in the second period as the pickup signal 唬outj. The latch 72b receives the resultant signal RS_2 from the comparator 7]b and latches the resultant signal RS-2 according to the enable signal EN-2 during the second period as the shackle signal 〇UT_2. The shackle signal 〇UTj is combined with OUT_2 to become the output signal 〇υτ. In this embodiment, each of the pickup signal OUT-UOU D-2 is estimated! The bit, the outgoing signal occupies 2 bits. The pull-down unit 73 includes a resistor 73a, a switch 7 complement 73c, and a mutual exclusion or gate (X〇R) 73d. The resistor 73a and the switch 7 are coupled to the 73c to be coupled in series between the input terminal PIN and the ground voltage GND. The mutex or gate 73d receives the shackle signals out-〗 and 〇υτ-2, and generates a causative signal ΕΝ-3. _ 73b is controlled by both the enable signal and the switch ^ is controlled by the enable signal ΕΝ3. - The operation of the input circuit 7 will be explained in conjunction with Figures 7 and 2. In this embodiment, all of the switches are turned on according to the high voltage level signal and turned off according to the low voltage level signal. Referring to Figure 2, during the first period ρ", the supply voltage I is raised from the beginning and has a high voltage level 'enable signal' with the supply voltage () 758-A32293TWF2 (201 (10) 913) 18 U42118 No. 96122496 The manual amends this revision date · 99.11.8 vBAT and rises. When the enable signal EN_] reaches the high voltage level, the switches 7〇a and 70d are turned on. If the input terminal 4 is floating (four), since the resistors 7〇b and 70c have the same resistance value, the voltage level of the input signal IN is pulled to an intermediate voltage between the supply voltage I and the ground voltage G rib. The level determining unit 7 thus determines the voltage level of the input signal W to be the intermediate voltage level. At the same time, the switch 7]d is turned on, so the voltage VTH 乂 is greater than the value of the threshold. Since the reading value ^ - is greater than the voltage level of the input number 1N, the comparison of the crying 71a produces a low voltage level of the fruit 俨轳 7 丄 production + 唬 RSJ. Since the input voltage of the tiger rN is greater than the threshold voltage VTH 2, the result signal RS-2 is accurate. – Generated and voltage level when the supply voltage vBAT rises to – the established power (for example, 2 knows that the enable signal ΕΝ 1 switches to the low two, 隹α ^ " Fort level, and the enable signal voltage bit #. The tea is referred to in Fig. 2, the enablement signal en is switched to the Γ, TP, to mark, and the period after the time TP is the second period Ρ_2. During the second period, ρ and 725 are high voltage level. Enable signal ΕΝ2 trigger. Shoot:: Receive and lock low power - level - touch ", 72a 轳οπτ 1 fruit I, as the pickup letter #〇outj. 拴 locker 72b number RS-2, as The backup lock (4) picks up the 2 locks; the latch signal (10) is corrected according to the result of the level. Therefore, according to the low voltage bit J, the input 鳊ΡΙΝ is in a floating state. — This is the second period ρ — 2 '斥 or brake position lock... high voltage level; ^ 0758-A32293TWF2 (2〇I (I〇913) 1M2118 Patent No. 96922496 revised this revision date: 99.] 1.8 two high voltage The enable signal EN". The switch core is: the voltage level enable signal EN-2 is turned on, and the switch 73. High power disgust: the standard letter No. EN-3 is turned on. Therefore, the input terminal ~ pulls down to: ground voltage GND to avoid floating at the input terminal PiN. - If the input pin Pin is in a low logic state, during the first period p ^, the input signal IN is in a low power bit position. Therefore, the level decision sheet & 7 is therefore determined that the input signal IN is at a low voltage level. According to the operation of the above analog digital conversion unit 71 and the pickup module 72, during the second period p 2, the lock is cried. The result signal of the shackle low voltage level is used as the pickup signal 〇 〇 〇 〇 〇 拴 拴 拴 拴 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 结果 结果 结果 结果 结果The default latching signals OUT-1 and OUT_2' can be judged that the input terminal p "operates in the same logic in the low logic. If the input pin is in the high logic state, the latch 72a locks the high voltage level result signal RS. -1 as the shackle signal OUTJ' and the shackle 72b locks the high voltage level result signal RS-2 as the 拴 lock 彳 s number out - 2. Therefore, according to the high voltage level shackle signal OUT - 1 and 0UT_2, it can be judged that the input end is in the logic state. At the input end P1N In the case of low logic state and high logic state, the shackle signals OUT_1 and 〇UT_2 'mutual exclusion or gate 73d, which have high/low voltage levels, are generated by mutual exclusion or gate 73d to generate low voltage level. The signal EN-3 is used to close the switch 73c. Therefore, the pull-down unit 73 is in an idle state. 〇 〇 758-A32293TWF2 (20100913) 20 ΙΟ Amendment of the patent specification No. 96丨22496
修正S期：99.Π.S 在此實，中，時序產生單元”可以第3圖之時序 屋生單几13或是第6m夕π士 r- β -些實施例中，當輸入電二產生單元13，，來實現。在 ^ ψ ΕΝ ! ώ t 7應用於積體電路時，致能 仏虎EN—]與EN_2由積體電路之内部產生。 本發明雖以較佳實施例揭露如上铁並並 :本：明的範圍，任何所屬技術領域中具有通常知識 :與 範圍所界定者為準。圍s視後附之申請專利 【圖式簡單說明】 第1圖表不本發明實施例之輸入電路，其可判斷輸 入端之兩個狀態；Correction S period: 99. Π.S In this real, medium, timing generation unit" can be the sequence of the third picture of the housing list 13 or 6m π 士r-β - in some embodiments, when inputting electricity The generating unit 13 is implemented. When ^ ψ ΕΝ ! ώ t 7 is applied to the integrated circuit, the enabling of the EN EN EN EN] and EN _2 are generated by the inside of the integrated circuit. The present invention is disclosed in the preferred embodiment as above. The combination of the following is not the scope of the present invention. An input circuit that can determine two states of the input terminal;
Vref、致能信號ΕΝ 1 第2圖表示第I圖中參考電壓 與EN—2間之關係； $ 3圖表示第】圖中時序產生單元之實施例； 第4圖表示當供電電壓VBAT緩慢地上升時供電電壓 VBAT與致能信號en J間之關係； 第5圖表示當供電電壓VBA·^^速地上升時供電電壓 VBAT與致能信號ENJ間之關係； 第6圖表不第1圖中時序產生單元之另一實施例； 以及 ' 第7圖表示本發明實施例之輸入電路，其可判斷輸 入端之三個狀態。 0758-A32293TWF2f20,()09l3) ^^118 ^^118 開關； 類比數位轉換單元 電阻器； 互斥或閘； 70b 、 7〇c 71a、71b 71 d〜開關； 電阻器；72〜拴鎖模組 73〜下拉單元； 73b、73c〜開關 74〜時序產生單; 第96122496號之專利說明書修正本 【主要元件符號說明】 1〜輸入電路； 10a〜開關； Π〜輸出單元； lid〜開關； 12a、12b〜開關； 13〜時序產生器； Pin〜輸入端； 13’〜時序產生器； 3 1〜分壓器； 32〜較單元； 32b〜D型正反器； 34〜多工器； 36〜反向器； 60〜計時器； 7〜輸入電路； 70a、70d〜 71〜 71c〜分壓器； 71e、71f、71g〜 72a、72b〜拴鎖器； 73 a〜 73d〜 修正日期：99.11.8 10〜位準決定單元； 10b〜電阻器； lla ' lib ' l]c〜反向器 12〜位準維持單元； 12c〜電阻器； N11〜節點； Ρ〇υτ輸出端； 3〇〜電壓產生器； 31a、31b〜電阻器； 32a〜比較器； 33〜計時器； 35〜或閘； 13”〜時序產生單元； 61〜反向器； 7 0〜位準決定電路； 〜電阻器； 〜比較器； 0758-A32293TWF2C20100913) 22 1342118 . 第96122496號之專利說明書修正本 修正日期：99.11.8 N 71 a、N 71 b〜節點； Ρ ι n〜輸入端； Ρ〇υτ〜輸出端。Vref, enable signal ΕΝ 1 Figure 2 shows the relationship between the reference voltage and EN-2 in Figure I; $3 shows the embodiment of the timing generation unit in the figure; Figure 4 shows the supply voltage VBAT slowly. The relationship between the supply voltage VBAT and the enable signal en J when rising; FIG. 5 shows the relationship between the supply voltage VBAT and the enable signal ENJ when the supply voltage VBA·^^ is rapidly increased; FIG. 6 is not in FIG. Another embodiment of the timing generation unit; and 'Fig. 7 shows an input circuit of an embodiment of the present invention, which can determine three states of the input. 0758-A32293TWF2f20,()09l3) ^^118 ^^118 Switch; analog digital conversion unit resistor; mutual exclusion or gate; 70b, 7〇c 71a, 71b 71 d~ switch; resistor; 72~ shackle module 73~ pull-down unit; 73b, 73c~ switch 74~ timing generation list; Patent Specification No. 96122496 [Revision of main component symbols] 1~ input circuit; 10a~ switch; Π~ output unit; lid~ switch; 12a, 12b~switch; 13~ timing generator; Pin~ input; 13'~ timing generator; 3 1~ voltage divider; 32~ comparator unit; 32b~D type flip-flop; 34~ multiplexer; Inverter; 60~timer; 7~input circuit; 70a, 70d~71~71c~ voltage divider; 71e, 71f, 71g~72a, 72b~ 拴 locker; 73 a~ 73d~ Revision date: 99.11. 8 10~ level determining unit; 10b~ resistor; lla 'lib 'l]c~inverter 12~level maintaining unit; 12c~resistor; N11~node; Ρ〇υτ output terminal; 3〇~voltage Generator; 31a, 31b~ resistor; 32a~ comparator; 33~ timer; 35~ or gate; 13"~ Sequence generating unit; 61~inverter; 7 0~bit determining circuit; ~resistor;~comparator; 0758-A32293TWF2C20100913) 22 1342118. Patent specification No. 96222496 Revision date: 99.11.8 N 71 a , N 71 b~ node; ι ι n~ input; Ρ〇υτ~ output.
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23 0758-A32203TWF2(20100913)23 0758-A32203TWF2 (20100913)