九、發明說明： 【發明所屬之技術領域】 本I明係關辦脈訊號處理，尤指_麵比解比㈣，其依據 電壓來设定一内部頻率並比較一外部頻率和該内部頻率、一種 '員率s成$ ’其採用該鮮比m來合成―時脈訊號，以及相關 方法。 【先前技術】 在積體電路m域巾，—外接式的接购in)係常常被用 來接收外。(5時脈’其中該外部時脈具有與一内部所產生的時脈 :不同的頻率，因此，積體電路必須是可以判斷出内部時脈和外 部時脈之二頻率，以及決定那—個時脈被選作為誠電路所需的 時脈。在習知領域中’―相位頻率偵·、—計數器以及複數個 ，位邏輯即可組合出—頻率娜器，其_來決定—電路内部所 需之頻率的日械訊號’㈣’㈣她鮮_器、該計數器以 及該複數個數位邏輯所組合成_率選擇^會烟積體電路之大 部份面積，因而提高了積體電路的製造成本。 請參考第1圖，第i圖所示係習知頻率比較器1〇的示意圖。 習知頻率比較器⑴包含有一頻率偵測電路11、一第一計數電路 12、一第二計數電路13以及-判斷邏輯14。當—第—時脈訊號加 和一第二時脈訊號IN2同時輸人至頻率偵測電路u時，對應於第 -時脈訊號抓和第二時脈訊號in2之一第一重置訊號咖^和 1331448 • 一第二重置訊號航2會分別被傳送至第一計數電路12和第二計 數電路，接著，第-重置訊#uRSTl和第二重置訊敍阳會 分別重置第-計數電路12以及第二計數電路13以開始分別計數 . 第一時脈訊號IN1和第二時脈訊號IN2之時脈週期。若第一時脈 • 訊號1N1之鮮係比第二時脈訊號IN2之頻率來得㈣，一溢出 訊號on會被輸出，接著，另一溢出訊號0F2亦會被輸出。溢出 訊號OFb OF2會被輸出至判斷邏# 14，最後，判斷邏輯14便會 φ 依據溢出訊號0F1、OF2輸出一狀態訊號來顯示第一、第二時脈 訊號im、in2之頻率關係。請參考美國專利號6_9浙，其係 揭露另-種習知的頻率比較器，其詳細内容於此不另費述。 另一方面，在積體電路接收一外部頻率時，積體電路需要用 該外部頻率來合成複數個任意頻率之訊號，或者積體電路需利用 該外部頻率來提供複數個時脈訊號，且該複數個時脈訊號具有不 -樣之相位’因此，—頻率合成减—頻率乘法器便亦需建立在 ®積體電路内。 【發明内容】 因此本發明的目的之一係在於提供一種類比頻率比較器，其 依據一電壓來設定一内部頻率以及比較一外部頻率和該内部頻 率、一種頻率合成器，其採用該頻率比較器來合成一時脈訊號， 以及相關方法。 1331448 ^ 本發明之一實施例提供了一種頻率比較器，用來比較一第一 訊號和一第二訊號之頻率。該頻率比較器包含有一頻率偵測電 路、一頻率產生器、一電荷泵電路以及一判斷邏輯耦。該頻率偵 測電路用來依據該第一訊號和一輸入電壓來產生一參考訊號；該 頻率產生器用來依據該輸入電壓來產生該第二訊號；該電荷泵電 路耦接於該頻率偵測電路和該頻率產生器，用來依據該參考訊號 和該第二訊號中之一訊號來致能一充電電流以提高一電壓位準， • 以及用來依據該參考訊號和該第二訊號令之另一訊號來致能一放 電電流以減低該電壓位準；以及該判斷邏輯耦接於該電荷泵電 路’用來依據該電壓準位來決定該第一訊號和該第二訊號之頻率 之間的一頻率關係。 本發明之另一實施例提供了一種頻率合成器，用來依據一第 一訊號來產生一第二訊號。該頻率合成器包含有一頻率偵測電 路、一頻率產生器、一電荷泵電路以及一調整電路。該頻率偵測 電路用來依據該第一訊號和一第一輸入電壓來產生一參考訊號； 該頻率產生器用來依據一第二輸入電壓來產生該第二訊號；該電 荷系電路耦接於該頻率偵測電路和該頻率產生器，用來依據該參 考訊號和該第二訊號中之一訊號來致能一充電電流以提高一電壓 位準，以及用來依據該參考訊號和該第二訊號十之另一訊號來致 能一放電電流以減低該電壓位準；以及該調整電路耦接於該電荷 栗電路、該頻率偵測電路以及該頻率產生器，用來依據該電壓準 位來調整該頻率偵測電路以及該頻率產生器，以調整該參考訊號 8 1331448 、 和該第二訊號之頻率。 本發明之另一實施例提供了一種頻率比較方法，用來比較一 第一訊號和一第一訊號之頻率。該頻率比較方法包含有:依據該第 ' —訊號和一輸入電壓來產生一參考訊號；依據該輸入電壓來產生 該第二訊號；依據該參考訊號和該第二訊號中之一訊號來致能一 充電電流以提高一電壓位準，以及依據該參考訊號和該第二訊號 Φ 中之另一訊號來致能一放電電流以減低該電壓位準；以及依據該 電壓準位來決定該第一訊號和該第二訊號之頻率之間的一頻率關 係。 本發明之另一實施例提供了一種頻率合成方法，用來依據一 第一訊號來產生一第二訊號。該頻率合成方法包含有:依據該第一 訊號和一第一輸入電壓來產生一參考訊號；依據一第二輸入電壓 來產生該第二訊號；依據該參考訊號和該第二訊號中之一訊號來 致能一充電電流以提高一電壓位準，以及依據該參考訊號和該第 一§fl號中之另一訊號來致能一放電電流以減低該電壓位準；以及 依據該電壓準位來調整該參考訊號和該第二訊號之頻率。 【實施方式】 在說明書及後續的巾請專·巾使用了某些詞彙來指稱 特定的餅。蘭躺巾具有通常知識者射理解，硬體製造商 可能會用獨的名詞來稱詞—個元件。本說明書及後續的申請 9 丄划丄448 專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件 在功能上的差異來作輕分的準則。在通篇朗#及後續的請求 項當中所提及的「包含」係為—敝式的躲，故應轉成「包 含但不限定於」。以外，「雛」—詞在聽包含任何直接及間接 的電氣連接手段。因此，若文中描述—第—裝置祕於一第二裝 置’則代表該第-裝置可直接電氣連接於該第二裝置，或透過其 他裝置或連接手段間接地電氣連接至該第二裝置。 請參考第2圖，第2圖係本發明頻率比較器1〇〇之一實施例 的示意圖。頻率比較器1〇〇係用來比較一第一訊號&(即一外部時 脈訊號)和一第二訊號S2(即一内部時脈訊號)之頻率，而頻率比較 器100包含有一頻率偵測電路10卜一頻率產生器102、一電荷泵 電路103、一判斷邏輯104以及一偏壓產生器105，其中頻率偵測 電路101係依據第一訊號S!和一輸入電壓VrQse來產生一參考訊號 Sr，頻率產生器102係依據諱輸入電壓Vr〇sc來產生第二訊號&， 電荷泵電路103係耦接於頻率偵測電路ιοί和頻率產生器1〇2，用 來依據參考訊號Sr或第二訊號S2來致能(enable)—充電電流Ic以提 昇一電壓準位Voset;並且用來依據參考訊號Sr和第二訊號&中的 另一個訊號來致能(enable)—放電電流Ide以降低電壓準位v<jset。判 斷邏輯104耦接於電荷泵電路1〇3，其係用來依據由電荷泵電路 103所輸出的電壓準位Voset來分辦第一訊號Si和第二訊號S2之間 的頻率關係；另一方面’偏壓產生器105係耦接於頻率偵測電路 101以及頻率產生器102，用來產生輸入電壓Vrosc。 1331448 、 請注意，在此一實施例中，充電的操作係由參考訊號s所 控制，而放電的操作則是由第二訊號心所控制，然而，此並非為 ， 本發明之限制條件。舉例來說，在本發明之另一設計中，放電操 作可由參考訊號Sr所控制，而充電操作則由第二訊號s所控制'， 而第一訊號3丨和第二訊號S2之間的頻率關係可以依據電壓準位 Voset來加以分辦。 • 以下所述係揭露頻率比較器100之内部元件間的操作。依據 本發明第2圖所揭露之實施例，頻率偵測電路1〇1包含有一第一 銀窗波產生II 1G11以及ϋ較n聰，其中第—織波產生 器1011係耦接於第一訊號Sl以轉換第一訊號Sl至一第一鋸齒波 訊號swl，以及第一比較器1012係耦接於第一鋸齒波訊號心丨和 輸入電壓Vrcs。，絲比較第—職訊號Swi和輸人電壓V咖以產 生參考訊號Sr。第一鋸齒波產生器1011包含有一單一脈波產生電 Φ路1011a、—第一電容C1、一第-電流源I!、-第-開關Wi、-第二開關W2以及一開關控制電路1〇llb，而如第2圖所示，單一 ，波產生電路lGlla係減於第—訊號\，用來於第_訊號^之 每週期產生一單一脈波訊號(onepulsesignai)(m Spi);第一電容 c’輕接於第一麵波產生器應之__輸㈣點％以及一第一 參考電壓vss(即-接地蝴；第—電流源接於—第二參考 電壓vdd(即-電源電虔）；第一開關Wi係輕接於第一電流源心和 第一鑛齒波產生器1011之輸出端點Νι之間，用來依據一第一開 關控制訊號Scl來選擇性地輕接第一電流源L至第一電容C1;第 丄幻1448 、 二開關W2係耦接於第一參考電壓vss和第一鋸齒波產生器1011 之輸出端點N!之間，用來依據一第二開關控制訊號sc2來選擇性 地輕接第一電容〇^至第一參考電壓vss;以及開關控制電路1011b 係耦接於單一脈波產生電路1011a、第一開關w!以及第二開關 W2’用來依據第一單一脈波產生電路l〇lla之一輸出訊號Spl來產 生第一開關控制訊號Scl和第二開關控制訊號Sc2。 φ 請再次參考第2圖’頻率產生器102包含有一第二鋸齒波產 生器1021以及一第二比較器1〇22。第二鋸齒波產生器1〇21係耦 接於第二訊號I以轉換第二訊號S2成為一第二鋸齒波訊號Sw2， 而第二比較器1022係耦接於第二鋸齒波訊號和輸入電壓 vrosc’用來比較第二鋸齒波訊號Sw2和輸入電壓Vr〇sc以產生第二訊 號S2。此外’第二鋸齒波產生器ι〇2ι包含有一第二電容Q、一 第二電流源I2、一第三開關Ws、一第四開關W4以及一開關控制 電路1〇21a，其中第二電容C2係輕接於第二錯齒波產生器1021之 -輸出端點n2和第-參考電慶Vss之間；第二電流源12係輕接於 第二參考電壓Vdd ;第三開關w3係減於第二電流源12和第二鑛 齒波產生益1021之輸出端點n2之間，用來依據一第三開關控制 訊號sc3來選擇性地輕接第二電流源l2至第二電容C2;第四開關 搞接於第二鑛齒波產生器應之輸出端點&和第一參考電 壓vss之間，用來依據一第四開關控制訊號h來選擇性地輛接第 •二電容C2至第一參考電壓、以及開關控制電路1021a係搞接於 第二訊號s2、第三開關w3以及第四開關W4，用來依據由第二鑛 12 -1波產生ϋ臟之輸出端N2所輸㈣第二訊號32來產生第三開 關控制訊號Sc3以及第四開關控制訊號Sc4。 .…此外’判斷邏輯104係輕接於電壓準位卩及-第三參考 賴Vr3以輸出—指示訊號Vid，其侧來指示出第—訊號义和第 二訊號Sk_頻率關係。在本實施例中偏壓產生器1〇5包含 有-電阻Rref以及-參考龍產生電路咖，其中參考電壓產生 鲁電路顧係_於電阻Rref以依據電阻‘之電阻值來設定輸入 電壓Vrosc。請注意，參考電壓產生電路1〇5卜頻率偵測電路1⑴、 頻率產生器102、電荷泵電路103以及判斷邏輯1〇4均係整合於一 單晶片中，而電阻RreH系設置於該單晶片之外部，換句話說，外部 電阻Rref之電阻值可輕易地被調整，而在實際操作上，當電阻Ια 以外接的方式耦接於參考電壓產生電路1〇51時，輸入電壓Vr〇sc 就被设定好了，其中輸入電壓vrosc會決定頻率產生器1〇2所產生 Φ 的第二訊號S2之頻率&。輸入電壓Vr〇sc之設定將於下詳述。 請參考第3圖，第3圖係第1圖所示之偏壓產生器105之一 實施例的示意圖。經由以閉迴路方式所連接之誤差放大器1〇52以 及一傳輸電晶體(pass transistor)，一第四參考電壓Vr4係耦接於電 阻Rref以產生一參考電流Iref，其中Ire产Vr4/Rref。參考電流Iref會接 著被一電流鏡電路1053所複製(mirror)以產生一電流鏡電流 Imirror ’而如熟習此項技藝者所習知的，電流鏡電路1〇53之電流鏡IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to the processing of pulse signals, in particular to the ratio of the surface to the ratio (4), which sets an internal frequency according to the voltage and compares an external frequency with the internal frequency, A 'rate rate s into $' which uses the fresh ratio m to synthesize the - clock signal, and related methods. [Prior Art] In the integrated circuit m-zone, the external connection in) is often used for reception. (5 clocks where the external clock has a different frequency than an internally generated clock; therefore, the integrated circuit must be able to determine the frequency of the internal clock and the external clock, and determine which one The clock is selected as the clock required by the Cheng circuit. In the field of knowledge, 'phase frequency detection, - counter and plural, bit logic can be combined - frequency nano, its _ to decide - circuit inside The required frequency of the Japanese mechanical signal '(4)' (4) her fresh _ device, the counter and the plurality of digital logic are combined into a large area of the NOx selection circuit, thereby improving the manufacturing of the integrated circuit Please refer to Fig. 1. Fig. 1 is a schematic diagram of a conventional frequency comparator 1〇. The conventional frequency comparator (1) includes a frequency detecting circuit 11, a first counting circuit 12, and a second counting circuit. 13 and - judgment logic 14. When the -th clock signal plus a second clock signal IN2 is simultaneously input to the frequency detection circuit u, corresponding to the first-clock signal capture and the second clock signal in2 a first reset signal coffee ^ and 1331448 • one The second reset signal will be transmitted to the first counting circuit 12 and the second counting circuit, respectively, and then the first-reset signal #uRST1 and the second reset signal will reset the first-counting circuit 12 and The second counting circuit 13 starts to respectively count the clock cycles of the first clock signal IN1 and the second clock signal IN2. If the first clock signal 1N1 is less than the frequency of the second clock signal IN2 (4) An overflow signal on will be output, and another overflow signal 0F2 will be output. The overflow signal OFb OF2 will be output to the judgment logic #14. Finally, the judgment logic 14 will output φ according to the overflow signals 0F1 and OF2. The status signal indicates the frequency relationship between the first and second clock signals im and in2. Please refer to U.S. Patent No. 6_9, which discloses another conventional frequency comparator, the details of which are not described herein. On the other hand, when the integrated circuit receives an external frequency, the integrated circuit needs to use the external frequency to synthesize a plurality of signals of any frequency, or the integrated circuit needs to use the external frequency to provide a plurality of clock signals, and the Multiple time signals Therefore, the frequency synthesis subtraction-frequency multiplier also needs to be built in the integrated circuit. [Invention] Therefore, one of the objects of the present invention is to provide an analog frequency comparator. An internal frequency is set according to a voltage, and an external frequency and the internal frequency are compared, a frequency synthesizer is used to synthesize a clock signal, and a related method. 1331448 ^ An embodiment of the present invention provides a The frequency comparator is configured to compare the frequencies of a first signal and a second signal. The frequency comparator includes a frequency detecting circuit, a frequency generator, a charge pump circuit and a determining logic coupling. Generating a reference signal according to the first signal and an input voltage; the frequency generator is configured to generate the second signal according to the input voltage; the charge pump circuit is coupled to the frequency detecting circuit and the frequency generator The method is configured to enable a charging current according to one of the reference signal and the second signal to increase a voltage level. And activating a discharge current to reduce the voltage level according to the reference signal and the other signal of the second signal; and the determining logic is coupled to the charge pump circuit to be used according to the voltage level Determining a frequency relationship between the first signal and the frequency of the second signal. Another embodiment of the present invention provides a frequency synthesizer for generating a second signal based on a first signal. The frequency synthesizer includes a frequency detecting circuit, a frequency generator, a charge pump circuit, and an adjusting circuit. The frequency detecting circuit is configured to generate a reference signal according to the first signal and a first input voltage; the frequency generator is configured to generate the second signal according to a second input voltage; the charge system is coupled to the The frequency detecting circuit and the frequency generator are configured to enable a charging current to increase a voltage level according to one of the reference signal and the second signal, and to use the reference signal and the second signal according to the reference signal and the second signal Another signal of ten is used to enable a discharge current to reduce the voltage level; and the adjustment circuit is coupled to the charge pump circuit, the frequency detection circuit and the frequency generator for adjusting according to the voltage level The frequency detecting circuit and the frequency generator adjust the frequency of the reference signal 8 1331448 and the second signal. Another embodiment of the present invention provides a frequency comparison method for comparing the frequencies of a first signal and a first signal. The frequency comparison method includes: generating a reference signal according to the first signal and an input voltage; generating the second signal according to the input voltage; and enabling the signal according to the reference signal and the second signal a charging current to increase a voltage level, and a discharging current according to the other of the reference signal and the second signal Φ to reduce the voltage level; and determining the first according to the voltage level A frequency relationship between the signal and the frequency of the second signal. Another embodiment of the present invention provides a frequency synthesizing method for generating a second signal according to a first signal. The frequency synthesizing method includes: generating a reference signal according to the first signal and a first input voltage; generating the second signal according to a second input voltage; and according to the reference signal and one of the second signals Enabling a charging current to increase a voltage level, and enabling a discharging current to reduce the voltage level according to the reference signal and another signal in the first §fl; and according to the voltage level Adjust the frequency of the reference signal and the second signal. [Embodiment] In the specification and subsequent towels, some words are used to refer to a specific cake. The blue lying towel has the usual knowledge to understand, and the hardware manufacturer may use the unique noun to refer to the word-component. This manual and subsequent applications 9 丄 丄 448 The patent scope does not use the difference in name as the way to distinguish the components, but the criterion for the lighter division of the components in terms of functional differences. The "contains" mentioned in the article "Land" and the subsequent requests are "hidden" and should be converted to "including but not limited to". In addition, the word "catch" - the word contains any direct and indirect electrical connection means. Thus, if a second device is described herein, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or means. Please refer to Fig. 2, which is a schematic diagram of an embodiment of the frequency comparator 1 of the present invention. The frequency comparator 1 is used to compare the frequencies of a first signal & (ie an external clock signal) and a second signal S2 (ie an internal clock signal), and the frequency comparator 100 includes a frequency detect The measuring circuit 10 includes a frequency generator 102, a charge pump circuit 103, a determining logic 104 and a bias generator 105. The frequency detecting circuit 101 generates a reference according to the first signal S! and an input voltage VrQse. The signal generator 102 generates a second signal according to the input voltage Vr〇sc, and the charge pump circuit 103 is coupled to the frequency detecting circuit ιοί and the frequency generator 1〇2 for using the reference signal Sr. Or the second signal S2 enables - the charging current Ic to raise a voltage level Voset; and is used to enable - discharge current according to another signal in the reference signal Sr and the second signal & Ide to lower the voltage level v < jset. The determining logic 104 is coupled to the charge pump circuit 1〇3 for dividing the frequency relationship between the first signal Si and the second signal S2 according to the voltage level Voset outputted by the charge pump circuit 103; The bias generator 105 is coupled to the frequency detecting circuit 101 and the frequency generator 102 for generating an input voltage Vrosc. 1331448, Please note that in this embodiment, the charging operation is controlled by the reference signal s, and the discharging operation is controlled by the second signal heart. However, this is not a limitation of the present invention. For example, in another design of the present invention, the discharge operation can be controlled by the reference signal Sr, and the charging operation is controlled by the second signal s, and the frequency between the first signal 3 丨 and the second signal S 2 The relationship can be divided according to the voltage level Voset. • The following describes the operation between the internal components of the frequency comparator 100. According to the embodiment of the present invention, the frequency detecting circuit 101 includes a first silver window wave generating II 1G11 and a second wave, wherein the first wave generator 1011 is coupled to the first signal. Sl converts the first signal S1 to a first sawtooth wave signal swl, and the first comparator 1012 is coupled to the first sawtooth wave signal heart and the input voltage Vrcs. The silk compares the first job signal Swi and the input voltage V coffee to generate the reference signal Sr. The first sawtooth generator 1011 includes a single pulse wave generating electric Φ path 1011a, a first capacitor C1, a first current source I!, a -th switch Wi, a second switch W2, and a switch control circuit 1 Llb, and as shown in Fig. 2, the single, wave generating circuit lGlla is subtracted from the first signal\, and is used to generate a single pulse signal (m Spi) in each cycle of the first signal ^; The capacitor c' is lightly connected to the first surface wave generator __transmission (four) point % and a first reference voltage vss (ie - grounding butterfly; the first current source is connected to - the second reference voltage vdd (ie - power supply第一); the first switch Wi is lightly connected between the first current source core and the output end point 第一ι of the first stolen tooth wave generator 1011 for selectively tapping the first switch control signal Scl a current source L is connected to the first capacitor C1; the second flip-flop 1448 and the second switch W2 are coupled between the first reference voltage vss and the output terminal N! of the first sawtooth generator 1011, and are used according to a second Switching control signal sc2 to selectively connect the first capacitor 至 to the first reference voltage vss; and the switch control circuit 1011b is coupled to The first pulse control circuit 1011a, the first switch w!, and the second switch W2' are configured to generate the first switch control signal Scl and the second switch control signal according to one of the output signals Spl of the first single pulse wave generating circuit 101a. Sc2. φ Please refer to FIG. 2 again. The frequency generator 102 includes a second sawtooth generator 1021 and a second comparator 1 〇 22. The second sawtooth generator 1 〇 21 is coupled to the second signal I. The second sawer signal 102 is coupled to the second sawtooth wave signal and the input voltage vrosc' for comparing the second sawtooth wave signal Sw2 and the input voltage Vr〇sc. The second sawtooth generator ι〇2ι includes a second capacitor Q, a second current source I2, a third switch Ws, a fourth switch W4, and a switch control circuit. 21a, wherein the second capacitor C2 is lightly connected between the output terminal end n2 of the second staggered wave generator 1021 and the first reference voltage Vss; the second current source 12 is lightly connected to the second reference voltage Vdd; The third switch w3 is reduced from the second current source 12 and the second mineral tooth wave Between the output terminal n2 of the benefit 1021, for selectively connecting the second current source 12 to the second capacitor C2 according to a third switch control signal sc3; the fourth switch is connected to the second mine tooth wave generation The output terminal & and the first reference voltage vss are used to selectively connect the second capacitor C2 to the first reference voltage and the switch control circuit 1021a according to a fourth switch control signal h The second signal s2, the third switch w3, and the fourth switch W4 are connected to generate the third switch control signal according to the fourth signal 32 outputted by the output terminal N2 generated by the second mine 12-1 wave. Sc3 and the fourth switch control signal Sc4. In addition, the 'decision logic 104 is lightly connected to the voltage level 卩 and the third reference VVr3 to output the indication signal Vid, the side of which indicates the relationship between the first signal and the second signal Sk_ frequency. In the present embodiment, the bias generator 1 〇 5 includes a -resistor Rref and a reference volt generating circuit, wherein the reference voltage generates a ruin circuit to the resistor Rref to set the input voltage Vrosc according to the resistance value of the resistor ‘. Please note that the reference voltage generating circuit 1〇5, the frequency detecting circuit 1(1), the frequency generator 102, the charge pump circuit 103, and the determining logic 1〇4 are all integrated in a single chip, and the resistor RreH is disposed on the single chip. Externally, in other words, the resistance value of the external resistor Rref can be easily adjusted. In actual operation, when the resistor Ια is externally coupled to the reference voltage generating circuit 1〇51, the input voltage Vr〇sc is It is set, in which the input voltage vrosc determines the frequency & of the second signal S2 generated by the frequency generator 1〇2. The setting of the input voltage Vr〇sc will be described in detail below. Please refer to FIG. 3, which is a schematic diagram of an embodiment of the bias generator 105 shown in FIG. 1. A fourth reference voltage Vr4 is coupled to the resistor Rref via a error amplifier 1〇52 connected in a closed loop manner and a pass transistor to generate a reference current Iref, wherein Ire produces Vr4/Rref. The reference current Iref is then mirrored by a current mirror circuit 1053 to produce a current mirror current Imirror'. The current mirror of the current mirror circuit 1〇53 is known to those skilled in the art.
比值（current mirror ratio ) Nmirror 可由 P 型電晶體(PMOS 13 1331448 ' 加—_2,或其他可行的裝置來直接碰，另-方面，輸入 電壓vrosc可以將電流鏡電济LlmhT〇r流通一電阻Ri來得到，因此， 。請注意，第3圖所示的電路架構僅為方 .便本發明實施例之描述，然而此並非用來作為本發明之限制條件。 依據以上所述的單一脈波產生電路1〇lla，當第一訊號&被 輸入時，單一脈波產生電路1〇Ua會於第一訊號&之每一週期產 _ 生單一脈波訊號spl給接下來的電路元件，如此就可以避免第一訊 號8!之工作週期(dutycycle)不穩定的問題。請參考第4圖，第4 圖係第2圖所示之單一脈波產生電路1〇lla之一實施例的示意 圖。單一脈波產生電路1011a包含有複數個反相器Invi、Inv2、複數 個電晶體Me Ms、My Μ?、一第三電容Q、一電阻心以及一反 及閘(NAND gate)NG。首先，第一訊號Sl會被反相器Ιην1、複數個 電晶體Μ*、Ms、Μό、、第三電容C3以及電阻R2所組成之一 鲁延遲單元(delay unit)所延遲以產生一延遲訊號Sdelay(如第4圖所 示）接耆’延遲訊號Sdeiay會被輸入至反及閘NG，然後，反及閘 NG便比較延遲訊號以及第一訊號I以輸出單一脈波訊號 Spi(如苐5圖所示）’第5圖係為第4圖和第2圖所示之延遲訊號 Sdelay、第一訊號S丨、單一脈波訊號Sy以及第一鋸齒波訊號§wl的 時序圖。由於延遲單元之操作可輕易地為熟習此項技藝者所瞭 解，因此於此不另贅述。另一方面，請注意，第4圖所示的電路 架構僅為方便本發明實施例之描述，然而此並用來作為本發明之 限制條件，亦即任何可以產生本發明所需的單一脈波訊號Spl之單The current mirror ratio Nmirror can be directly touched by a P-type transistor (PMOS 13 1331448 'plus -_2, or other feasible devices. On the other hand, the input voltage vrosc can flow the current mirror LLMhT〇r to a resistor Ri Therefore, it should be noted that the circuit architecture shown in FIG. 3 is only a description of the embodiments of the present invention, but this is not intended to be a limitation of the present invention. According to the single pulse generation described above. The circuit 1〇lla, when the first signal & is input, the single pulse wave generating circuit 1〇Ua generates a single pulse signal spl to the next circuit component in each cycle of the first signal & It is possible to avoid the problem that the duty cycle of the first signal 8! is unstable. Please refer to Fig. 4, which is a schematic diagram of an embodiment of a single pulse wave generating circuit 1?lla shown in Fig. 2. The single pulse wave generating circuit 1011a includes a plurality of inverters Invi, Inv2, a plurality of transistors Me Ms, My Μ?, a third capacitor Q, a resistor core, and a NAND gate NG. First, The first signal Sl will be inverted by the inverter Ιην1 And a plurality of transistors Μ*, Ms, Μό, a third capacitor C3, and a resistor R2 are delayed by a delay unit to generate a delay signal Sdelay (as shown in FIG. 4). The delay signal Sdeiay will be input to the inverse gate NG. Then, the gate NG will compare the delay signal with the first signal I to output a single pulse signal Spi (as shown in Fig. 5). The timing diagrams of the delay signal Sdelay, the first signal S丨, the single pulse signal Sy, and the first sawtooth wave signal §wl shown in Fig. 2, because the operation of the delay unit can be easily used by those skilled in the art. In other words, please note that the circuit architecture shown in FIG. 4 is only for convenience of description of the embodiments of the present invention, but is also used as a limitation of the present invention, that is, any Single pulse signal Spl required by the present invention