TW200803170A - Input circuits and methods thereof - Google Patents

Abstract

An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a logic level of the input signal. The output unit is coupled to the input terminal. In the first period, the output unit outputs the input signal with the determined logic level at an output terminal of the input circuit to serve as an output signal. In a second period following the first period, the output unit latches the determined logic level of the input signal according to a second enable signal and outputs the input signal with the determined logic level at the output terminal to serve as the output signal.

Description

200803170 IX. Description of the Invention: [Technical Field] The present invention relates to an input circuit, and more particularly to an input circuit for determining two or two inputs on an input pin: Prior Art In general, according to the input signal, the logic input pad of the integrated circuit has two logic states, a high logic state and a low drum state. In some applications, the logical wheel pin may have a floating state indicating that the logic input pin does not receive any two. Thus, conventional input circuits can be used to determine two states on the input pin, such as a floating state and a high logic state, or a floating state: a low logic state. The conventional input circuit can be used to judge the wheel:? Three states, such as a floating state, a high logic state, and a low state. When the input pin is in the floating state, the input circuit of the input circuit is a resistor that pulls the position of the input pin high or low. For example, when the volume=pin has a floating state and a high logic state, and the input (four) is connected, the conventional input circuit is connected to the input pin and the resistance between the input: The level is pulled low, and the wheel determines that the level of the input pin is a low logic level. When the input pin: high logic state, the aforementioned input circuit determines that the input pin Z is a high logic level. However, the resistance between the wheel and the ground: Leakage current is generated in the path formed. Therefore, it is desirable to provide a kind of ς 0758-A32293TWF; MTKI-06-l 12; Yvonne 6 200803170 2nd Π: the floating state of the input pin, and when the input pin is in the low or five logic state, it can be reduced The generation of leakage current. SUMMARY OF THE INVENTION The present invention provides a wheeled person circuit, including a level determining unit and a second two: a fixed unit receives input from an input end of an input circuit: a first period controlled by a second consistent energy signal, determines an input signal card. It is coupled to the wheel end early. During the first period, the turn-out unit is input to the output of the input circuit by the input of the n-out & output with the determined voltage bit f (4) as the output signal. During the connection, the output unit inputs (4) the voltage level of the shirt according to the second enable signal, and outputs an input signal having the determined voltage level as an output signal by the output terminal. The present invention further provides an input circuit including a level decision, an analog digital conversion unit, and a latch mode, group. The level decision unit receives the input signal from the input terminal of the input circuit, and the voltage level of the mosquito input signal is based on the first-period signal during the first period. The analog digital conversion unit receives the wheeled p-number ' having a determined voltage level and converts the input signal to a digital signal based on the determined voltage of the input signal during the first period. The shackle mode is controlled by the second enable signal during the second period following the first period, with the pickup signal as the output signal. In order to make the above objects, features and advantages of the present invention more obvious, the following is a preferred embodiment, and with reference to the drawings, detail 0758-A32293TWF; MTKI-06-l 12; YV0nne 7 200803170 is explained below. [Embodiment] Fig. 1 shows an input circuit and an output unit n according to an embodiment of the present invention. The input can be the integral circuit of the integrated circuit. Level determination unit 1. The input signal IN is received by the input circuit PIN, and the power plant called the signal-carrying signal is called the first one in the first period: as the output signal two ^ E^, 2 brother: ί:, In the middle of the second period, the rounding unit 11 has a voltage level of 6 determined according to the enable signal, and the tiger OUT. According to the output signal 0U, the state of the incoming PIN. In the embodiment of the present invention, the electric house of the 1JT station is said to be based on a reference position, the knife is 35 electric level and the low electric level is repeated, and in the digital logic, the corresponding logic is High level and logic low level. In the present invention, the two states of the input terminal 可 are still in a state of contact, or a floating state and a low logic state. In the lower input side ~ the floating state and the low logic state are 1 eve. As shown in Fig. 1, the input circuit 1 further includes a level maintaining unit 〇 758-A32293TWF; MTKI-06-112; Yvonne 200803170 quasi-maintaining unit 12 is enabled by the letter 2 17 " ί human terminal PlN electric dust value. When the level is maintained, the voltage of the input terminal PIN is subjected to :::: board. The input circuit i also includes a timing generation unit (tlming 2 〇 n Umt) 13 for generating The enable signals EN_1 and EN 2. The enable signal EN_i and the enable signal EN-2 have opposite (four) levels, for example, both are high voltage levels and the other is low voltage level.

Referring to Fig. 1, the output unit 11 includes inverters Ua, 11b, and Uc, and a switch lid. The inverters Ila and 11b are lightly connected in series. As shown in FIG. 1, the inverter 11a is coupled between the node N11 and the input terminal Pm, and the inverter 11b is coupled between the output terminal ρ〇υτ and the node Nil. The switch 11d is controlled by the enable signal item 2, and is coupled between the input terminal ΡΙΝ and the node Nil. Referring to Fig. 1, the level determining unit 1 includes a switch (10) and a resistance switch K)a which are controlled by an enable signal EN". The switch core 1 is coupled to the reference voltage Vref. In this embodiment, since the two states of the wheel terminal Pm are the floating state and the low logic state, the reference voltage vR = is the power supply voltage (power v〇ltage). Conversely, if the two states of the input PIN are the floating state and the high logic state, the reference voltage VR = is the ground voltage. The first end of the resistor 10a is coupled to the second end of the switch i (10), and the second end of the resistor 10a is coupled to the input end Pin.

The level maintaining unit 12 includes switches 12a and 12b, and a resistor crying, 12c. The switches 12 and 12b and the resistor 12c are lightly connected in series between the reference voltage VREF and the input terminal PIN. The switch i2a is controlled by the sound of the sound 075δ-A32293TWF; MTKI-06-112; Yvonne 9 200803170, OUT-controlled and the switch 12b is controlled by the enable signal. In the H% example, the I test power VREF is grounded, and the switch 12b is controlled by the reverse signal of the month b仏唬EN-2. Figure 2 is a comparison between the voltage V- and the enable signal eNj. ^: The operation of the input circuit 1 will be '" according to Figures 1 and 2. In this example, all switches are turned on by a high voltage level signal and turned off by a logic low level signal.

Referring to Fig. 2, during the first period P-1, the reference voltage VREF starts to rise from 0V and has a high voltage level, and the enable signal EN-1 rises with the reference voltage VREF (supply voltage). When the enable signal 1 reaches the high voltage level to turn on the switch, in the level determining unit "1", a first path is formed between the f test voltage VREF and the input terminal PiN. If the input terminal Pm is in the floating state, the voltage level criterion of the input signal 35IN is transmitted through the first path and is pulled up according to the reference voltage Vref. The level determining unit (7) determines the input signal and the voltage level is a high voltage level. In other words, the level determining unit 10 determines that the voltage level of the input signal IN is the voltage level of the parameter = voltage. In the first period p", the switch Ud is closed by the enable signal EN-2 opposite to the enable signal EN-1, and the input signal IN having a high voltage level is turned to the output through the inverters 11a and 11b. end

Pout, as the rounding signal 〇υτ. Since the switch 12b is also turned off by the enable signal EN_2, the level maintaining unit 12 is in an inactive state. When the reference voltage vREF rises to a predetermined voltage (for example, 2·7 ν), the enable signal ΕΝ-1 is switched to low. Voltage level to turn off the switch 1〇&, and 0758-A32293TWF; MTKI.〇6-112; Yvonne 10 200803170 The enable signal EN_2 is switched to a high voltage level to turn on the switch ud. Refer to Fig. 2, where the enable signal EN_1 is switched to the low voltage level, the flag "TP" is indicated, and the period after the time TP is called "#=== P_2. During the second period p-2 'the high voltage level of the input signal IN is latched by the inverters 11a and lie, and the input signal IN having the high voltage level is output to the inverters ua and nb to Rim" a from the natives, copper out ^ Ρ〇υτ, to

As the output signal OUT. Therefore, according to the output signal OUT ’ of the high voltage level, it can be judged that the input terminal pIN is in a floating state. Further, in the second period P-2, the first path is turned off by the switch i〇a. Since the switches 12a and 12b are respectively turned on by the output signal 〇υτ and the enable signal ΕΝ_2, the level maintaining unit 12+ forms a second path between the reference voltage VREF and the input terminal ΡΙΝ. This second path slightly raises the voltage value of the high voltage level of the input signal IN to prevent the voltage value of the high voltage level of the input signal IN from being disturbed by noise. In the first period P-1, if the wheel terminal ΡΙΝ is in a low logic state, the input signal IN is a low voltage level. The level determining unit 1〇 determines that the input signal IN is at a low voltage level. Since the switch ud is turned off by the enable signal Ε γ, the input signal having the low voltage level is transmitted through the k reverse 11a and the lib output to the output ρ 〇υ τ as an output signal. OUT. The switch 12b whose second path is closed is cut off, so the level maintaining unit 12 is in an idle state. Due to the switch l〇a that is turned on during the first period, leakage current is generated in the first path. Then, in the second period P-2, the en-B knife is switched to the low-voltage repeat level to close the switch 1 〇a. The first road you R] Shi + TT 匕 σ road location this cut, and no more leakage current flows 〇 758-A32293TWF; MTKI. 〇 6-l 12; Yvonne 200803170 The first way. The enable signal ΕΝ2 is switched to a high voltage level to turn on the switch iid, the low voltage level at the top of the input signal is locked by the inverter na& Uc, and the wheeled signal with a low voltage level is transmitted through The inverters Ua and 11b are outputted to the output terminal ρ 〇υ τ as the rounding signal 〇υτ. Therefore, according to the low level output signal 〇UT, it can be determined that the input terminal Ριν is in a low logic state.

In addition, in the second period Ρ2, since the switch 12a is turned off by the low voltage level=output signal out, the level maintaining unit 12 is also in the idle state, and the input 彳5 No. 1N is a low voltage level. Since both the first and second paths are cut during the second/monthly P-2, there is no leakage and flow is generated. In some embodiments, when the two states of the input terminal Pw are the two-connected state and the high-logic state, the reference power 1 V is a ground voltage having a low electric house level. If the input terminal PIN is in the floating state, the input passes through the first path of the level determining unit 1 and is pulled down according to the tea test voltage VREF. The level mosquito unit 1 () therefore determines that the input _ = is low. If the input terminal & is in a high logic state: the bit is determined to be early, then the mosquito input signal IN is the high battery level. The transition state of the loading signal 1 and EN-2 indicates the embodiment of the timing generating unit 13 in Fig. 1 according to the drawing system. The signal generator 13 includes a voltage generator 3, a comparison unit 32, a timer 33, a multiplexer 34, or a gate %. The divider 36° voltage divider 31 includes resistors 3 and 3 lb. Comparison = including comparator 32a & D type flip-flop 3 沘, braking is earlier than 32 B is driven by the falling edge 'and produces initial low power 0758-A32293TWF; MTKI-06-112; Yv〇nne 200803170仏唬CS_1. The timer 33 generates a control signal CS_2 which initially has a low voltage level. The voltage generator 3 〇 receives the supply voltage Vbat and generates Vj based on the supply voltage VBAT. In this embodiment, the electricity is generated, and can be coupled to the power supply by the bandgap voltage generator (bandgap v〇ltage generat〇r) in the compactor 31. The resistors 31a and 31b are coupled in series. The voltage ν ΒΑ τ is between the ground voltage GND. The voltage divider 31 generates a voltage V_2 based on a voltage difference between a predetermined ratio of the supply voltage Vbat and the ground voltage. This predetermined ratio is determined by the resistance values of the resistors... and =. The non-inverting terminal (+) of the comparator 32a receives 黾 [V-1 whose inverting terminal (-) receives the voltage V-2. Assume that the thunderbolt pressure JBAT rises slowly, for example, the rise time is less than - 丨亳 second (n; s) package as shown in Figure 4. The comparator 32a compares the voltages Vj and v_2, and produces the result signal RS, and changes the result of the comparison signal RS to the one end of the electric multiplexer to receive the result signal RS' and the other end receives [VBAT. During the period of the first phase, p-1, at the beginning, the voltage V 2 β ; 黾 1 V-1, the result signal is changed to the low voltage level than the parent state 32a. Then, the voltage V-2 becomes smaller than the voltage V", and the comparators 32a, :I change the fruit D number RS to a high voltage level. Since the resulting signal voltage level becomes a high voltage level, since the D-type flip-flop 32 is in a state of transition only at the falling edge, the control signal CSj is maintained at a low voltage level. The sum 35 receives the control signals CSJ and CS 2 each having a low voltage level, and the input signal S S to the multi-guard 34 of the low voltage level. The multiplexer f outputs the supply voltage VBAT as the enable signal ENJ. In other words, during the first period P-1, the enable signal is up 〇758-A32293TWP with the supply voltage VBAT; MTKI-〇6.112; Yv〇nne n 200803170 and the output is reversed. The opposite state 3 6 receives and reverses the enable signal εν 1 of the enable signal ΕΝ-1 as the enable signal εν_2: after the time τρ, that is, in the second period ρ-2, the voltage ν becomes greater than the voltage v− !! At time τρ at which the supply voltage Vbat is equal to 2 7 ν, the comparator 32a changes the resultant signal RS to a low voltage level. Since the == high (four) level changes to a low electric grind level, a falling edge is produced on the resulting (four). The D-type flip-flop 32 is thus triggered, and the control M CS_1 becomes a high voltage level as the power supply (four) Vbat. The OR gate 35 receives the control signal Cs 2 having the high voltage level control signal cs ancient voltage level, and will output a /, low - and cross-voltage level to the multiplexer 34. The multiplexer 34 then outputs the resulting signal RS of the low voltage level as a enablement. Therefore, the "number" is changed from "= level to low (four) level at time Tp of 2.7 v. The inverter 36 receives and reverses the low-level dust level. ^ Output the reverse enable signal ΕΝ 1 as the enable (4) EN-2. Note that the control number CS-2 initially has a low level: when the timer 33 reaches the time τρ and the control signal (1) 2 is at the voltage level, the timing The controller changes the control signal CS2 to a high voltage level, so that the multiplexer 34 rounds - the port signal ENJ. Outputs, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Since the voltage Vj generated by the voltage generator 3G cannot be quickly turned up = -2 is always greater than the voltage V". The result of the comparator 二 二 二 二 信号 信号 信号 信号 信号 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 。 。 。 。 The low voltage level control signal (1) is circumscribed, and the loyalty selection signal SS is output to the multiplexer 34. Duplex crying w then output power supply anger v ° ° 34 when the supply voltage VJ: AT as an enable (four) EN - Bu, therefore,

When Vbat is designed for 2.7V, the enable signal ΕΝ-1 is not prepared by the ancient low voltage level. In this case, when the timer ^day 4 (four) device 33 reaches the time TP, the timer 33 is connected.

The control signal C: S 2 is changed to the ancient + cranial & 诂 诂 夕 且 and then the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _旒SS, as the enable signal ΕΝ_1. / In some embodiments, the timing generation unit 13 can be simplified. Fig. 6 is a view showing another embodiment in which the order of the trampoline 13 in the trampoline in Fig. 1 is generated. Timing early το 13" includes a timer 6 〇 and an inverter 61. The timer is a sonic enable signal Ε ν". When the timer (9) reaches the time τρ between the first period ρ 1 and the first period P-2, the timer 6 改变 changes the enabling signal — 1 to a low voltage level. The inverter 31 receives and reverses the enable signal ΕΓρΕΓ-1, and turns the reverse enable signal to 1 as the enablement ^ on the hN 2 gentleman in the second example, when the input circuit 1 is applied In the integrated circuit, the enable signals EN-1 and EN-2 are generated internally by the integrated circuit. - Figure 7 shows an input circuit of an embodiment of the present invention which can determine the three states of the input terminal, i.e., the floating state, the high logic f, and the low logic state. As shown in Fig. 7X, the input circuit 7 includes a level determining circuit 70: an analog digital converting unit 7 and a shackle module 72. The input can be the logic input pin of the integrated circuit. The level determining unit 7 receives the input signal IN from the input terminal PIN of the circuit 7 by the input 758-A32293TWF; MTKI.〇6-112; Yvonne 200803170, and determines the input when the enable signal EN_1 is high during the first period. The voltage level of the signal IN. The analog-to-digital conversion unit 71 receives the input signal IN having the determined voltage level, and converts the input signal IN into the digital signal RS in accordance with the voltage level determined by the input signal IN during the first period. During the second period following the first period, the shackle module 72 latches the digital signal RS as the output signal OUT according to the enable signal EN_2. According to the output signal OUT, the state of the input terminal PIN can be judged. In the embodiment of the present invention, the voltage level can be divided into a high voltage level and a low voltage level according to a reference level, and correspondingly to the logic high level and the logic low level in the digital logic. As shown in FIG. 7, the input circuit further includes a pull-down unit 73. The pull-down unit 73 is coupled between the input terminal IN and the ground voltage GND. During the second period, when the input terminal PIN is in the floating state, the pull-down unit 73 pulls the input terminal Pm to the ground voltage GND. The input circuit 7 further includes a timing generating unit 74 for generating enable signals EN_1 to EN_2. The enable signal EN_1 has an opposite voltage level to the enable signal EN_2. Referring to Fig. 7, the level determining unit 70 includes switches 70a and 70d and resistors 70b and 70c. Switches 70a and 70 are controlled by control signal EN_1. The resistor 70b and the switch 70a are coupled in series between the supply voltage Vbat and the input terminal Pin. The resistor 70c and the switch 70d are coupled in series between the input terminal Pm and the ground voltage GND. In this embodiment, the resistance values of the resistors 70b and 70c are equal. Referring to Figure 7, analog-to-digital converter 71 includes comparators 71a and 0758-A32293TWF; MTKI-06-112; Yvomie 16 200803170

71b' and the voltage divider 71c. The voltage divider 71c is coupled between the supply voltage vBAT and the ground voltage GND, and is controlled by the enable signal ENj to generate the threshold voltage VTHj & vth-2 during the first period. The voltage divider 71c includes a switch 71d, and resistors 71e to 71g. The resistors 7u to 71g are connected in series % between the supply voltage VB Ατ and the ground voltage gnd. The switch 71d is controlled by the enable signal ENj. The threshold voltage VTH-1 is generated in the node N7ia between the resistors 71e and 71f, and the threshold voltage VTHJ is generated in the node N71b between the resistors 71f and 71g. The comparison state 71a receives the signal IN from the non-inverting terminal (+), and receives the threshold voltage VTHj from the terminal (-). The comparator 71a compares the voltage level determined by the input k唬IN with the threshold voltage VTHj, and generates a result signal RS according to the comparison result. The comparator 71b receives the signal IN from the non-inverting terminal (+), and is terminated by the opposite end ( The threshold voltage VTH_2 is received. Compared with the comparison 71b, the input signal 比较 has determined the voltage level and the threshold voltage VTH-2, and the result signal rs-2 is generated according to the comparison result. Result signal • RS-1 is combined with the resulting signal RS-2 to become the digital signal HS. In this embodiment, each of the resultant signals RS-1 and RS-2 occupies 1 bit, and thus the digital signal RS has 2 bits. The shackle module 72 includes shackles 72 & and 72b. The shackle crying 72& receives the result signal RSJ from the (4) 7U, and selects the lock result signal RSj' as the pickup signal OUT-1 in the middle according to the enable signal EN-2. The latch 72b receives the resultant signal RS-2 from the comparator 71b and latches the junction signal RS_2' as the shackle signal 〇υτ_2 according to the enable signal ΕΝ-2 during the second period. Pick-up signal 〇υτ工 0758-A32293TWF; MTKI-06-112; Yvonne 17 200803170 • Combined with OUT_2 to become the output signal OUT. In this embodiment, each of the shackles signals OUT__1 and OUT_2 occupies 1 bit, so the output signal occupies 2 bits. The pull-down unit 73 includes a resistor 73a, switches 73b and 73c, and a reverse OR gate (XOR) 73d. The resistor 73a and the switches 73b and 73c are coupled in series between the input terminal PIN and the ground voltage GND. The inverse OR gate 73d receives the shackle signals OUTJ and OUT_2 and generates an enable signal EN_3. The switch 73b is controlled by the enable signal EN_2, and the switch 73c is controlled by the enable signal EN_3. The operation of the input circuit 7 will be described in conjunction with Figures 7 and 2. In this embodiment, all of the switches are turned on in accordance with the high voltage level signal and are turned off in accordance with the low voltage level signal. Referring to Figure 2, during the first period P_1, the supply voltage

Vbat starts from 0V and has a high voltage level, and the enable signal rises with the supply voltage VBAT. When the enable signal ΕΝ-1 reaches the high voltage level, the switches 70a and 70d are turned on. If the input terminal Pin is in the floating state, since the resistors 70b and 70c have the same resistance value, the voltage level of the input signal IN is pulled to an intermediate voltage between the supply voltage VBAT and the ground voltage GND. The level determining unit 70 thus determines the voltage level of the input signal IN to be an intermediate voltage level. At the same time, the switch 71d is turned on, so that the threshold voltage VTH_1 can be obtained to be larger than the threshold voltage VTH_2. Since the threshold voltage VTH_1 is greater than the voltage level of the input signal IN, the comparator 71a produces a low voltage level result signal RS_J. Since the voltage level of the input signal IN is greater than the threshold voltage VTH_2, the comparator 71b generates a high voltage bit 0758-A32293TWF; MTKI-06-112; Yvonne 18 200803170 • The resulting signal RS_2. When the supply voltage VBAT rises to a predetermined voltage (for example, 2.7V), the enable signal EN_1 is switched to the low voltage level, and the enable signal EN_2 is switched to the high voltage level. Referring to Fig. 2, the time when the enable signal EN_1 is switched to the low voltage level is marked with the symbol "TP", and the period after the time TP is referred to as the second period P_2. During the second period PJ, the latches 72a and 72b are triggered by the high voltage level enable signal ΕΝ_2. The latch 72a receives and latches the low voltage level result signal RS_1 as the shackle signal OUTJ. The latch 72b receives and latches the high voltage level result signal RS_2 as the shackle signal OUT_2. Therefore, according to the shackle signal OUT_1 of the low voltage level and the shackle signal OUT_2 of the high voltage level, it can be judged that the input terminal Pin is in a floating state. Further, in the second period P_2, the inverse gate 73d receives the latch signal OUTj of the low voltage level and the latch signal OUT_2 of the high voltage level, and generates the enable signal EN_3 of the high voltage level. The switch 73b is turned on by the high voltage level enable signal EN_2, and the high voltage level of the switch 73c causes the enable signal EN_3 to be turned on. Therefore, the input terminal PIN is pulled down to the ground voltage GND to prevent the input terminal PIN from floating. If the input PIN is in a low logic state, during the first period P_1, the input signal IN is at a low voltage level. The level determining unit 70 thus determines that the input signal IN is at a low voltage level. According to the operation of the analog digital conversion unit 71 and the shackle module 72, in the second period P_2, the shackle 72a locks the low voltage level result signal RS_1 as the shackle signal OUT_1, and the shackle 72b locks The result signal of the low voltage level is RS 2 0758-A32293TWF; MTKI-06-112; Yvomie 19 200803170 ^ as the shackle signal 〇UT_2. Therefore, according to the low voltage level shackles 〇UT_1 and OUT_2, it can be judged that the input terminal ΡΙΝ is in a low logic state. In the same operation, if the input terminal ΡΙΝ is in the high logic state, the latch 72a locks the high voltage level result signal RS_1 as the shackle signal 〇UT_1, and the shackle 72b locks the high voltage level result signal. RS_2 is used as the shackle signal OUT_2. Therefore, according to the high voltage level shackles 〇UT_l and OUT_2, it can be judged that the input ΡΪΝ is in the high ® logic state. In the case where the input terminal ΡΙΝ is in the low logic state and the high logic state, since the reverse gate 73d receives the latch signals OUT_l and OUT_2 having high/low voltage levels, the reverse gate 73d generates a low voltage level. The signal EN_3 can be turned off to turn off the switch 73c. Therefore, the pull-down unit 73 is in an idle state. In this embodiment, the timing generating unit 74 can be implemented by the timing generating unit 13' of FIG. 3 or the timing generating unit 13" of FIG. 6. In some embodiments, when the input circuit 7 is applied to the integrated circuit The enable signals EN_1 and EN_2 are generated by the internals of the integrated circuit. The present invention has been disclosed in the preferred embodiments as above, but it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art is not Without departing from the spirit and scope of the invention, the invention may be modified and modified, and the scope of the present invention is defined by the scope of the appended claims. 0758-A32293TWF; MTKI-06-112; Yvonne 20 200803170 [Simple description of the diagram] The human terminal ^ ^ ^ (4) The input circuit of the embodiment, which can determine the relationship between the second picture and the relationship between the two and the color of the second picture; the middle test voltage VREF, enable Signal _" f3 diagram shows the embodiment of the timing generation unit in Fig. 1; f4 diagram shows the relationship between the power supply voltage VBAT and the enable signal en_1 when the power supply voltage (4) rises slowly; Fig. 5 shows the supply voltage When Vbat rises quickly Voltage νΒΑΤ the enable signal EN 1-relationship among which; FIG. 6 shows a first! Further implementation of the timing generation unit in the figure and Fig. 7 shows an input circuit of an embodiment of the present invention which can determine three states of the input terminal. Do not [main component symbol description] 1~ input circuit; 10-, level determining unit; 10a~ switch; 10b, ~ resistor; 1/output unit; 11a, 1 lb, 1 ic~ reverse lid~ switch; 12~ level maintaining unit; 12a, 12b~switch; 12c-~ resistor; 13, / timing generator; Nil·~ node; Pin" ^ input; Ρ〇υτ wheel-out; 13,, timing generation 30~ voltage generator; 3b/divider; 31a' 3lb~ resistor; 0758-A32293TWF; MTKI-06.112; Yvoime 21 200803170 32~ comparison unit; 32a 32b~D type flip-flop; 33- 34 ~ multiplexer; 35, 36 ~ reverser; 13" 6 0 ~ timer; 61, 7 ~ input circuit; 70, 70a, 70d ~ switch; 70b 71 ~ analog digital conversion unit; 71a 71c ~ voltage divider 71d 71e, 71f, 71g~ resistor; 72, 72a, 72b~ 拴 latch; 73- 73a~ resistor; 73b 73d~ reverse or gate; 74- N71a, N71b~ node; Pin, Ρ〇υτ output ... comparator; 1 ten timer; or gate; - timing generation unit; inverter; 'bit Determining circuit;, 70c~ resistor;, 71 b~ delivery device than the car; through switching; - latch module; 'down unit;, 73c~ switch; / timing generation unit; ^ input terminal;

0758-A32293TWF; MTKI-06-112; Yvonne 22

Claims (1)

200803170 X. The scope of application for patents·· 1 · The type of wheeled circuit, including: (4) The input of the input channel is determined by the input terminal, and the voltage of the input signal is determined during the middle period. a first enable signal control, and: a turn-off unit coupled to the wheel-in terminal, - - 钤屮, 嫂 j 忒 a first period 'the output unit is input by the input circuit 敫: outputting the input signal having the determined voltage level as the -round signal: and the unit, in the second period following the first period, the output second enable signal to lock the input The signal has been determined > and the output signal has the determined voltage level as the output signal. ▲ 2. For the input circuit described in item 1 of the patent scope, wherein the unit receives a reference voltage 'and when the input terminal is at - sweat, the voltage level of the input signal is determined as the voltage of the reference voltage. Level. The input circuit described in claim 2, wherein when the input terminal is in the -low logic state, the level determines that the single (four) input signal is a low voltage level. Λ 4·If the input circuit described in item 2 of the patent scope further includes a level, holding a single 兀, when the wheel end is in the floating state, the first one is used according to the 忒 and the wheel A signal is sent to maintain the voltage value of the determined voltage level of the turn-in signal. 0758-A32293TWF; MTKI.06-112; Yv〇nne 23 200803170 5. As claimed in the patent scope! The level determining unit includes: a “input circuit, wherein the - the first switch is controlled by the first end of the first enable signal—the reference voltage; and the “different-switch” resistor. The first resistor - the second end of the switch, $ ^ is coupled to the first input. Knowing that it is light The output Si is in the wheeled circuit of the first item, wherein a first inverter; a second inverter between the wheel end and the output, the --reverse Connected to a first node in series; a third inverter; a second switch controlled by the second enable signal, and lightly connected to the third in the same manner as the third print Between the node and the output. The input circuit of claim 1, wherein the human bird causes the nickname to have a voltage level opposite to the second enable signal 〇8 as described in claim 1 of the patent scope. The input circuit ′ further includes a second switch, a fourth switch, and a second resistor coupled in series between a reference voltage and the input terminal, and the reference voltage is also coupled to the level determining unit. 9. The input circuit of claim 8, wherein the third switch is controlled by the turn-off signal, and the fourth switch is controlled by the 〇758-A32293TWF; MTKI.〇6-112; Yvonne 24 200803170 ^ Second enable signal. 10. The input circuit of claim 1, further comprising a timing generating unit for generating the first and second enabling signals, wherein the first enabling signal and the second enabling signal Have the opposite power level. The input circuit of claim 10, wherein the timing generating unit comprises a first timer for generating the first enable signal, wherein, when the first The timer reaches a time between the first and second periods, the first timer changes the voltage level of the first enable signal, and the first four inverters receive the first The energy signal is consistent and the second enable signal is output. 12. The input circuit of claim 1, wherein the timing generating unit comprises: a voltage generator, receiving a supply voltage for generating a first voltage according to the supply voltage; Connected between the supply voltage and a ground voltage to generate a second electrical component according to a predetermined ratio of the voltage difference between the supply voltage and the ground voltage; a comparison unit for comparing the first And generating a result signal and a first control signal with the second voltage, and changing the voltage level of the result voltage and the first control voltage according to the comparison result; the first meter is used to generate a second Control signal, wherein, 0758-A32293TWF; MTKI-06-l 12; Yv〇mie 25 200803170 arrives between the first and the second period, the first unit has not changed the first - control signal electric house' Changing a voltage level of the second enable signal by a timer; and receiving, by the multiplexer, the voltage level of the power supply voltage and the result signal = and the second control signal to output = £ or a, Knob k For the first enable signal. 13. A wheeled circuit, including · > level determining unit, (4) the input circuit of the input circuit receives a: =, used to determine the voltage level of the _in signal according to the -first-enable signal during a first period, wherein The first period is controlled by the coincidence signal; the analog-to-digital conversion unit receives the far input nickname having the determined voltage level for determining the determined voltage level of the input signal during the period The input signal is converted into a digital bit-lock module for latching the digital signal according to the second enable signal during a second period following the first period to obtain two output signals. The input circuit of claim 13, wherein the state of the input terminal is determined based on the output signal. 15. The input circuit of claim 13, wherein the level determining unit 70 is coupled between a supply voltage and a ground voltage, and when the input terminal is in a floating state, determining the Input signal power 0758-A32293TWF; MTKI-06-112; Yvonn (26 200803170 will be in the position of f / electric power denomination (4) - level - including the input circuit described in item 15 Further, the package is connected to the wheel end and the port is connected to the terminal, and the input end is in the floating state; - also between the 'when the signal is pulled down by the input terminal according to the output material. The encirclement 13 rhyme is described by the circuit, and the level determining unit includes ·· , , A a switch 'controlled by the first _ enable signal; the first resistor' is coupled in series with the first switch to an I, a 黾 pressure and the wheel end, and a second switch Controlled by the first enable signal; and - the second resistor 'and the second switch are connected in series between the input terminal and a ground voltage. 18. The input circuit of claim 13, wherein the analog-to-digital conversion unit comprises: a first voltage divider coupled between a supply voltage and a ground voltage for a first period, generating a first threshold voltage and a second threshold voltage according to the first enable signal; a first comparator receiving the input signal and the first threshold voltage for comparing the determined input signal a voltage level and the first voltage, and generating a first result signal according to the comparison result; and a second comparator receiving the input signal and the second threshold voltage for comparing the determined input signal a voltage level and the second voltage 'and a second result signal according to the comparison result; 0758-A32293TWF; MTKI-06-112; Yvonne 27 200803170 /, Zhongyi Haidi 1 and 2nd result signals combined into Digital signal. The input circuit of claim 13, wherein the first enable signal and the second enable signal have opposite voltage levels, such as item 13 of the scope of the patent application. The input circuit further includes a fourth switch, a fifth switch, and a sixth resistor coupled between the input terminal and a ground voltage in a string % manner. The input circuit of claim 2, wherein the output signal is logically calculated to obtain a third enable signal, the fourth switch is controlled by the second enable signal, and the The fifth switch is controlled by the third enable signal. An input circuit as described in the scope of claim 2, further comprising: a timing generating unit for generating the first and second enabling signals, wherein the first enabling signal and the second The energy signal has a loose voltage level. The input circuit of claim 22, wherein the timing generating unit comprises: “a first timer for generating the first enable signal, wherein when the first timer arrives At a time between the first and second periods, the first timer changes a voltage level of the first enable signal; and a first inverter is configured to receive the first enable signal, And outputting the second enable signal. 24. The input circuit according to claim 22, wherein 〇758-A32293TWF; MTKH)6-m; Yvo Cong 2〇200803170, the timing generating unit includes a power generator, receiving a lightning supply + drop + * ^ 1 eight-turn voltage for generating a first voltage according to the supply voltage; - a first voltage divider 'coupled to the supply voltage and one a ground voltage between 3, for generating a second voltage according to a predetermined ratio of the voltage difference between the power supply voltage and the grounding voltage; - a comparing unit for comparing the first and second voltages, generating - Result signal and -th-control signal, and based on the comparison result And changing the voltage level of the result voltage and the first control voltage; and 'the first day of the defensive state, for generating a second control signal, wherein, the second timer reaches the medium (four) - and the second period For a predetermined time, the comparison unit has not changed the first control signal voltage level 'the second timing II changes the money level of the second enable signal; and... Γ multiplex f 'receives the supply voltage XI The result (4) is used to output the power supply voltage or the result signal as the first enable signal according to the (four) level of the first and second control signals. 25. A method suitable for an input circuit, The input circuit has an input terminal, the method comprising: determining a voltage level of an input signal on the wheel input end; picking up a determined voltage level of the wheeled signal; and having a determined voltage level The input signal is an output signal; and the horse determines the state of the input terminal according to the rounding signal. 0758-A32293TWF; MTKl.〇6.112; Yv〇nne 29