TWI420821B - Power converter and pulse width modulation signal controlling apparatus thereof - Google Patents

Description

Power conversion device and pulse width modulation signal control device thereof

The present invention relates to a power conversion device, and more particularly to a pulse width modulation signal control device for a power conversion device.

In response to the versatility of today's electronic products, it is a popular way to generate and provide different operating power sources through a so-called power converter. The power conversion device switches the power transistor switch by using a Pulse Width Modulation (PWM) signal to achieve a switching operation between the power sources.

The pulse width modulation signal is typically generated by a pulse width modulation signal control device. In the case where the pulse width modulation signal control device is integrated by an integrated circuit (IC), in order to increase the new function of the pulse width modulation signal control device, it is often necessary to add an additional pin to provide an additional input signal. . Since these additional pins in the integrated circuit will occupy a larger circuit area in the circuit layout of the pulse width modulation signal control device, the circuit cost is increased. In addition, in the case where the total number of pins is increased, the integrated circuitized pulse width modulation signal control device may have to change the type of its package, so that the circuit board carrying the pulse width modulation signal control device also corresponds. modify. In other words, this extra-pin action will create many cumbersome engineering problems.

The invention provides a pulse width modulation signal control device, which enables the mode setting function to be completed through the signal pin position without unnecessary feet.

The invention provides a power conversion device, wherein the mode setting function of the pulse width modulation signal control device can be completed through a signal pin, and no extra pin is needed.

The invention provides a pulse width modulation signal control device, which comprises a signal pin, a core circuit, a setting judgment circuit, a signal adjustment and selection circuit and a timing circuit. The signal pin is connected to the setting component for receiving an external input signal. The setting judging circuit receives the setting signal, compares the setting signal with the reference value, and thereby generates a setting judgment result. The signal adjustment and selection circuit is coupled to the signal pin. When in the first state, the signal pin is coupled to the setting judgment circuit and the external input signal is adjusted according to the setting component, and the signal pin is coupled to the second state. Core circuit. The setting signal is generated according to the setting component. The timing circuit generates a selection signal. The timing circuit is coupled to the signal adjustment and selection circuit for controlling the state of the signal adjustment and selection circuit, wherein the timing circuit causes the signal adjustment and selection circuit to be in the first state for a predetermined period of time.

In an embodiment of the invention, the setting determining circuit includes a comparator for receiving an external input signal and a reference value, and comparing the setting signal with the reference value to generate a setting determination result.

In an embodiment of the invention, the setting determination circuit further includes a latch. The shackle is coupled to the comparator, and the shackle is used to set the judgment result according to the shackle signal.

In an embodiment of the invention, the timing circuit generates a shackle signal when the timing reaches a predetermined time period.

In an embodiment of the invention, the setting determination circuit includes a first analog bit converter and a processor. The first analog-to-digital converter is coupled to the signal pin, and receives and converts the set signal of the analog format into a digital format. The processor receives the setting signal of the digital format, and generates a setting judgment result according to the setting signal and the reference value of the comparison digital format.

In an embodiment of the invention, the setting determination circuit further includes a register. The register is coupled to the analog digital converter to lock the digital format setting signal according to the shackle signal.

In an embodiment of the invention, the pulse width modulation signal control device further includes a second analog digital converter. The second analog-to-digital converter is coupled to the processor, receives the feedback signal of the analog format, and converts the feedback signal of the analog format into a digital format. The feedback signal is at least one of a feedback voltage and a feedback current.

In an embodiment of the invention, the processor receives the feedback signal in a digital format and generates a protection signal according to the feedback signal in the digital format.

In an embodiment of the invention, the pulse width modulation signal control device further includes a pulse width modulation signal generating circuit. The pulse width modulation signal generating circuit is coupled to the setting determining circuit to generate at least one pulse width modulation signal according to the setting determination result and the protection signal.

In an embodiment of the invention, the signal conditioning and selection circuit includes a current source, a first switching element, and a second switching element. The current source is coupled to the signal pin. The first switching element is connected in series between the current source and the reference voltage. The second switching element is connected in series between the core circuit and the signal pin. Wherein, when the first switching element is turned on, the current source provides an adjustment current through the reference resistor, and thereby the external input signal is adjusted as a setting signal.

The invention further provides a power conversion device comprising at least one power conversion circuit and a pulse width modulation signal control device. The pulse width modulation signal control device is coupled to the power conversion circuit for generating at least one pulse width modulation signal to control the power conversion operation of the power conversion circuit, and the pulse width modulation signal control device includes a signal pin, a core circuit, and a setting judgment. Circuits, signal conditioning and selection circuits, and timing circuits. The signal pin is connected to the setting component for receiving an external input signal. The setting judging circuit receives the setting signal, compares the setting signal with the reference value, and thereby generates a setting judgment result. The signal adjustment and selection circuit is coupled to the signal pin. When in the first state, the signal pin is coupled to the setting judgment circuit, and the external input signal is adjusted according to the setting component, and the signal pin is coupled to the core circuit when in the second state. , wherein the setting signal is generated according to the setting component. The timing circuit generates a selection signal. The timing circuit is coupled to the signal adjustment and selection circuit for controlling the state of the signal adjustment and selection circuit, wherein the timing circuit causes the signal adjustment and selection circuit to be in the first state for a predetermined period of time.

In an embodiment of the invention, the power conversion circuit is a DC-to-DC power conversion circuit, a DC-to-AC power conversion circuit, or an AC-to-DC power conversion circuit.

Based on the above, the present invention performs timing by the timing circuit in accordance with the point in time at which the operating power of the pulse width modulation signal control device is supplied. According to the result of the timing, the signal adjustment and selection circuit is used to adjust the external input signal to the set signal to complete the mode setting function. In this way, the mode setting function can be completed by the signal pin, and there is no need to provide an extra pin, which effectively saves the circuit area.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a pulse width modulation signal control apparatus 100 according to an embodiment of the present invention. The pulse width modulation signal control device 100 includes a signal pin 110, a signal adjustment and selection circuit 120, a setting determination circuit 130, a core circuit 140, and a timing circuit 150. For example, the pulse width modulation signal control device 100 is externally connected to a setting component through the signal pin 110 and receives a reference level signal through the setting component, in this embodiment. The external input signal Vdd.

The signal adjustment and selection circuit 120 is coupled to the signal pin 110, and coupled to the signal pin 110 to the core circuit 140 according to the selection signal SEL, or the external input signal Vdd is set to the setting signal MSET and coupled to the signal pin 110 to the setting judgment. Circuit 130.

Specifically, the signal adjustment and selection circuit 120 performs an adjustment and coupling operation of the external input signal Vdd according to the selection signal SEL. For example, when the selection signal SEL is at the first level (eg, logic low level “0”), the signal adjustment and selection circuit 120 is now in the first state to adjust the external input signal Vdd to another voltage level. The setting signal MSET. Moreover, the signal adjustment and selection circuit 120 couples the signal pin 110 to the setting determination circuit 130 to transmit the setting signal MSET to the setting determination circuit 130. Please note here that the setting signal MSET is set according to an electrical characteristic of the setting component. In this embodiment, the setting component is the reference resistor Rref, so the setting signal MSET is set according to the resistance of the reference resistor Rref. In other embodiments, the setting component may also be a capacitor, a diode, or the like. In other words, the user can change the setting characteristic signal MSET by changing the electrical characteristic value of the external setting component, for example, the resistance of the reference resistor Rref, and further, the pulse width modulation signal control device 100 is performed. Different mode settings.

In addition, when the selection signal SEL is at the second level (eg, a logic high level "1"), the signal adjustment and selection circuit 120 is now in the second state to couple the signal pin 110 to the core circuit 140. The core circuit 140 can operate normally according to the external input signal Vdd. In this embodiment, the core circuit 140 may be a so-called power good control circuit, that is, whether an output voltage of a conversion circuit (not shown) controlled by the pulse width modulation signal control device 100 has approached or risen to A stable, unchanging level is known to know if a good signal can be generated to inform other circuits to start operating.

The selection signal SEL is generated by the timing circuit 150. The timing circuit 150 performs timing based on the time point at which the operating power of the pulse width modulation signal control device 100 (in the present embodiment, the operating power source is equivalent to the external input signal Vdd) is supplied. When the timing result of the timer circuit 150 is less than a predetermined time period, the timer circuit 150 generates the selection signal SEL to cause the signal adjustment and selection circuit 120 to couple the signal pin 110 to the setting determination circuit 130 to transmit the setting signal MSET to The determination circuit 130 is set. In contrast, when the timing result of the timer circuit 150 is greater than or equal to the predetermined time period, the timer circuit 150 changes the generated selection signal SEL to cause the signal adjustment and selection circuit 120 to couple the signal pin 110 to the core circuit 140 to directly connect the external circuit. The signal Vdd is input to the core circuit 140.

More specifically, when the operating power supply of the pulse width modulation signal control device 100 has just started to rise to a stable state. At this time, the pulse width modulation signal control device 100 is just beginning to operate. Since the conversion circuit controlled by the pulse width modulation signal control device 100 has not yet started operating due to the mode configuration phase, the output voltage of the conversion circuit has not yet approached a predetermined voltage value, and the core circuit 140 does not need to operate. Here, the signal adjustment and selection circuit 120 transmits the setting signal MSET to the setting determination circuit 130 so that the setting determination circuit 130 operates against the comparison of the setting signal MSET and the reference value. After the timer circuit 150 has passed the preset time period, the setting determination circuit 130 is allowed to output the mode setting signal MODE_SET. At the same time, a conversion circuit controlled by the pulse width modulation signal control device 100 starts to operate, and the signal adjustment and selection circuit 120 directly connects the external input signal Vdd to the core circuit 140, so that the core circuit 140 can start to determine the output voltage. status. In this way, by a single signal pin 110, the mode setting of the pulse width modulation signal control device 100 and the original core circuit 140 and the like can be completed, and no additional pin needs to be added.

Here, the comparison operation of the setting determination circuit 130 compares the magnitude of the reference signal MSET with the reference value. When the reference value has only one value, the setting determination circuit 130 can obtain the setting determination result MODE_SET (for example, a signal for setting the determination result MODE_SET to be one bit) by setting the two modes by this comparison operation. Of course, if the reference value includes a plurality of values, the setting determination circuit 130 can obtain the setting determination result MODE_SET (for example, a signal for setting the determination result MODE_SET to be a plurality of bits) by which the more modes can be set by the comparison operation. The pulse width modulation signal control device 100 can determine the operation mode in the plurality of operation modes according to the setting determination result MODE_SET.

As a practical example, if the reference value has only one value V1, the setting judgment result MODE_SET which can set two modes can be obtained by setting whether the signal MSET is greater than the value V1. If the reference value includes two different values V1 and V2 and the value V1 is greater than V2, the three modes can be set by setting the signal MSET to be greater than the value V1, between the values V1 and V2, or less than the value V2. Set the judgment result MODE_SET.

It is worth mentioning that in order to make the setting judgment result MODE_SET generated by the setting judgment circuit 130 stable, when the timing of the timer circuit 150 reaches a predetermined time period, the shackle signal SETF is further generated. The shackle signal SETF is transmitted to the setting determination circuit 130, and the setting determination circuit 130 locks the setting determination result MODE_SET generated by the shackle signal SETF.

Referring to FIG. 2A, FIG. 2A is a schematic diagram of an embodiment of a pulse width modulation signal control apparatus 100. In the depiction of FIG. 2A, signal conditioning and selection circuit 120 includes voltage coupling element 121 and switching elements 122, 123. The voltage coupling element 121 is coupled to the signal pin 110 to receive the external input signal Vdd. The switching element 123 is connected in series between the voltage coupling element 121 and the reference voltage GND, and is controlled by the selection signal SEL1. The switching element 122 is connected in series between the core circuit 140 and the signal pin 110 and is controlled by the selection signal SEL2. Wherein, when the switching element 123 is turned on, the voltage coupling element 121 couples the voltage on the signal pin 110 to generate the setting signal MSET. Further, the switching elements 123 and 122 are not turned off at the same time. In the arrangement stage, the initial state switching element 122 and the switching element 123 are both turned on, and then the switching element 122 is turned off, indicating that the pulse width modulation signal control device 100 is performing the mode setting operation. In contrast, when the pulse width modulation signal control device 100 completes the mode setting operation, the switching element 122 is turned on to connect the external input signal Vdd to the core circuit 140, after which the switching element 123 is turned off.

The setting determination circuit 130 includes a comparator 131 and a shackle 132. The comparator 131 receives the setting signal MSET and the reference value Vref, and compares the setting signal MSET with the reference value Vref to generate a setting determination result MODE_SET. The shackle 132 is coupled to the comparator 131 to lock the determination result MODE_SET according to the shackle signal SETF.

2A and 2B, FIG. 2B is an operation waveform diagram of the embodiment of FIG. 2A. After the external input signal Vdd is stably supplied to the signal pin 110 and after a delay time Td, the timer circuit 150 starts the timing action according to the start count flag START. At this time, since the timing has not yet reached the predetermined time period, the voltage PGOOD on the signal pin 110 is adjusted to the setting signal MSET. At the same time, the timing circuit 150 generates a logic high level selection signal SEL2 to turn off the switching element 122, and causes the setting signal MSET to be coupled to the comparator 131 for comparison with the reference value Vref, and in turn to generate the setting determination result MODE_SET. When the timing of the timer circuit 150 reaches a predetermined time period, that is, at the critical time point TA, the timer circuit 150 generates a shackle signal SETF to lock the setting determination result MODE_SET, and generates a logic low level selection signal SEL2 to turn on the switch. Element 122, after which timing circuit 150 further generates a logic high level select signal SEL1 to turn off switching element 123 to cause external input signal Vdd to be directly coupled to core circuit 140.

Referring to FIG. 3, FIG. 3 is a schematic diagram of a pulse width modulation signal control apparatus 300 according to another embodiment of the present invention. The pulse width modulation signal control device 300 includes an analog bit converter 360 and a pulse width modulation signal generation in addition to the signal pin 310, the signal adjustment and selection circuit 320, the setting determination circuit 330, the core circuit 340, and the timing circuit 350. Circuit 370.

Different from the embodiment shown in FIG. 2A, the setting determination circuit 330 in this embodiment includes an analog digital conversion circuit 331, a temporary storage unit 332, and a processor 333. The analog digital conversion circuit 331 is coupled to the signal pin 310 to receive and convert the analog format setting signal MSET into a digital format setting signal dMSET. The register 332 is coupled to the analog digital conversion circuit 331 to receive the setting signal dMSET in the digital format. The register 332 is further coupled to the timer circuit 350 to receive the latch signal SETF and to lock the digital format setting signal dMSET by the latch signal SETF.

The processor 333 is coupled to the register 332 to receive the setting signal dMSET in the digit format locked by the register 332. The processor 333 is further coupled to the analog digital conversion circuit 360 and the pulse width modulation signal generating circuit 370. The analog digital conversion circuit 360 receives the feedback signal of the analog format, and the feedback signal is at least one of the feedback voltage VFB and the feedback current IFB. Here, the feedback voltage VFB and the feedback current IFB are voltage and current signals fed back by the output of the power conversion device (not shown) applied by the pulse width modulation signal control device 300.

The analog digital conversion circuit 360 converts at least one of the received feedback voltage VFB and the feedback current IFB into a digital format feedback voltage dVFB and a feedback current dIFB. The processor 333 receives at least one of the feedback voltage dVFB and the feedback current dIFB of the digital format to compare with the setting signal dMSET, and thereby determines whether the power conversion device has a phenomenon in which a so-called voltage or current abnormality occurs. Here, voltage anomalies include over voltage and under voltage, and current anomalies include over current and under current.

As a simple example, when the processor 333 determines that the set signal dMSET is greater than the feedback voltage dVFB, it indicates that the voltage is too low; when the set signal dMSET is smaller than the feedback voltage dVFB, it indicates that the voltage is too high; and the setting signal dMSET is greater than When the current dIFB is fed back, it indicates that the current is too low; when the setting signal dMSET is smaller than the feedback current dIFB, it indicates that the current is too high.

The processor 333 further generates the protection signal PROT according to the above-mentioned determined phenomenon, and the pulse width modulation signal generation circuit 370 enters the protection mode to stop the output pulse width modulation signal PWM_OUT when receiving the protection signal PROT generated by the processor 333.

Further, the signal adjustment and selection circuit 320 in this embodiment includes a current source 321 and switching elements 322, 323. In the configuration phase, the selection signals SEL1 and SEL2 both default to a low level, and when the timing circuit 350 does not reach the predetermined time period, the selection signal SEL2 is supplied to turn off the switching element 322 (at the same time, the selection signal SEL1 defaults to a low level). To turn on the switching element 323). At the same time, the current source 321 provides an adjustment current through the reference resistor Rref, and thereby adjusts the external input signal Vdd to the set signal MSET. In other words, the setting signal MSET can be set by the magnitude of the resistance of the reference resistor Rref. When the timing circuit 350 counts for a predetermined period of time, the timer circuit 350 provides the selection signal SEL2 to turn on the switching element 322, then supplies the selection signal SEL1 to turn off the switching element 323, and cuts off the flow path of the adjustment current provided by the current source 321. Then, the external input signal Vdd is transmitted to the core circuit 340 for normal operation.

Referring to FIGS. 4A-4C, FIGS. 4A-4C are schematic views respectively showing a power conversion device 400 according to three embodiments of the present invention. In the illustration of FIG. 4A, the power conversion device 400 includes a power conversion circuit 410 and a pulse width modulation signal control device 300. The pulse width modulation signal control device 300 is the embodiment shown in FIG. 3 . The power conversion circuit 410 is coupled to the pulse width modulation signal control device 300 to receive the pulse width modulation signal PWM_OUT generated by the pulse width modulation signal control device 300. The power conversion circuit 410 is a DC-to-DC power converter that receives the DC voltage VDC and performs power conversion by the PWM signal PWM_OUT to generate a DC output voltage VOUT.

Here, the pulse width modulation signal control device 300 can also be replaced with the pulse width modulation signal control device 200 illustrated in FIG. 2A. The DC to DC power converter 410 illustrated in FIG. 4A can also be replaced by other forms of DC to DC power converters.

In the depiction of FIG. 4B, the power conversion device 400 includes a power conversion circuit 420 and a pulse width modulation signal control device 300. The power conversion circuit 420 is coupled to the pulse width modulation signal control device 300 to receive the pulse width modulation signal PWM_OUT generated thereby. The power conversion circuit 420 is an AC-to-DC power converter that receives the AC voltage VAC and performs power conversion by the PWM signal PWM_OUT to generate a DC output voltage VOUT.

In the illustration of FIG. 4B, the pulse width modulation signal control device 300 can also be replaced with the pulse width modulation signal control device 200 illustrated in FIG. 2A. The AC to DC power converter 420 can also be replaced by other forms of AC to DC power converters.

In the illustration of FIG. 4C, the power conversion device 400 includes a power conversion circuit 430 and a pulse width modulation signal control device 300. The power conversion circuit 430 is coupled to the pulse width modulation signal control device 300 to receive the pulse width modulation signal PWM_OUT generated thereby. The power conversion circuit 430 is a DC-to-AC power converter that receives the DC voltage VDC and performs power conversion by the PWM signal PWM_OUT to generate an AC output voltage VOUT.

Similarly, in the illustration of FIG. 4C, the pulse width modulation signal control device 300 can also be replaced with the pulse width modulation signal control device 200 illustrated in FIG. 2A. The DC-to-AC power converter 430 can also be replaced by other types of DC-to-AC power converters.

In summary, the present invention utilizes a timer to time the signal pin to receive external input signals and set signals at different points in time. When the set signal is received at the signal pin, the mode setting action is completed. After the mode setting action is completed, the original action of the core circuit to which the original signal pin is connected is restored.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 300. . . Pulse width modulation signal control device

110, 310. . . Signal pin

120, 320. . . Signal adjustment and selection circuit

130, 330. . . Setting judgment circuit

140, 340. . . Core circuit

150, 350. . . Timing circuit

121. . . Voltage coupling element

122, 123, 322, 323. . . Switching element

131. . . Comparators

132. . . Shackle

360, 331. . . Analog digital converter

370. . . Pulse width modulation signal generating circuit

332. . . Register

333. . . processor

321. . . Battery

400. . . Power conversion device

410~430. . . Power conversion circuit

Vref. . . Reference

START. . . Starting count flag

Td. . . delay

PGOOD, VDC, VAC. . . Voltage

PROT. . . Protection signal

IFB, dIFB. . . Feedback current

VFB, dVFB. . . Feedback voltage

MSET, dMSET. . . Setting signal

SEL, SEL1, SEL2. . . Selection signal

Vdd‧‧‧ external input signal

Rref‧‧‧ reference resistor

MODE_SET‧‧‧Set judgment result

SETF‧‧‧ shackle signal

PWM_OUT‧‧‧ pulse width modulation signal

TA‧‧‧ critical time point

FIG. 1 is a schematic diagram of a pulse width modulation signal control apparatus 100 according to an embodiment of the present invention.

2A is a schematic diagram of an embodiment of a pulse width modulation signal control device 100.

2B is a diagram showing an operation waveform of the embodiment of FIG. 2A.

FIG. 3 is a schematic diagram of a pulse width modulation signal control apparatus 300 according to another embodiment of the present invention.

4A-4C are schematic views respectively showing a power conversion device 400 of three embodiments of the present invention.

100. . . Pulse width modulation signal control device

110. . . Signal pin

120. . . Signal adjustment and selection circuit

130. . . Setting judgment circuit

140. . . Core circuit

150. . . Timing circuit

MSET. . . Setting signal

SEL. . . Selection signal

Vdd. . . External input signal

Rref. . . Reference resistance

MODE_SET. . . Set judgment result

SETF. . . Shackle signal

Claims (12)

A pulse width modulation signal control device comprises: a signal pin, connected to a setting component for receiving an external input signal; a core circuit; a setting determining circuit, receiving a setting signal, comparing the setting signal with a reference And a signal adjustment and selection circuit coupled to the signal pin, wherein the signal adjustment and selection circuit is coupled to the signal pin to the setting determination circuit according to the first state The setting component adjusts the external input signal to the setting signal and when the second state is coupled to the signal pin to the core circuit, wherein the setting signal is generated according to the setting component; and a timing circuit coupled to the signal adjustment And selecting a circuit to control the state of the signal adjustment and selection circuit, wherein the timing circuit causes the signal adjustment and selection circuit to be in the first state for a predetermined period of time. The pulse width modulation signal control device of claim 1, wherein the setting determination circuit comprises: a comparator receiving the setting signal and the reference value, and comparing the setting signal with the reference value to generate the Set the judgment result. The pulse width modulation signal control device of claim 2, wherein the setting determining circuit further comprises: a latching device coupled to the comparator, wherein the timing circuit is located at the signal adjusting and selecting circuit A shackle signal is generated during the first state to lock the setting determination result. The pulse width modulation signal control device of claim 1, wherein the setting determining circuit comprises: a first analog digital converter coupled to the signal pin, receiving and converting the setting signal of the analog format a digital format; the processor receives the setting signal in a digital format, and compares the setting signal of the digital format with the reference value to generate the setting determination result; and a register coupled to the analog digital converter The setting signal in the digital format is locked according to a shackle signal. The pulse width modulation signal control device of claim 4, further comprising: a second analog-to-digital converter coupled to the processor, receiving a feedback signal of an analog format, and converting the feedback of the analog format The signal is in a digital format, wherein the feedback signal is at least one of a feedback voltage and a feedback current. The processor receives the feedback signal in a digital format and generates a protection signal according to the feedback signal in the digital format. The pulse width modulation signal control device of claim 5, further comprising: a pulse width modulation signal generation circuit coupled to the setting determination circuit, and determining whether to generate at least one pulse width adjustment according to the protection signal Change the signal. The pulse width modulation signal control device of claim 1, wherein the signal adjustment and selection circuit comprises: a first switching element coupled between the signal pin and a reference voltage; A second switching component is coupled between the core circuit and the signal pin. The pulse width modulation signal control device according to claim 1, wherein the setting component is a resistor. A power conversion device includes: at least one power conversion circuit; and a pulse width modulation signal control device coupled to the power conversion circuit for generating at least one pulse width modulation signal to control a power conversion operation of the power conversion circuit The pulse width modulation signal control device comprises: a signal pin, connected to a setting component for receiving an external input signal; a core circuit; a setting determining circuit, receiving a setting signal, comparing the setting signal with a reference And a signal adjustment and selection circuit coupled to the signal pin, wherein the signal adjustment and selection circuit is coupled to the signal pin to the setting determination circuit according to the first state The setting component adjusts the external input signal to the setting signal and when the second state is coupled to the signal pin to the core circuit, wherein the setting signal is generated according to the setting component; and a timing circuit coupled to the signal adjustment And selecting a circuit to control the state of the signal adjustment and selection circuit, wherein the timing circuit is for a predetermined period of time The signal adjustment and the selection circuit is in the first state. The power conversion device of claim 9, wherein the pulse width modulation signal control device has a plurality of operation modes, and The result of the setting determination determines the operation in the corresponding operation mode. The power conversion device of claim 9, wherein the pulse width modulation signal control device receives a feedback signal, and determines whether to stop generating the at least one pulse width modulation signal according to the feedback signal and the setting determination result. . The power conversion device of claim 11, wherein the power conversion circuit is a DC-to-DC power conversion circuit, a DC-to-AC power conversion circuit, or an AC-to-DC power conversion circuit.