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TW201413847A - 銅柱導線直連結構與其形成方法 - Google Patents

銅柱導線直連結構與其形成方法 Download PDF

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TW201413847A
TW201413847A TW102129623A TW102129623A TW201413847A TW 201413847 A TW201413847 A TW 201413847A TW 102129623 A TW102129623 A TW 102129623A TW 102129623 A TW102129623 A TW 102129623A TW 201413847 A TW201413847 A TW 201413847A
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metal
bump
substrate
direct connection
solder joint
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TWI529830B (zh
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陳冠宇
林育蔚
曾裕仁
郭庭豪
陳承先
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台灣積體電路製造股份有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

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Abstract

本發明提供一種銅柱導線直連(bump on trace,BOT)結構，包括：一接觸組件受到一積體電路支撐；一凸塊下方金屬化層(UBM)特徵結構電性耦合到該接觸組件；一金屬凸塊位於該凸塊下方金屬化層(UBM)特徵結構之上；以及一基板導線位於一基板之上，其中該基板導線藉由一焊料接合部份與一金屬層間化合物(IMCs)耦合到該金屬凸塊，其中該金屬層間化合物(IMCs)的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。

Description

銅柱導線直連結構與其形成方法
本發明係有關於一種半導體結構，且特別是有關於一種銅柱導線直連結構與其形成方法。
在封裝逐漸縮小以及輸入/輸出計數(input/output counts)逐漸升高的趨勢之下，覆晶銅柱導線直連(bump on trace,BOT)封裝需要更為精細的間距(finer pitch)。因為對精細間距的要求，導致凸塊尺寸縮小。如此一來，金屬/焊料界面(金屬凸塊)以及焊料/導線接合界面的面積也隨之縮小。因此，由於電流密度較高，在「凸塊對導線」(bump-to-trace)與「導線對凸塊」(trace-to-bump)之位置的電遷移(electromigration,EM)阻抗性因而劣化。
本發明提供一種銅柱導線直連(bump on trace,BOT)結構，包括：一接觸組件受到一積體電路支撐；一凸塊下方金屬化層(UBM)特徵結構電性耦合到該接觸組件；一金屬凸塊位於該凸塊下方金屬化層(UBM)特徵結構之上；以及一基板導線位於一基板之上，其中該基板導線藉由一焊料接合部份與一金屬層間化合物(IMCs)耦合到該金屬凸塊，其中該金屬層間 化合物(IMCs)的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
本發明另提供一種銅柱導線直連結構，包括：一 接觸組件受到一積體電路支撐；一凸塊下方金屬化層(UBM)特徵結構電性耦合到該接觸組件；一金屬凸塊位於該凸塊下方金屬化層(UBM)特徵結構之上；一基板導線位於一基板之上；金屬層間化合物(IMCs)設置於該金屬凸塊與該基板導線之上；以及一焊料接合部份形成於，介於設置於該金屬凸塊之上與設置於該基板導線之上的該金屬層間化合物(IMCs)之間，其中該金屬層間化合物(IMCs)的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
本發明亦提供一種銅柱導線直連結構之形成方 法，包括：形成一接觸組件於一積體電路之上；電性耦合一凸塊下方金屬化層(UBM)特徵結構到該接觸組件；形成一金屬凸塊於該凸塊下方金屬化層(UBM)特徵結構之上；形成一基板導線於一基板之上；以及藉由一焊料接合部份與一金屬層間化合物(IMCs)耦合該基板導線到該金屬凸塊，其中該金屬層間化合物形成於該基板導線與該金屬凸塊之間，其中該金屬層間化合物的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
10‧‧‧銅柱導線直連(bump on trace,BOT)結構
12‧‧‧接觸組件(contact element)
14‧‧‧凸塊下方金屬化(under bump metallurgy,UBM)特徵結構
16‧‧‧金屬凸塊
18‧‧‧基板導線(substrate trace)
20‧‧‧基板
22‧‧‧焊料接合部份(solder joint)
24‧‧‧金屬層間化合物(intermetallic compounds,IMCs)
26‧‧‧積體電路
28‧‧‧絕緣層
30‧‧‧鈍化層
32‧‧‧聚亞醯胺(polyimide)層
34‧‧‧團塊
36‧‧‧金屬凸塊之側壁
38‧‧‧金屬凸塊之底部寬度
40‧‧‧金屬凸塊之頂部寬度
42‧‧‧金屬氧化物
50‧‧‧形成銅柱導線直連(BOT)結構之方法
52‧‧‧形成接觸組件於晶片之上
54‧‧‧耦合凸塊下方金屬化(UBM)特徵結構到接觸組件
56‧‧‧設置金屬凸塊於凸塊下方金屬化(UBM)特徵結構之上
58‧‧‧設置基板導線於基板之上
60‧‧‧耦合基板導線到金屬凸塊，以使金屬層間化合物(IMCs)的橫截面面積對焊料接合部份的橫截面面積之比例大於40%
第1圖為一剖面圖，其顯示本發明一實施例之銅柱導線直連(bump on trace,BOT)結構。
第2圖為一剖面圖，其顯示適用於第1圖的銅柱導線直連(bump on trace,BOT)結構的金屬凸塊。
第3圖為一剖面圖，其顯示適用於第1圖的銅柱導線直連(bump on trace,BOT)結構的金屬凸塊。
第4圖為一平面圖，其顯示第1圖的銅柱導線直連(bump on trace,BOT)結構的金屬凸塊具有各種周邊形狀。
第5圖顯示第1圖的銅柱導線直連(bump on trace,BOT)結構的形成方法。
本發明將藉由一些較佳實施例描述名為銅柱導線直連(bump on trace,BOT)的凸塊結構。然而，本發明所揭露的概念也可以適用於其他半導體結構或電路。
現在請參照第1圖，其顯示銅柱導線直連(BOT)結構10的實施例。如圖所示，銅柱導線直連(BOT)結構體10包括接觸組件(contact element)12、凸塊下方金屬化(under bump metallurgy,UBM)特徵結構14、金屬凸塊16、基板導線(substrate trace)18、基板20、焊料接合部份(solder joint)22以及金屬層間化合物(intermetallic compounds,IMCs)24。
在一實施例中，接觸組件12為一鋁墊。如第1圖所示，接觸組件12通常是受到積體電路26(亦即，晶片)所支撐。為了清晰而便於說明，積體電路26的各個層狀結構及特徵結構，包括電晶體(transistors)、互連層狀結構(interconnect layers)、鈍化後互連結構(post passivation interconnects)、重新分配層(redistribution layers)以及類似的結構等等受到省略 而未顯示於圖式中，因為這些結構對於理解本發明所揭露的內容並非必要。
在一實施例中，設置絕緣層28於接觸組件12及 積體電路26之間。在一實施例中，絕緣層28包括極低介電常數(extremely low-k,ELK)介電材料。在一實施例中，鈍化層30覆蓋於積體電路26(及/或絕緣層28)之上。如第1圖所示，鈍化層30可具有一個暴露出接觸組件12的鈍化層開口。在一實施例中，聚亞醯胺(polyimide)層32覆蓋於鈍化層30之上。 聚亞醯胺層32可具有一個暴露出接觸組件12的聚亞醯胺(polyimide)開口。
仍請參照第1圖，凸塊下方金屬化特徵結構14電 性耦合到接觸組件12。在一實施例中，凸塊下方金屬化特徵結構14由下列材料所形成，包括：鈦(titanium,Ti)、氮化鈦(titanium nitride,TiN)、銅鎳合金(copper nickel)、鋁(aluminum,Al)以及類似之材料，凸塊下方金屬化特徵結構14具有一厚度介於約0.1-5μm，端視其應用領域而定。如圖所示，各種層狀構造包括，例如，鈍化層及聚亞醯胺層，可設置在部份的凸塊下方金屬化特徵結構14及接觸組件12之間。
仍請參照第1圖，金屬凸塊16設置於凸塊下方金 屬化特徵結構14之上。舉例而言，在一實施例中，金屬凸塊16由合適的材料形成，例如，銅(copper,Cu)、鎳(nickel,Ni)、金(gold,Au)、鈀(palladium,Pd)、鈦(titanium,Ti)、類似之材料或上述材料之合金。
如第1圖所示，基板導線18通常設置於基板20 之上。在一實施例中，基板導線18由下列材料所形成，包括銅(copper,Cu)、鎳(nickel,Ni)、金(gold,Au)、鋁(aluminum,Al)、銀(silver Ag)、類似之材料或上述材料之合金。舉例而言，在一實施例中，基板導線18可經過表面處理，在其表面塗佈，例如，有機可焊性防腐劑(organic solderability preservatives,OSP)、浸漬錫(immersion tin,IT)等等。
仍請參照第1圖，藉由焊料接合部份22及金屬層 間化合物(IMCs)24，基板導線18結構耦合及/或電性耦合到金屬凸塊16。在一實施例中，焊料接合部份22包括錫(tin,Sn)、鉛(lead,Pb)或其他合適的焊料材料。
在一實施例中，金屬層間化合物(IMCs)24的橫截 面面積對焊料接合部份22的橫截面面積之比例約大於40%以上。換言之，在第1圖中，金屬層間化合物(IMCs)24的兩個間隔分開部份所佔據的面積，在耦合金屬凸塊16到基板導線18之團塊(conglomeration)34的總面積之中約佔大於40%。此外，焊料接合部份22所佔據的面積在團塊34的總面積之中約佔小於60%。
所期望之金屬層間化合物(IMCs)24對焊料接合部 份22的比例，可藉由下列方式獲得，例如，減少焊料接合部份22的垂直高度。也可藉由下列方式實現所需的金屬層間化合物(IMCs)24對焊料接合部份22的比例，增加晶粒接合期間的熱積存量(thermal budget)，以產生更多與焊料接合部份22相對應的金屬層間化合物(IMCs)24。本發明所屬技術領域具有通常知識者應可了解，可藉由調控其他製程參數或尺寸而得到 該比例。
藉由保持金屬層間化合物(IMCs)24對焊料接合部 份22的比例超過40%，銅柱導線直連(BOT)結構10之電遷移(electromigration,EM)阻抗性(resistance)增加。相較於在傳統BOT元件中單獨存在焊料接合部份22時的擴散係數，金屬層間化合物(IMCs)24及焊料接合部份22之組合的擴散係數較低，因而造成上述現象。事實上，在第1圖中的金屬層間化合物(IMCs)24/焊料接合部份22的組合具有較低的擴散係數，因此導致原子通量(atomic flux)較低，其中原子通量較低將造成較慢的電遷移失效時間(electromigration failure time)。
在一實施例中，團塊34包括一額外的金屬層或材 料(圖中未顯示)。舉例而言，此額外的金屬層或材料可設置在介於金屬凸塊16及焊料接合部份22及/或金屬層間化合物(IMCs)24之間。在這種情況下，藉由焊料接合部份22、金屬層間化合物(IMCs)24以及額外的金屬，使基板導線18耦合到金屬凸塊16。在一實施例中，額外的金屬可以是鎳(nickel,Ni)或其他導電材料。
現在請參照第2圖，金屬凸塊16可以是垂直的凸 塊。因此，金屬凸塊16的側壁36可以是垂直的(依第2圖中的方向)。在此一實施例中，金屬凸塊16的頂部寬度40與底部寬度38是相同的。如第2圖所示，在一實施例中，金屬氧化物42(例如，氧化銅(cupric oxide,CuO)、氧化亞銅(cuprous oxide,Cu2O)、氧化鋁(aluminum oxide,Al2O3)等等)形成於金屬凸塊16的側壁36上。
如第3圖所示，金屬凸塊16亦可以是階梯狀凸塊 (ladder bump)。如此一來，金屬凸塊16具有傾斜的(sloped)或錐形的(tapering)縱向剖面。事實上，金屬凸塊16通常具有一個頂端截除圓錐體(truncated cone)的形狀。在一實施例中，沿著金屬凸塊16的側壁36之整個高度(亦即，或是長度)，從遠側端部(此為最接近團塊34的部份)到設置端部(mounted end)的範圍內，金屬凸塊16的側壁36保持線性。如第3圖所示，在一實施例中，金屬凸塊16亦包括金屬氧化物42於側壁36上。相較於未經塗覆的側壁，金屬氧化物42可提供側壁36與模造成形材料(molding material)或底部填充材料(nderfill material)之間較佳的黏著性。
仍請參照第3圖，在一實施例中，金屬凸塊16的 底部寬度38大於金屬凸塊16的頂部寬度40，其中金屬凸塊16的底部寬度38是最接近積體電路26(第1圖)的部份，而金屬凸塊16的頂部寬度40是最遠離積體電路26的部份。在一實施例中，頂部寬度40介於約10-80μm之間。在一實施例中，底部的寬度38介於約20-90μm之間。在一實施例中，對第3圖中之金屬凸塊16而言，頂部寬度40對底部寬度38的比例介於約0.5-0.89之間。
本發明所屬技術領域具有通常知識者應可了解， 本文所討論的各種寬度及間隔的具體尺寸是基於設計選擇的考量，並且取決於所需的特定技術節點(technology node)以及所屬應用領域。
在一實施例中，利用微影製程(photolithography process)形成金屬凸塊16，如第3圖所示。事實上，在微影製程中，可適當地將光阻塑形，以產生如第3圖所示之金屬凸塊16的形狀。在一實施例中，可利用電鍍(electrolytic plating)製程形成金屬凸塊16。
現在請參照第4圖，當從上方觀察時，金屬凸塊 16的周邊可能呈現或類似於各種不同的形狀。在一實施例中，當從在第1圖中之積體電路26的設置端點(mounted end)進行觀察時，金屬凸塊16的形狀為圓形(circle)、矩形(rectangle)、橢圓形(ellipse)、長圓形(obround)、六邊形(hexagon)、八邊形(octagon)、梯形(trapezoid)、菱形(diamond)、膠囊形(capsule)以及上述形狀之組合。在第4圖中，所顯示的金屬凸塊16周邊形狀與第1圖的底層金屬基板導線18相關。
現在請參照第5圖，提供方法50的實施例，方法 50係用以形成如第1圖所示的銅柱導線直連(BOT)結構10。在步驟52中，形成接觸組件12於積體電路26之上。在步驟54中，凸塊下方金屬化(UBM)特徵結構14電性耦合到接觸組件12。在步驟56中，設置金屬凸塊16於凸塊下方金屬化(UBM)特徵結構14之上。在步驟58中，設置基板導線18於基板20之上。在步驟60中，利用焊料接合部份22及金屬層間化合物(IMCs)24耦合基板導線18到金屬凸塊16，使金屬層間化合物(IMCs)24的橫截面面積對焊料接合部份22的橫截面面積之比例大於40%。
從上文應可了解，實施例中的銅柱導線直連(BOT) 結構10提供許多有利的特徵。例如，銅柱導線直連(BOT)結構 10允許精細的間距配置，同時仍可提供較高的電遷移阻抗性(electromigration resistance)，這是因為與單獨存在的焊料相比，焊料接合部份22及金屬層間化合物(IMCs)24的團塊34具有較低的擴散係數。因此，電遷移失效的時間較慢。
以下的引用文獻與本發明的主題相關。這些引用文獻之全部內容皆透過引用方式併入本文：‧美國專利公開號：2011/0285023，沈，等人。2011年11月24日，題目為「具有不同尺寸的基板互連結構(substrate interconnections having different sizes)」
在一實施例中，提供一種銅柱導線直連(BOT)結構，包括：一接觸組件受到一積體電路支撐，一凸塊下方金屬化層(UBM)特徵結構電性耦合到該接觸組件，一金屬凸塊位於該凸塊下方金屬化層(UBM)特徵結構之上，以及一基板導線位於一基板之上，其中該基板導線藉由一焊料接合部份及一金屬層間化合物(IMCs)耦合到該金屬凸塊，其中該金屬層間化合物(IMCs)的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
在一實施例中，提供一種銅柱導線直連(BOT)結構，包括：一接觸組件受到一積體電路支撐，一凸塊下方金屬化層(UBM)特徵結構電性耦合到該接觸組件，一金屬凸塊位於該凸塊下方金屬化層(UBM)特徵結構之上，一基板導線位於一基板之上，金屬層間化合物(IMCs)位於該金屬凸塊與該基板導線之上，以及一焊料接合部份形成在介於設置於該金屬凸塊之上與設置於該基板導線之上的該金屬層間化合物(IMCs)之 間，其中該金屬層間化合物(IMCs)的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
在一實施例中，提供一種銅柱導線直連(BOT)結構 之形成方法，包括：形成一接觸組件於一積體電路之上，電性耦合一凸塊下方金屬化層(UBM)特徵結構到該接觸組件，形成一金屬凸塊於該凸塊下方金屬化層(UBM)特徵結構之上，形成一基板導線於一基板之上，以及藉由一焊料接合部份及一金屬層間化合物(IMCs)耦合該基板導線到該金屬凸塊，其中該金屬層間化合物形成於該基板導線與該金屬凸塊之間，其中該金屬層間化合物的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
10‧‧‧銅柱導線直連(bump on trace,BOT)結構
12‧‧‧接觸組件(contact element)
14‧‧‧凸塊下方金屬化(under bump metallurgy,UBM)特徵結構
16‧‧‧金屬凸塊
18‧‧‧基板導線(substrate trace)
20‧‧‧基板
22‧‧‧焊料接合部份(solder joint)
24‧‧‧金屬層間化合物(intermetallic compounds,IMCs)
26‧‧‧積體電路
28‧‧‧絕緣層
30‧‧‧鈍化層
32‧‧‧聚亞醯胺(polyimide)層
34‧‧‧團塊

Claims (10)

  1. 一種銅柱導線直連(bump on trace,BOT)結構，包括：一接觸組件受到一積體電路支撐；一凸塊下方金屬化層(UBM)特徵結構電性耦合到該接觸組件；一金屬凸塊位於該凸塊下方金屬化層(UBM)特徵結構之上；以及一基板導線位於一基板之上，其中該基板導線藉由一焊料接合部份與一金屬層間化合物(IMCs)耦合到該金屬凸塊，其中該金屬層間化合物(IMCs)的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
  2. 如申請專利範圍第1項所述之銅柱導線直連結構，其中該金屬凸塊具有一非錐形的(non-tapering)或錐形的(tapering)縱向剖面。
  3. 如申請專利範圍第1項所述之銅柱導線直連結構，其中該金屬凸塊的一底部寬度等於或大於該金屬凸塊的一頂部寬度。
  4. 如申請專利範圍第1項所述之銅柱導線直連結構，其中該金屬凸塊的一頂部寬度對該金屬凸塊的一底部寬度之比例介於約0.5-0.89之間。
  5. 如申請專利範圍第1項所述之銅柱導線直連結構，其中該金屬凸塊的側壁受到一金屬氧化物的塗佈。
  6. 如申請專利範圍第1項所述之銅柱導線直連結構，其中該基板導線經過一表面處理步驟。
  7. 如申請專利範圍第1項所述之銅柱導線直連結構，其中該基板導線藉由焊料接合部份、金屬層間化合物(IMCs)以及一額外的金屬耦合到該金屬凸塊，其中該額外的金屬設置在介於該金屬凸塊及該焊料接合部份之間。
  8. 一種銅柱導線直連結構之形成方法，包括：形成一接觸組件於一積體電路之上；電性耦合一凸塊下方金屬化層(UBM)特徵結構到該接觸組件；形成一金屬凸塊於該凸塊下方金屬化層(UBM)特徵結構之上；形成一基板導線於一基板之上；以及藉由一焊料接合部份與一金屬層間化合物(IMCs)耦合該基板導線到該金屬凸塊，其中該金屬層間化合物形成於該基板導線與該金屬凸塊之間，其中該金屬層間化合物的一第一橫截面面積對該焊料接合部份的一第二橫截面面積之比例大於40%。
  9. 如申請專利範圍第8項所述之銅柱導線直連結構之形成方法，尚包括設置一額外的金屬介於該金屬凸塊及該焊料接合部份之間。
  10. 如申請專利範圍第8項所述之銅柱導線直連結構之形成方法，其中該金屬凸塊具有一錐形的(tapering)縱向剖面具有金屬氧化物於側壁之上。
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